From fc03ac055e87efe978f7f02959038f71f8615bd3 Mon Sep 17 00:00:00 2001
From: adrizcorp <adrizcorp@gmail.com>
Date: Fri, 20 Oct 2023 19:58:14 -0700
Subject: [PATCH] Working 10G hw for ZCu106

---
 Docs/Possible_Improvements/pl_eth_10g.pdf     |   5811 +
 src/constraints/constraints.xdc               |     45 +
 .../pl_eth_10g.cache/wt/gui_handlers.wdf      |     46 +
 .../wt/java_command_handlers.wdf              |     22 +
 .../pl_eth_10g.cache/wt/project.wpc           |      3 +
 .../pl_eth_10g.cache/wt/synthesis.wdf         |     39 +
 .../pl_eth_10g.cache/wt/synthesis_details.wdf |      3 +
 .../pl_eth_10g.cache/wt/webtalk_pa.xml        |     94 +
 .../bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v    |     44 +
 .../bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh   |  14004 +
 .../pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl   |   2060 +
 .../pl_eth_10g_auto_cc_0.xml                  |   4681 +
 .../pl_eth_10g_auto_cc_0_clocks.xdc           |     33 +
 .../pl_eth_10g_auto_cc_0_ooc.xdc              |     49 +
 .../sim/pl_eth_10g_auto_cc_0.cpp              |   1016 +
 .../sim/pl_eth_10g_auto_cc_0.h                |    460 +
 .../sim/pl_eth_10g_auto_cc_0.v                |    290 +
 .../sim/pl_eth_10g_auto_cc_0_sc.cpp           |     97 +
 .../sim/pl_eth_10g_auto_cc_0_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_cc_0_stub.sv          |    194 +
 .../synth/pl_eth_10g_auto_cc_0.v              |    292 +
 .../sysc/axi_clock_converter.cpp              |     24 +
 .../sysc/axi_clock_converter.h                |     27 +
 .../pl_eth_10g_auto_cc_1.xml                  |   4681 +
 .../pl_eth_10g_auto_cc_1_clocks.xdc           |     33 +
 .../pl_eth_10g_auto_cc_1_ooc.xdc              |     49 +
 .../sim/pl_eth_10g_auto_cc_1.cpp              |   1046 +
 .../sim/pl_eth_10g_auto_cc_1.h                |    490 +
 .../sim/pl_eth_10g_auto_cc_1.v                |    308 +
 .../sim/pl_eth_10g_auto_cc_1_sc.cpp           |     97 +
 .../sim/pl_eth_10g_auto_cc_1_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_cc_1_stub.sv          |    212 +
 .../synth/pl_eth_10g_auto_cc_1.v              |    310 +
 .../sysc/axi_clock_converter.cpp              |     24 +
 .../sysc/axi_clock_converter.h                |     27 +
 .../pl_eth_10g_auto_ds_0.xml                  |   4382 +
 .../pl_eth_10g_auto_ds_0_clocks.xdc           |      7 +
 .../pl_eth_10g_auto_ds_0_ooc.xdc              |     49 +
 .../sim/pl_eth_10g_auto_ds_0.cpp              |   1242 +
 .../sim/pl_eth_10g_auto_ds_0.h                |    668 +
 .../sim/pl_eth_10g_auto_ds_0.v                |    391 +
 .../sim/pl_eth_10g_auto_ds_0_sc.cpp           |     96 +
 .../sim/pl_eth_10g_auto_ds_0_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_ds_0_stub.sv          |    314 +
 .../src/axi_dwidth_converter.cpp              |    527 +
 .../src/axi_dwidth_converter.h                |    116 +
 .../synth/pl_eth_10g_auto_ds_0.v              |    393 +
 .../pl_eth_10g_auto_ds_1.xml                  |   4382 +
 .../pl_eth_10g_auto_ds_1_clocks.xdc           |      7 +
 .../pl_eth_10g_auto_ds_1_ooc.xdc              |     49 +
 .../sim/pl_eth_10g_auto_ds_1.cpp              |   1242 +
 .../sim/pl_eth_10g_auto_ds_1.h                |    668 +
 .../sim/pl_eth_10g_auto_ds_1.v                |    391 +
 .../sim/pl_eth_10g_auto_ds_1_sc.cpp           |     96 +
 .../sim/pl_eth_10g_auto_ds_1_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_ds_1_stub.sv          |    314 +
 .../src/axi_dwidth_converter.cpp              |    527 +
 .../src/axi_dwidth_converter.h                |    116 +
 .../synth/pl_eth_10g_auto_ds_1.v              |    393 +
 .../pl_eth_10g_auto_pc_0.xml                  |   4557 +
 .../pl_eth_10g_auto_pc_0_ooc.xdc              |     50 +
 .../sim/pl_eth_10g_auto_pc_0.cpp              |   1090 +
 .../sim/pl_eth_10g_auto_pc_0.h                |    538 +
 .../sim/pl_eth_10g_auto_pc_0.v                |    345 +
 .../sim/pl_eth_10g_auto_pc_0_sc.cpp           |     96 +
 .../sim/pl_eth_10g_auto_pc_0_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_pc_0_stub.sv          |    254 +
 .../src/axi_protocol_converter.cpp            |     25 +
 .../src/axi_protocol_converter.h              |     24 +
 .../synth/pl_eth_10g_auto_pc_0.v              |    347 +
 .../pl_eth_10g_auto_pc_1.xml                  |   4557 +
 .../pl_eth_10g_auto_pc_1_ooc.xdc              |     50 +
 .../sim/pl_eth_10g_auto_pc_1.cpp              |   1089 +
 .../sim/pl_eth_10g_auto_pc_1.h                |    538 +
 .../sim/pl_eth_10g_auto_pc_1.v                |    345 +
 .../sim/pl_eth_10g_auto_pc_1_sc.cpp           |     96 +
 .../sim/pl_eth_10g_auto_pc_1_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_pc_1_stub.sv          |    254 +
 .../src/axi_protocol_converter.cpp            |     25 +
 .../src/axi_protocol_converter.h              |     24 +
 .../synth/pl_eth_10g_auto_pc_1.v              |    347 +
 .../pl_eth_10g_auto_us_0.xml                  |   4382 +
 .../pl_eth_10g_auto_us_0_clocks.xdc           |      7 +
 .../pl_eth_10g_auto_us_0_ooc.xdc              |     49 +
 .../sim/pl_eth_10g_auto_us_0.cpp              |   1222 +
 .../sim/pl_eth_10g_auto_us_0.h                |    648 +
 .../sim/pl_eth_10g_auto_us_0.v                |    379 +
 .../sim/pl_eth_10g_auto_us_0_sc.cpp           |     96 +
 .../sim/pl_eth_10g_auto_us_0_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_us_0_stub.sv          |    302 +
 .../src/axi_dwidth_converter.cpp              |    527 +
 .../src/axi_dwidth_converter.h                |    116 +
 .../synth/pl_eth_10g_auto_us_0.v              |    381 +
 .../pl_eth_10g_auto_us_1.xml                  |   4382 +
 .../pl_eth_10g_auto_us_1_clocks.xdc           |      7 +
 .../pl_eth_10g_auto_us_1_ooc.xdc              |     49 +
 .../sim/pl_eth_10g_auto_us_1.cpp              |   1006 +
 .../sim/pl_eth_10g_auto_us_1.h                |    450 +
 .../sim/pl_eth_10g_auto_us_1.v                |    265 +
 .../sim/pl_eth_10g_auto_us_1_sc.cpp           |     96 +
 .../sim/pl_eth_10g_auto_us_1_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_us_1_stub.sv          |    188 +
 .../src/axi_dwidth_converter.cpp              |    527 +
 .../src/axi_dwidth_converter.h                |    116 +
 .../synth/pl_eth_10g_auto_us_1.v              |    267 +
 .../pl_eth_10g_auto_us_2.xml                  |   4382 +
 .../pl_eth_10g_auto_us_2_clocks.xdc           |      7 +
 .../pl_eth_10g_auto_us_2_ooc.xdc              |     49 +
 .../sim/pl_eth_10g_auto_us_2.cpp              |   1036 +
 .../sim/pl_eth_10g_auto_us_2.h                |    480 +
 .../sim/pl_eth_10g_auto_us_2.v                |    283 +
 .../sim/pl_eth_10g_auto_us_2_sc.cpp           |     96 +
 .../sim/pl_eth_10g_auto_us_2_sc.h             |     98 +
 .../sim/pl_eth_10g_auto_us_2_stub.sv          |    206 +
 .../src/axi_dwidth_converter.cpp              |    527 +
 .../src/axi_dwidth_converter.h                |    116 +
 .../synth/pl_eth_10g_auto_us_2.v              |    285 +
 .../pl_eth_10g_axi_dma_0_0.xdc                |     65 +
 .../pl_eth_10g_axi_dma_0_0.xml                |   8893 +
 .../pl_eth_10g_axi_dma_0_0_clocks.xdc         |     46 +
 .../sim/pl_eth_10g_axi_dma_0_0.vhd            |    569 +
 .../synth/pl_eth_10g_axi_dma_0_0.vhd          |    576 +
 .../pl_eth_10g_axi_pl_ps_0.xml                |   1645 +
 .../pl_eth_10g_dma_rx_rst_0.xml               |    270 +
 .../sim/pl_eth_10g_dma_rx_rst_0.v             |     72 +
 .../synth/pl_eth_10g_dma_rx_rst_0.v           |     73 +
 .../pl_eth_10g_dma_tx_rst_0.xml               |    270 +
 .../sim/pl_eth_10g_dma_tx_rst_0.v             |     72 +
 .../synth/pl_eth_10g_dma_tx_rst_0.v           |     73 +
 .../pl_eth_10g_ps_axi_periph_0.xml            |   1644 +
 .../pl_eth_10g_rst_ps8_0_99M_0.xdc            |     49 +
 .../pl_eth_10g_rst_ps8_0_99M_0.xml            |    897 +
 .../pl_eth_10g_rst_ps8_0_99M_0_board.xdc      |      2 +
 .../sim/pl_eth_10g_rst_ps8_0_99M_0.vhd        |    147 +
 .../synth/pl_eth_10g_rst_ps8_0_99M_0.vhd      |    153 +
 .../pl_eth_10g_rx_data_fifo_0.xml             |   2074 +
 .../sim/pl_eth_10g_rx_data_fifo_0.v           |    162 +
 .../synth/pl_eth_10g_rx_data_fifo_0.v         |    164 +
 .../pl_eth_10g_rx_rst_n_0.xml                 |    270 +
 .../sim/pl_eth_10g_rx_rst_n_0.v               |     72 +
 .../synth/pl_eth_10g_rx_rst_n_0.v             |     73 +
 .../pl_eth_10g_s00_mmu_0.xml                  |   7873 +
 .../sim/pl_eth_10g_s00_mmu_0.v                |    385 +
 .../synth/pl_eth_10g_s00_mmu_0.v              |    387 +
 .../pl_eth_10g_s01_mmu_0.xml                  |   7873 +
 .../sim/pl_eth_10g_s01_mmu_0.v                |    277 +
 .../synth/pl_eth_10g_s01_mmu_0.v              |    279 +
 .../pl_eth_10g_s02_mmu_0.xml                  |   7875 +
 .../sim/pl_eth_10g_s02_mmu_0.v                |    295 +
 .../synth/pl_eth_10g_s02_mmu_0.v              |    297 +
 .../pl_eth_10g_sfp_tx_dis_0.xml               |    273 +
 .../sim/pl_eth_10g_sfp_tx_dis_0.cpp           |     73 +
 .../sim/pl_eth_10g_sfp_tx_dis_0.h             |     65 +
 .../sim/pl_eth_10g_sfp_tx_dis_0.v             |     68 +
 .../sim/pl_eth_10g_sfp_tx_dis_0_stub.sv       |     86 +
 .../sim/xlconstant_v1_1_7.h                   |     69 +
 .../synth/pl_eth_10g_sfp_tx_dis_0.v           |     69 +
 .../pl_eth_10g_tx_data_fifo_0.xml             |   2074 +
 .../sim/pl_eth_10g_tx_data_fifo_0.v           |    156 +
 .../synth/pl_eth_10g_tx_data_fifo_0.v         |    158 +
 .../pl_eth_10g_tx_rst_n_0.xml                 |    270 +
 .../sim/pl_eth_10g_tx_rst_n_0.v               |     72 +
 .../synth/pl_eth_10g_tx_rst_n_0.v             |     73 +
 .../pl_eth_10g_util_vector_logic_0_0.xml      |    270 +
 .../sim/pl_eth_10g_util_vector_logic_0_0.v    |     72 +
 .../synth/pl_eth_10g_util_vector_logic_0_0.v  |     73 +
 .../pl_eth_10g_xbar_0/pl_eth_10g_xbar_0.xml   |  47754 ++++
 .../sim/pl_eth_10g_xbar_0.cpp                 |   6705 +
 .../pl_eth_10g_xbar_0/sim/pl_eth_10g_xbar_0.h |   2851 +
 .../pl_eth_10g_xbar_0/sim/pl_eth_10g_xbar_0.v |    424 +
 .../sim/pl_eth_10g_xbar_0_sc.cpp              |    113 +
 .../sim/pl_eth_10g_xbar_0_sc.h                |    102 +
 .../sim/pl_eth_10g_xbar_0_stub.sv             |    320 +
 .../ip/pl_eth_10g_xbar_0/src/axi_crossbar.cpp |    269 +
 .../ip/pl_eth_10g_xbar_0/src/axi_crossbar.h   |     85 +
 .../synth/pl_eth_10g_xbar_0.v                 |    427 +
 .../pl_eth_10g_xbar_1/pl_eth_10g_xbar_1.xml   |  47724 ++++
 .../sim/pl_eth_10g_xbar_1.cpp                 |   7051 +
 .../pl_eth_10g_xbar_1/sim/pl_eth_10g_xbar_1.h |   3081 +
 .../pl_eth_10g_xbar_1/sim/pl_eth_10g_xbar_1.v |    436 +
 .../sim/pl_eth_10g_xbar_1_sc.cpp              |    113 +
 .../sim/pl_eth_10g_xbar_1_sc.h                |    102 +
 .../sim/pl_eth_10g_xbar_1_stub.sv             |    332 +
 .../ip/pl_eth_10g_xbar_1/src/axi_crossbar.cpp |    269 +
 .../ip/pl_eth_10g_xbar_1/src/axi_crossbar.h   |     85 +
 .../synth/pl_eth_10g_xbar_1.v                 |    439 +
 .../pl_eth_10g_xlconcat_0_0.xml               |   5065 +
 .../sim/pl_eth_10g_xlconcat_0_0.v             |    328 +
 .../synth/pl_eth_10g_xlconcat_0_0.v           |    332 +
 .../pl_eth_10g_xlconstant_0_0.xml             |    274 +
 .../sim/pl_eth_10g_xlconstant_0_0.cpp         |     73 +
 .../sim/pl_eth_10g_xlconstant_0_0.h           |     65 +
 .../sim/pl_eth_10g_xlconstant_0_0.v           |     68 +
 .../sim/pl_eth_10g_xlconstant_0_0_stub.sv     |     86 +
 .../sim/xlconstant_v1_1_7.h                   |     69 +
 .../synth/pl_eth_10g_xlconstant_0_0.v         |     69 +
 .../pl_eth_10g_xlconstant_1_0.xml             |    273 +
 .../sim/pl_eth_10g_xlconstant_1_0.cpp         |     73 +
 .../sim/pl_eth_10g_xlconstant_1_0.h           |     65 +
 .../sim/pl_eth_10g_xlconstant_1_0.v           |     68 +
 .../sim/pl_eth_10g_xlconstant_1_0_stub.sv     |     86 +
 .../sim/xlconstant_v1_1_7.h                   |     69 +
 .../synth/pl_eth_10g_xlconstant_1_0.v         |     69 +
 .../pl_eth_10g_xlconstant_2_0.xml             |    274 +
 .../sim/pl_eth_10g_xlconstant_2_0.cpp         |     73 +
 .../sim/pl_eth_10g_xlconstant_2_0.h           |     65 +
 .../sim/pl_eth_10g_xlconstant_2_0.v           |     68 +
 .../sim/pl_eth_10g_xlconstant_2_0_stub.sv     |     86 +
 .../sim/xlconstant_v1_1_7.h                   |     69 +
 .../synth/pl_eth_10g_xlconstant_2_0.v         |     69 +
 .../an_lt_lpm_dfe_gt_drp.txt                  |      1 +
 .../pl_eth_10g_xxv_ethernet_0_0/core_xdc.txt  |      1 +
 ...pl_eth_10g_xxv_ethernet_0_0_axi4lite_reg.h |   3505 +
 .../ip_0/pl_eth_10g_xxv_ethernet_0_0_gt.xci   |   1410 +
 .../ip_0/pl_eth_10g_xxv_ethernet_0_0_gt.xml   |  24001 ++
 .../gtwizard_ultrascale_v1_7_gthe4_channel.v  |   3697 +
 .../ip_0/sim/pl_eth_10g_xxv_ethernet_0_0_gt.v |    811 +
 ...xv_ethernet_0_0_gt_gthe4_channel_wrapper.v |   1735 +
 ...h_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4.v |   3846 +
 ...eth_10g_xxv_ethernet_0_0_gt_gtwizard_top.v |   3401 +
 .../gtwizard_ultrascale_v1_7_gthe4_channel.v  |   3697 +
 .../synth/pl_eth_10g_xxv_ethernet_0_0_gt.v    |    817 +
 .../synth/pl_eth_10g_xxv_ethernet_0_0_gt.xdc  |     86 +
 ...xv_ethernet_0_0_gt_gthe4_channel_wrapper.v |   1735 +
 ...h_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4.v |   3846 +
 ...eth_10g_xxv_ethernet_0_0_gt_gtwizard_top.v |   3401 +
 .../pl_eth_10g_xxv_ethernet_0_0_gt_ooc.xdc    |     96 +
 .../pl_eth_10g_xxv_ethernet_0_0.v             |    587 +
 .../pl_eth_10g_xxv_ethernet_0_0.xml           | 129606 +++++++++
 .../gtwizard_ultrascale_v1_7_gthe4_common.v   |    928 +
 ...xxv_ethernet_0_0_gt_gthe4_common_wrapper.v |    397 +
 .../synth/pl_eth_10g_xxv_ethernet_0_0.xdc     |    165 +
 .../pl_eth_10g_xxv_ethernet_0_0_board.xdc     |      2 +
 .../synth/pl_eth_10g_xxv_ethernet_0_0_ooc.xdc |     91 +
 ...0g_xxv_ethernet_0_0_axi4_lite_if_wrapper.v |   6360 +
 ..._eth_10g_xxv_ethernet_0_0_common_wrapper.v |    195 +
 .../pl_eth_10g_xxv_ethernet_0_0_top.v         |    848 +
 ...g_xxv_ethernet_0_0_ultrascale_rx_userclk.v |    153 +
 ...g_xxv_ethernet_0_0_ultrascale_tx_userclk.v |    151 +
 .../pl_eth_10g_xxv_ethernet_0_0_wrapper.v     |   1098 +
 .../hdl/pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef  |    Bin 0 -> 863896 bytes
 .../hdl/zynq_ultra_ps_e_v3_3_3.v              |   5063 +
 .../pl_eth_10g_zynq_ultra_ps_e_0_0.xdc        |     26 +
 .../pl_eth_10g_zynq_ultra_ps_e_0_0.xml        |  82951 ++++++
 .../pl_eth_10g_zynq_ultra_ps_e_0_0_ooc.xdc    |      3 +
 .../pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.c |  23824 ++
 .../pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.h |  38619 +++
 .../psu_init.html                             |   3087 +
 .../psu_init.tcl                              |  18127 ++
 .../psu_init_gpl.c                            |  23833 ++
 .../psu_init_gpl.h                            |  38633 +++
 .../sim/pl_eth_10g_zynq_ultra_ps_e_0_0.cpp    |   1240 +
 .../sim/pl_eth_10g_zynq_ultra_ps_e_0_0.h      |    688 +
 .../sim/pl_eth_10g_zynq_ultra_ps_e_0_0_sc.cpp |    117 +
 .../sim/pl_eth_10g_zynq_ultra_ps_e_0_0_sc.h   |     98 +
 .../pl_eth_10g_zynq_ultra_ps_e_0_0_stub.sv    |    338 +
 ..._eth_10g_zynq_ultra_ps_e_0_0_vip_wrapper.v |    845 +
 .../sim_tlm/b_transport_converter.h           |    170 +
 .../sim_tlm/xilinx_zynqmp.cpp                 |    343 +
 .../sim_tlm/xilinx_zynqmp.h                   |    172 +
 .../sim_tlm/zynq_ultra_ps_e_tlm.cpp           |    254 +
 .../sim_tlm/zynq_ultra_ps_e_tlm.h             |    210 +
 .../synth/pl_eth_10g_zynq_ultra_ps_e_0_0.v    |   1852 +
 .../ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd    |    413 +
 .../05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv      | 209447 +++++++++++++++
 .../hdl/axi_clock_converter_v2_1_vl_rfs.v     |   2177 +
 .../hdl/axi_dwidth_converter_v2_1_vl_rfs.v    |  15354 ++
 .../hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v |  15354 ++
 .../276e/hdl/fifo_generator_v13_2_rfs.v       |   7777 +
 .../276e/hdl/fifo_generator_v13_2_rfs.vhd     |  18837 ++
 .../hdl/fifo_generator_v13_2_vhsyn_rfs.vhd    |  31975 +++
 .../276e/simulation/fifo_generator_vlog_beh.v |  10519 +
 .../2985/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd   | 193196 +++++++++++++
 .../2985/simulation/blk_mem_gen_v8_4.v        |   4522 +
 .../3f90/hdl/util_vector_logic_v2_0_vl_rfs.v  |     80 +
 .../ipshared/4919/hdl/axi_sg_v4_1_rfs.vhd     |  29829 ++
 .../4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd    |  56544 ++++
 .../ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v  |   1041 +
 .../51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd        |   1032 +
 .../54c0/hdl/axi_data_fifo_v2_1_vl_rfs.v      |   1956 +
 .../hdl/axi_protocol_converter_v2_1_vl_rfs.v  |   5588 +
 .../8713/hdl/axis_infrastructure_v1_1_0.vh    |    337 +
 .../hdl/axis_infrastructure_v1_1_vl_rfs.v     |   1324 +
 .../8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd   |   1646 +
 .../ipshared/88c9/hdl/axi_mmu_v2_1_vl_rfs.v   |   1271 +
 .../ipshared/89d8/hdl/axi_dma_v7_1_vh_rfs.vhd |  24060 ++
 .../ipshared/94c3/hdl/axi_vip_v1_1_vl_rfs.sv  |    633 +
 .../ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd   |   3342 +
 .../abd4/hdl/axis_data_fifo_v2_0_vl_rfs.v     |    667 +
 .../af2c/hdl/axi_register_slice_v2_1_vl_rfs.v |   4843 +
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_ooc.xdc
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.v
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_stub.sv
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sysc/axi_clock_converter.cpp
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_ooc.xdc
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_stub.sv
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sysc/axi_clock_converter.cpp
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.v
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_stub.sv
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/synth/pl_eth_10g_auto_ds_0.v
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_ooc.xdc
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.v
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_sc.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_stub.sv
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.h
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.h
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.v
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_sc.h
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_stub.sv
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/src/axi_dwidth_converter.cpp
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_ooc.xdc
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.cpp
 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.h
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_sc.h
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 create mode 100644 src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/src/axi_dwidth_converter.cpp
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+  /ColorSpace /DeviceRGB
+  /BitsPerComponent 8
+  /Width 269
+  /Height 114
+  /SMask 102 0 R
+  /Length 91998
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+trailer
+<<
+  /Size 103
+  /Info 1 0 R
+  /Root 2 0 R
+>>
+startxref
+239435
+%%EOF
diff --git a/src/constraints/constraints.xdc b/src/constraints/constraints.xdc
new file mode 100644
index 0000000..b79ef84
--- /dev/null
+++ b/src/constraints/constraints.xdc
@@ -0,0 +1,45 @@
+# Copyright 2020 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+## enable tx by forcing 0 from design. sfp0,1,2,3 => a12, a13, b13, c13
+set_property PACKAGE_PIN AE22 [get_ports {sfp_tx_dis[0]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {sfp_tx_dis[0]}]
+
+#sfp2
+set_property PACKAGE_PIN AA2 [get_ports gt_rx_gt_port_0_p]
+set_property PACKAGE_PIN AA1 [get_ports gt_rx_gt_port_0_n]
+set_property PACKAGE_PIN Y4 [get_ports gt_tx_gt_port_0_p]
+set_property PACKAGE_PIN Y3 [get_ports gt_tx_gt_port_0_n]
+
+#USER_MGT_SI570_CLOCK2_C_P
+set_property PACKAGE_PIN U10 [get_ports gt_ref_clk_clk_p]
+create_clock -period 6.400 -name gt_ref_clk [get_ports gt_ref_clk_clk_p]
+
+#LED 2 and 3
+# led 0 .. 7 => ag14, af13, ae13, aj14, aj15, ah13, ah14, al12
+#set_property IOSTANDARD LVCMOS25 [get_ports *led]
+#set_property PACKAGE_PIN AF13 [get_ports axil_reset_led]
+#set_property PACKAGE_PIN AJ14 [get_ports {axi_lite_clk_led[0]}]
+#set_property PACKAGE_PIN AH13 [get_ports {mgt_clk_led[0]}]
+#set_property PACKAGE_PIN AH14 [get_ports {rx_clk_led[0]}]
+#set_property PACKAGE_PIN AG14 [get_ports {sys_reset_led}]
+#set_property PACKAGE_PIN AL12 [get_ports {gtwiz_rst_led}]
+
+#CR 965826
+#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 6.40
+#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 6.40
+#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_0] -datapath_only 6.40
+#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0] -datapath_only 6.40
+#set_max_delay -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 10.000
+#set_max_delay -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 10.000
\ No newline at end of file
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf
new file mode 100644
index 0000000..a1647b9
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf
@@ -0,0 +1,46 @@
+version:1
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diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/java_command_handlers.wdf b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..4178f4e
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/java_command_handlers.wdf
@@ -0,0 +1,22 @@
+version:1
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diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/project.wpc b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/project.wpc
new file mode 100644
index 0000000..30d3330
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
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diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis.wdf b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..2c80ca9
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+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis.wdf
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diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis_details.wdf b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000..78f8d66
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000..5a72f6c
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml
@@ -0,0 +1,94 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri Oct 20 16:41:35 2023">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="e44f545a56b248f4976b49478b84eb20" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AutoConnectTarget" value="7" type="JavaHandler"/>
+<property name="CustomizeRSBBlock" value="6" type="JavaHandler"/>
+<property name="ExitApp" value="4" type="JavaHandler"/>
+<property name="LaunchOpenTarget" value="2" type="JavaHandler"/>
+<property name="LaunchProgramFpga" value="7" type="JavaHandler"/>
+<property name="NewExportHardware" value="2" type="JavaHandler"/>
+<property name="OpenHardwareManager" value="19" type="JavaHandler"/>
+<property name="OpenProject" value="1" type="JavaHandler"/>
+<property name="OpenRecentTarget" value="14" type="JavaHandler"/>
+<property name="ProgramDevice" value="9" type="JavaHandler"/>
+<property name="RefreshServer" value="2" type="JavaHandler"/>
+<property name="RefreshTarget" value="1" type="JavaHandler"/>
+<property name="RunBitgen" value="2" type="JavaHandler"/>
+<property name="RunImplementation" value="2" type="JavaHandler"/>
+<property name="RunSynthesis" value="3" type="JavaHandler"/>
+<property name="SaveRSBDesign" value="1" type="JavaHandler"/>
+<property name="ShowView" value="1" type="JavaHandler"/>
+<property name="ToolsSettings" value="1" type="JavaHandler"/>
+<property name="ViewTaskImplementation" value="2" type="JavaHandler"/>
+<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_OK" value="10" type="GuiHandlerData"/>
+<property name="CmdMsgDialog_OK" value="15" type="GuiHandlerData"/>
+<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiHandlerData"/>
+<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="3" type="GuiHandlerData"/>
+<property name="ExportPlatformWizard_FIXED_POST_IMPL" value="2" type="GuiHandlerData"/>
+<property name="ExportPlatformWizard_OUTPUT_XSA_NAME" value="1" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="22" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="40" type="GuiHandlerData"/>
+<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="8" type="GuiHandlerData"/>
+<property name="MainMenuMgr_CHECKPOINT" value="3" type="GuiHandlerData"/>
+<property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_EXPORT" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="8" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IMPORT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TEXT_EDITOR" value="5" type="GuiHandlerData"/>
+<property name="MainToolbarMgr_RUN" value="3" type="GuiHandlerData"/>
+<property name="PACommandNames_AUTO_CONNECT_TARGET" value="7" type="GuiHandlerData"/>
+<property name="PACommandNames_EXPORT_HARDWARE" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_OPEN_TARGET_WIZARD" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_REFRESH_SERVER" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_REFRESH_TARGET" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_RUN_BITGEN" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
+<property name="PAViews_DASHBOARD" value="1" type="GuiHandlerData"/>
+<property name="PAViews_MIG" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="4" type="GuiHandlerData"/>
+<property name="PSSPanelClockingPage_PLL_OPTIONS" value="1" type="GuiHandlerData"/>
+<property name="PSSPanelClockingPage_TABBED_PANE" value="6" type="GuiHandlerData"/>
+<property name="PSSPanelDDRPage_OTHER_OPTIONS" value="2" type="GuiHandlerData"/>
+<property name="PSSPanelMainPage_SWITCH_TO_ADVANCED_MODE" value="1" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_ADV_CLK_TREE" value="47" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_CLK_TREE" value="7" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_GENERAL_TREE" value="12" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_MIO_TREE" value="8" type="GuiHandlerData"/>
+<property name="ProgramFpgaDialog_PROGRAM" value="7" type="GuiHandlerData"/>
+<property name="RunGadget_SHOW_ERROR_AND_CRITICAL_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
+<property name="SettingsDialog_PROJECT_TREE" value="6" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
+<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
+<property name="TclConsoleView_COPY" value="1" type="GuiHandlerData"/>
+<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="5" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="50" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="32" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v
new file mode 100644
index 0000000..2cc84ab
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v
@@ -0,0 +1,44 @@
+//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+//Date        : Fri Oct 20 12:44:41 2023
+//Host        : DESKTOP-5FH9OH3 running 64-bit major release  (build 9200)
+//Command     : generate_target pl_eth_10g_wrapper.bd
+//Design      : pl_eth_10g_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module pl_eth_10g_wrapper
+   (gt_ref_clk_clk_n,
+    gt_ref_clk_clk_p,
+    gt_rx_gt_port_0_n,
+    gt_rx_gt_port_0_p,
+    gt_tx_gt_port_0_n,
+    gt_tx_gt_port_0_p,
+    sfp_tx_dis);
+  input gt_ref_clk_clk_n;
+  input gt_ref_clk_clk_p;
+  input gt_rx_gt_port_0_n;
+  input gt_rx_gt_port_0_p;
+  output gt_tx_gt_port_0_n;
+  output gt_tx_gt_port_0_p;
+  output [0:0]sfp_tx_dis;
+
+  wire gt_ref_clk_clk_n;
+  wire gt_ref_clk_clk_p;
+  wire gt_rx_gt_port_0_n;
+  wire gt_rx_gt_port_0_p;
+  wire gt_tx_gt_port_0_n;
+  wire gt_tx_gt_port_0_p;
+  wire [0:0]sfp_tx_dis;
+
+  pl_eth_10g pl_eth_10g_i
+       (.gt_ref_clk_clk_n(gt_ref_clk_clk_n),
+        .gt_ref_clk_clk_p(gt_ref_clk_clk_p),
+        .gt_rx_gt_port_0_n(gt_rx_gt_port_0_n),
+        .gt_rx_gt_port_0_p(gt_rx_gt_port_0_p),
+        .gt_tx_gt_port_0_n(gt_tx_gt_port_0_n),
+        .gt_tx_gt_port_0_p(gt_tx_gt_port_0_p),
+        .sfp_tx_dis(sfp_tx_dis));
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh
new file mode 100644
index 0000000..1304fff
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh
@@ -0,0 +1,14004 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Oct 20 12:45:21 2023" VIVADOVERSION="2020.2">
+
+  <SYSTEMINFO ARCH="zynquplus" DEVICE="xczu7ev" NAME="pl_eth_10g" PACKAGE="ffvc1156" SPEEDGRADE="-2"/>
+
+  <EXTERNALPORTS>
+    <PORT DIR="O" LEFT="0" NAME="sfp_tx_dis" RIGHT="0" SIGIS="undef" SIGNAME="sfp_tx_dis_dout">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="sfp_tx_dis" PORT="dout"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" NAME="gt_rx_gt_port_0_n" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxn_in_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_rxn_in_0"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" NAME="gt_rx_gt_port_0_p" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxp_in_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_rxp_in_0"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" NAME="gt_tx_gt_port_0_n" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_txn_out_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_txn_out_0"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" NAME="gt_tx_gt_port_0_p" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_txp_out_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_txp_out_0"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="gt_ref_clk_clk_n" SIGIS="clk" SIGNAME="xxv_ethernet_0_gt_refclk_n">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_refclk_n"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="gt_ref_clk_clk_p" SIGIS="clk" SIGNAME="xxv_ethernet_0_gt_refclk_p">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_refclk_p"/>
+      </CONNECTIONS>
+    </PORT>
+  </EXTERNALPORTS>
+
+  <EXTERNALINTERFACES>
+    <BUSINTERFACE BUSNAME="External_Interface_gt_ref_clk" NAME="gt_ref_clk" TYPE="TARGET">
+      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+      <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+      <PORTMAPS>
+        <PORTMAP LOGICAL="CLK_N" PHYSICAL="gt_ref_clk_clk_n"/>
+        <PORTMAP LOGICAL="CLK_P" PHYSICAL="gt_ref_clk_clk_p"/>
+      </PORTMAPS>
+    </BUSINTERFACE>
+    <BUSINTERFACE BUSNAME="External_Interface_gt_rx" NAME="gt_rx" TYPE="TARGET">
+      <PORTMAPS>
+        <PORTMAP LOGICAL="gt_port_0_n" PHYSICAL="gt_rx_gt_port_0_n"/>
+        <PORTMAP LOGICAL="gt_port_0_p" PHYSICAL="gt_rx_gt_port_0_p"/>
+      </PORTMAPS>
+    </BUSINTERFACE>
+    <BUSINTERFACE BUSNAME="xxv_ethernet_0_gt_tx" NAME="gt_tx" TYPE="INITIATOR">
+      <PORTMAPS>
+        <PORTMAP LOGICAL="gt_port_0_n" PHYSICAL="gt_tx_gt_port_0_n"/>
+        <PORTMAP LOGICAL="gt_port_0_p" PHYSICAL="gt_tx_gt_port_0_p"/>
+      </PORTMAPS>
+    </BUSINTERFACE>
+  </EXTERNALINTERFACES>
+
+  <MODULES>
+    <MODULE COREREVISION="23" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
+          <REGISTERS>
+            <REGISTER NAME="MM2S_DMACR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
+              <FIELDS>
+                <FIELD NAME="RS">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Keyhole">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when the multichannel feature is enabled or in Direct Register mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Cyclic_BD_Enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.&#xA;This bit is non functional when DMA operates in multichannel mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IOC_IrqEn">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Dly_IrqEn">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Err_IrqEn">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable.&#xA;  0 - Error Interrupt disabled&#xA;  1 - Error Interrupt enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IRQThreshold">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="IRQDelay">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_DMASR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x04"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
+              <FIELDS>
+                <FIELD NAME="Halted">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Idle">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGIncld">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="1 - Scatter Gather Enabled&#xA;0 - Scatter Gather not enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="DMAIntErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="DMASlvErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="DMADecErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGIntErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit� already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGSlvErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGDecErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IOC_Irq">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Dly_Irq">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Err_Irq">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.   &#xA;0 - No error Interrupt.   &#xA;1 - Error interrupt detected.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IRQThresholdSts">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="IRQDelaySts">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_CURDESC">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Current_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_CURDESC_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Current_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_TAILDESC">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Tail_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_TAILDESC_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Tail_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_SA">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Source_Address">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_SA_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Source_Address">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MM2S_LENGTH">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Transfer Length Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Length">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="SG_CTL">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User and Cache Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x03"/>
+              <FIELDS>
+                <FIELD NAME="SG_CACHE">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+                </FIELD>
+                <FIELD NAME="SG_USER">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_DMACR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
+              <FIELDS>
+                <FIELD NAME="RS">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Keyhole">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when DMA is used in multichannel mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Cyclic_BD_Enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IOC_IrqEn">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Dly_IrqEn">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Err_IrqEn">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IRQThreshold">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.&#xA;Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="IRQDelay">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_DMASR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x34"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
+              <FIELDS>
+                <FIELD NAME="Halted">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 &#xA;Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Idle">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGIncld">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="DMAIntErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.&#xA;This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="DMASlvErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="DMADecErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGIntErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit� already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGSlvErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SGDecErr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IOC_Irq">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Dly_Irq">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Err_Irq">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="IRQThresholdSts">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="IRQDelaySts">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_CURDESC">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x38"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Current_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). &#xA;Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_CURDESC_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x3C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Current_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_TAILDESC">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Tail_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. &#xA;Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_TAILDESC_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x44"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Tail_Descriptor_Pointer">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_DA">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Destination Address Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x48"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Destination_Address">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_DA_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM Destination Address Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Destination_Address">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="S2MM_LENGTH">
+              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Transfer Length Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Length">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.&#xA;At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.&#xA;Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+          </REGISTERS>
+        </ADDRESSBLOCK>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_S_AXI_LITE_ADDR_WIDTH" VALUE="10"/>
+        <PARAMETER NAME="C_S_AXI_LITE_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_DLYTMR_RESOLUTION" VALUE="125"/>
+        <PARAMETER NAME="C_PRMRY_IS_ACLK_ASYNC" VALUE="1"/>
+        <PARAMETER NAME="C_ENABLE_MULTI_CHANNEL" VALUE="0"/>
+        <PARAMETER NAME="C_NUM_MM2S_CHANNELS" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_S2MM_CHANNELS" VALUE="1"/>
+        <PARAMETER NAME="C_INCLUDE_SG" VALUE="1"/>
+        <PARAMETER NAME="C_SG_INCLUDE_STSCNTRL_STRM" VALUE="0"/>
+        <PARAMETER NAME="C_SG_USE_STSAPP_LENGTH" VALUE="0"/>
+        <PARAMETER NAME="C_SG_LENGTH_WIDTH" VALUE="16"/>
+        <PARAMETER NAME="C_M_AXI_SG_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_SG_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_MICRO_DMA" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_MM2S" VALUE="1"/>
+        <PARAMETER NAME="C_INCLUDE_MM2S_SF" VALUE="1"/>
+        <PARAMETER NAME="C_MM2S_BURST_SIZE" VALUE="64"/>
+        <PARAMETER NAME="C_M_AXI_MM2S_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_MM2S_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_M_AXIS_MM2S_TDATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="1"/>
+        <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="1"/>
+        <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
+        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="8"/>
+        <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="1"/>
+        <PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_axi_dma_0_0"/>
+        <PARAMETER NAME="c_include_sg" VALUE="1"/>
+        <PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
+        <PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
+        <PARAMETER NAME="c_num_s2mm_channels" VALUE="1"/>
+        <PARAMETER NAME="c_sg_length_width" VALUE="16"/>
+        <PARAMETER NAME="c_dlytmr_resolution" VALUE="125"/>
+        <PARAMETER NAME="c_prmry_is_aclk_async" VALUE="1"/>
+        <PARAMETER NAME="c_sg_include_stscntrl_strm" VALUE="0"/>
+        <PARAMETER NAME="c_micro_dma" VALUE="0"/>
+        <PARAMETER NAME="c_include_mm2s" VALUE="1"/>
+        <PARAMETER NAME="c_m_axi_mm2s_data_width" VALUE="64"/>
+        <PARAMETER NAME="c_m_axis_mm2s_tdata_width" VALUE="64"/>
+        <PARAMETER NAME="c_include_mm2s_dre" VALUE="1"/>
+        <PARAMETER NAME="c_include_mm2s_sf" VALUE="1"/>
+        <PARAMETER NAME="c_mm2s_burst_size" VALUE="64"/>
+        <PARAMETER NAME="c_include_s2mm" VALUE="1"/>
+        <PARAMETER NAME="c_sg_use_stsapp_length" VALUE="0"/>
+        <PARAMETER NAME="c_m_axi_s2mm_data_width" VALUE="64"/>
+        <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="64"/>
+        <PARAMETER NAME="c_include_s2mm_dre" VALUE="1"/>
+        <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
+        <PARAMETER NAME="c_s2mm_burst_size" VALUE="8"/>
+        <PARAMETER NAME="c_addr_width" VALUE="32"/>
+        <PARAMETER NAME="c_single_interface" VALUE="0"/>
+        <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x80000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x8000FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="124998749" DIR="I" NAME="s_axi_lite_aclk" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="124998749" DIR="I" NAME="m_axi_sg_aclk" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="I" NAME="m_axi_mm2s_aclk" SIGIS="clk" SIGNAME="xxv_ethernet_0_tx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_clk_out_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="I" NAME="m_axi_s2mm_aclk" SIGIS="clk" SIGNAME="xxv_ethernet_0_rx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_clk_out_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="axi_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_sg_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axi_sg_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_sg_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_sg_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_sg_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_sg_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_sg_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_sg_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_sg_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_sg_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_sg_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_sg_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_sg_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="m_axi_sg_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_sg_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_sg_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_sg_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axi_sg_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_sg_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_sg_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_sg_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_sg_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_sg_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_sg_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="m_axi_sg_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="m_axi_sg_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_sg_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_sg_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_sg_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_mm2s_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_mm2s_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="63" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_mm2s_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_mm2s_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_mm2s_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="mm2s_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="axi_dma_0_mm2s_prmry_reset_out_n">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dma_tx_rst" PORT="Op1"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="63" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="s_axis_tdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="s_axis_tkeep"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axis_mm2s_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="s_axis_tvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axis_mm2s_tready" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="s_axis_tready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axis_mm2s_tlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="s_axis_tlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="63" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s2mm_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="axi_dma_0_s2mm_prmry_reset_out_n">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dma_rx_rst" PORT="Op1"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="63" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="m_axis_tdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="m_axis_tkeep"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="m_axis_tvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="m_axis_tready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="m_axis_tlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_0_mm2s_introut">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_xlconcat_0" PORT="In0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_0_s2mm_introut">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_xlconcat_0" PORT="In1"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="zups_ps_axi_periph_M00_AXI" DATAWIDTH="32" NAME="S_AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="124998749"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_lite_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_lite_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_lite_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_lite_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_lite_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_lite_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_lite_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_lite_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_lite_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_lite_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_lite_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_lite_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_lite_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_lite_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_lite_wready"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_SG" DATAWIDTH="32" NAME="M_AXI_SG" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="124998749"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="m_axi_sg_araddr"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="m_axi_sg_arburst"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="m_axi_sg_arcache"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="m_axi_sg_arlen"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="m_axi_sg_arprot"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="m_axi_sg_arready"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="m_axi_sg_arsize"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="m_axi_sg_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_sg_awaddr"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_sg_awburst"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_sg_awcache"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_sg_awlen"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_sg_awprot"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_sg_awready"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_sg_awsize"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_sg_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_sg_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_sg_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_sg_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="m_axi_sg_rdata"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="m_axi_sg_rlast"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="m_axi_sg_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="m_axi_sg_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_sg_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_sg_wdata"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_sg_wlast"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_sg_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_sg_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_sg_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_MM2S" DATAWIDTH="64" NAME="M_AXI_MM2S" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="64"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="m_axi_mm2s_araddr"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="m_axi_mm2s_arburst"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="m_axi_mm2s_arcache"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="m_axi_mm2s_arlen"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="m_axi_mm2s_arprot"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="m_axi_mm2s_arready"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="m_axi_mm2s_arsize"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="m_axi_mm2s_arvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="m_axi_mm2s_rdata"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="m_axi_mm2s_rlast"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="m_axi_mm2s_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="m_axi_mm2s_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_mm2s_rvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_S2MM" DATAWIDTH="64" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="8"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_s2mm_awaddr"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_s2mm_awburst"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_s2mm_awcache"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_s2mm_awlen"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_s2mm_awprot"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_s2mm_awready"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_s2mm_awsize"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_s2mm_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_s2mm_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_s2mm_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_s2mm_bvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_s2mm_wdata"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_s2mm_wlast"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_s2mm_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_s2mm_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_s2mm_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXIS_MM2S" NAME="M_AXIS_MM2S" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_mm2s_tdata"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_mm2s_tkeep"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_mm2s_tlast"/>
+            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_mm2s_tready"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_mm2s_tvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="rx_data_fifo_M_AXIS" NAME="S_AXIS_S2MM" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_s2mm_tdata"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_s2mm_tkeep"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_s2mm_tlast"/>
+            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_s2mm_tready"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_s2mm_tvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE ADDRESSBLOCK="HP0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_SG" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_SG" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_PCIE_LOW" BASENAME="C_BASEADDR" BASEVALUE="0xE0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xEFFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_SG" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_PCIE_LOW" BASENAME="C_BASEADDR" BASEVALUE="0xE0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xEFFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_PCIE_LOW" BASENAME="C_BASEADDR" BASEVALUE="0xE0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xEFFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+        <MEMRANGE ADDRESSBLOCK="HP0_LPS_OCM" BASENAME="C_BASEADDR" BASEVALUE="0xFF000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="zups_zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="zups_zynq_ultra_ps_e_0"/>
+      </PERIPHERALS>
+    </MODULE>
+    <MODULE COREREVISION="1" FULLNAME="/dma_rx_rst" HWVERSION="2.0" INSTANCE="dma_rx_rst" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="util_vector_logic" VLNV="xilinx.com:ip:util_vector_logic:2.0">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="C_OPERATION" VALUE="not"/>
+        <PARAMETER NAME="C_SIZE" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_dma_rx_rst_0"/>
+        <PARAMETER NAME="LOGO_FILE" VALUE="data/sym_notgate.png"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="Op1" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s2mm_prmry_reset_out_n">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s2mm_prmry_reset_out_n"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Res" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="undef" SIGNAME="dma_rx_rst_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_reset_0"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="1" FULLNAME="/dma_tx_rst" HWVERSION="2.0" INSTANCE="dma_tx_rst" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="util_vector_logic" VLNV="xilinx.com:ip:util_vector_logic:2.0">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="C_OPERATION" VALUE="not"/>
+        <PARAMETER NAME="C_SIZE" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_dma_tx_rst_0"/>
+        <PARAMETER NAME="LOGO_FILE" VALUE="data/sym_notgate.png"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="Op1" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_mm2s_prmry_reset_out_n">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="mm2s_prmry_reset_out_n"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Res" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="undef" SIGNAME="dma_tx_rst_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_reset_0"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="4" FULLNAME="/rx_data_fifo" HWVERSION="2.0" INSTANCE="rx_data_fifo" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_data_fifo" VLNV="xilinx.com:ip:axis_data_fifo:2.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_data_fifo;v=v2_0;d=pg085-axi4stream-infrastructure.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
+        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000010011011"/>
+        <PARAMETER NAME="C_FIFO_DEPTH" VALUE="32768"/>
+        <PARAMETER NAME="C_FIFO_MODE" VALUE="2"/>
+        <PARAMETER NAME="C_IS_ACLK_ASYNC" VALUE="0"/>
+        <PARAMETER NAME="C_SYNCHRONIZER_STAGE" VALUE="3"/>
+        <PARAMETER NAME="C_ACLKEN_CONV_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_FIFO_MEMORY_TYPE" VALUE="auto"/>
+        <PARAMETER NAME="C_USE_ADV_FEATURES" VALUE="826486851"/>
+        <PARAMETER NAME="C_PROG_EMPTY_THRESH" VALUE="5"/>
+        <PARAMETER NAME="C_PROG_FULL_THRESH" VALUE="11"/>
+        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="TUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="FIFO_DEPTH" VALUE="32768"/>
+        <PARAMETER NAME="FIFO_MODE" VALUE="2"/>
+        <PARAMETER NAME="IS_ACLK_ASYNC" VALUE="0"/>
+        <PARAMETER NAME="ACLKEN_CONV_MODE" VALUE="0"/>
+        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+        <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+        <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
+        <PARAMETER NAME="HAS_WR_DATA_COUNT" VALUE="1"/>
+        <PARAMETER NAME="HAS_RD_DATA_COUNT" VALUE="1"/>
+        <PARAMETER NAME="HAS_AEMPTY" VALUE="0"/>
+        <PARAMETER NAME="HAS_PROG_EMPTY" VALUE="0"/>
+        <PARAMETER NAME="PROG_EMPTY_THRESH" VALUE="5"/>
+        <PARAMETER NAME="HAS_AFULL" VALUE="0"/>
+        <PARAMETER NAME="HAS_PROG_FULL" VALUE="0"/>
+        <PARAMETER NAME="PROG_FULL_THRESH" VALUE="11"/>
+        <PARAMETER NAME="ENABLE_ECC" VALUE="0"/>
+        <PARAMETER NAME="HAS_ECC_ERR_INJECT" VALUE="0"/>
+        <PARAMETER NAME="FIFO_MEMORY_TYPE" VALUE="auto"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_rx_data_fifo_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rx_rst_n_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_rst_n" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="xxv_ethernet_0_rx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_clk_out_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_axis_tvalid_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="63" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_axis_tdata_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="s_axis_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_axis_tkeep_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axis_tlast" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_axis_tlast_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="s_axis_tuser" RIGHT="0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tuser">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_axis_tuser_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axis_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tkeep"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axis_tlast" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="m_axis_tuser" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="31" NAME="axis_wr_data_count" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="31" NAME="axis_rd_data_count" RIGHT="0" SIGIS="undef"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="xxv_ethernet_0_axis_rx_0" NAME="S_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="1"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_tkeep"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
+            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
+            <PORTMAP LOGICAL="TUSER" PHYSICAL="s_axis_tuser"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="rx_data_fifo_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="1"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
+            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
+            <PORTMAP LOGICAL="TUSER" PHYSICAL="m_axis_tuser"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="1" FULLNAME="/rx_rst_n" HWVERSION="2.0" INSTANCE="rx_rst_n" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="util_vector_logic" VLNV="xilinx.com:ip:util_vector_logic:2.0">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="C_OPERATION" VALUE="not"/>
+        <PARAMETER NAME="C_SIZE" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_rx_rst_n_0"/>
+        <PARAMETER NAME="LOGO_FILE" VALUE="data/sym_notgate.png"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="Op1" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_user_rx_reset_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="user_rx_reset_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Res" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="undef" SIGNAME="rx_rst_n_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="s_axis_aresetn"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="7" FULLNAME="/sfp_tx_dis" HWVERSION="1.1" INSTANCE="sfp_tx_dis" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="CONST_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="CONST_VAL" VALUE="0x1"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_sfp_tx_dis_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="sfp_tx_dis_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="sfp_tx_dis"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="4" FULLNAME="/tx_data_fifo" HWVERSION="2.0" INSTANCE="tx_data_fifo" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_data_fifo" VLNV="xilinx.com:ip:axis_data_fifo:2.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_data_fifo;v=v2_0;d=pg085-axi4stream-infrastructure.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
+        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000011011"/>
+        <PARAMETER NAME="C_FIFO_DEPTH" VALUE="32768"/>
+        <PARAMETER NAME="C_FIFO_MODE" VALUE="2"/>
+        <PARAMETER NAME="C_IS_ACLK_ASYNC" VALUE="0"/>
+        <PARAMETER NAME="C_SYNCHRONIZER_STAGE" VALUE="3"/>
+        <PARAMETER NAME="C_ACLKEN_CONV_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_FIFO_MEMORY_TYPE" VALUE="auto"/>
+        <PARAMETER NAME="C_USE_ADV_FEATURES" VALUE="826486851"/>
+        <PARAMETER NAME="C_PROG_EMPTY_THRESH" VALUE="5"/>
+        <PARAMETER NAME="C_PROG_FULL_THRESH" VALUE="11"/>
+        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="FIFO_DEPTH" VALUE="32768"/>
+        <PARAMETER NAME="FIFO_MODE" VALUE="2"/>
+        <PARAMETER NAME="IS_ACLK_ASYNC" VALUE="0"/>
+        <PARAMETER NAME="ACLKEN_CONV_MODE" VALUE="0"/>
+        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+        <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+        <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
+        <PARAMETER NAME="HAS_WR_DATA_COUNT" VALUE="1"/>
+        <PARAMETER NAME="HAS_RD_DATA_COUNT" VALUE="1"/>
+        <PARAMETER NAME="HAS_AEMPTY" VALUE="0"/>
+        <PARAMETER NAME="HAS_PROG_EMPTY" VALUE="0"/>
+        <PARAMETER NAME="PROG_EMPTY_THRESH" VALUE="5"/>
+        <PARAMETER NAME="HAS_AFULL" VALUE="0"/>
+        <PARAMETER NAME="HAS_PROG_FULL" VALUE="0"/>
+        <PARAMETER NAME="PROG_FULL_THRESH" VALUE="11"/>
+        <PARAMETER NAME="ENABLE_ECC" VALUE="0"/>
+        <PARAMETER NAME="HAS_ECC_ERR_INJECT" VALUE="0"/>
+        <PARAMETER NAME="FIFO_MEMORY_TYPE" VALUE="auto"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_tx_data_fifo_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="tx_rst_n_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_rst_n" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="xxv_ethernet_0_tx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_clk_out_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="63" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="s_axis_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tkeep"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axis_tlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_axis_tvalid_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_axis_tready_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_axis_tdata_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axis_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_axis_tkeep_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axis_tlast" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_axis_tlast_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="axis_wr_data_count" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="31" NAME="axis_rd_data_count" RIGHT="0" SIGIS="undef"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXIS_MM2S" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_tkeep"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
+            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="tx_data_fifo_M_AXIS" NAME="M_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
+            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="1" FULLNAME="/tx_rst_n" HWVERSION="2.0" INSTANCE="tx_rst_n" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="util_vector_logic" VLNV="xilinx.com:ip:util_vector_logic:2.0">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="C_OPERATION" VALUE="not"/>
+        <PARAMETER NAME="C_SIZE" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_tx_rst_n_0"/>
+        <PARAMETER NAME="LOGO_FILE" VALUE="data/sym_notgate.png"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="Op1" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_user_tx_reset_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="user_tx_reset_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Res" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="undef" SIGNAME="tx_rst_n_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="s_axis_aresetn"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="7" FULLNAME="/xlconstant_0" HWVERSION="1.1" INSTANCE="xlconstant_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="CONST_WIDTH" VALUE="56"/>
+        <PARAMETER NAME="CONST_VAL" VALUE="0x00000000000000"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_xlconstant_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="55" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_0_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_preamblein_0"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="7" FULLNAME="/xlconstant_1" HWVERSION="1.1" INSTANCE="xlconstant_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="CONST_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="CONST_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_xlconstant_1_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_1_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="ctl_tx_send_idle_0"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="ctl_tx_send_lfi_0"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="ctl_tx_send_rfi_0"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="7" FULLNAME="/xlconstant_2" HWVERSION="1.1" INSTANCE="xlconstant_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="CONST_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="CONST_VAL" VALUE="0x5"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_xlconstant_2_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="2" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_2_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rxoutclksel_in_0"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="txoutclksel_in_0"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="0" FULLNAME="/xxv_ethernet_0" HWVERSION="3.3" INSTANCE="xxv_ethernet_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xxv_ethernet" VLNV="xilinx.com:ip:xxv_ethernet:3.3">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=xxv_ethernet;v=v3_3;d=pg210-25g-ethernet.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_0" NAME="Reg" RANGE="65536" USAGE="register">
+          <REGISTERS>
+            <REGISTER NAME="GT_RESET_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="GT_RESET_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_gt_reset_all">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl gt reset all.&#xA;  0 - Normal operation&#xA;  1 - Reset the GT&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_gt_rx_reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl gt rx reset.&#xA;  0 - Normal operation&#xA;  1 - Reset the GT receiver&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_gt_tx_reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl gt tx reset.&#xA;  0 - Normal operation&#xA;  1 - Reset the GT transmitter&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="RESET_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="RESET_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0004"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="rx_serdes_reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="rx serdes reset.&#xA;  0 - Normal operation&#xA;  1 - Reset the Receiver serdes&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="tx_serdes_reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="tx serdes reset.&#xA;  0 - Normal operation&#xA;  1 - Reset the transmitter serdes&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="29"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="29"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="rx_reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="rx reset.&#xA;  0 - Normal operation&#xA;  1 - Reset the receiver &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="30"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="30"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="tx_reset">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="tx_reset.&#xA;  0 - Normal operation&#xA;  1 - Reset the transmitter&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MODE_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="MODE_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0008"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x40000000"/>
+              <FIELDS>
+                <FIELD NAME="tick_reg_mode_sel">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="tick reg mode sel.&#xA;  1 - tick_reg is used to read the statistics counters.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="30"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="30"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_local_loopback">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl local loopback.&#xA;  0 - Normal operation&#xA;  1 - places the transceiver into the PMA loopback state. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x000C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00003003"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx enable.&#xA;  0 - only IDLEs are transmitted by the core.&#xA;  1 - Enables the transmission of data. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_fcs_ins_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx fcs ins enable.&#xA;  0 - the core does not add FCS to packet.&#xA;  1 - the core calculates and adds the FCS to the packet. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_ignore_fcs">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx ignore fcs.&#xA;  0 - A packet with bad FCS is being transmitted, it is not binned as good.&#xA;  1 - A packet with bad FCS is binned as good.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_send_lfi">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx send lfi.&#xA;  0 - Normal operation&#xA;  1 - Transmit Local Fault Indication (LFI) code word. Takes precedence over Remote Fault Indication (RFI).&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_send_rfi">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx send rfi.&#xA;  0 - Normal operation&#xA;  1 - the TX path transmits only RFI code words.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_send_idle">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx send idle.&#xA;  0 - Normal operation&#xA;  1 - The TX path only transmits Idle code words.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_ipg_value">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx ipg value.&#xA;  This signal can be optionally present.&#xA;  The ctl_tx_ipg_value defines the target average minimum Inter Packet Gap (IPG, in bytes) inserted between AXI4-Stream packets.&#xA;  Valid values are 8 to 12.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_test_pattern">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx test pattern.&#xA;  0 - Normal operation&#xA;  1 - Test pattern generation enable for the TX core. A value of 1 enables test mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_test_pattern_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx test pattern enable.&#xA;  0 - Normal operation&#xA;  1 - Test pattern generation enable for the TX core.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="15"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="15"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_test_pattern_select">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx test pattern select.&#xA;  Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_data_pattern_select">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx data pattern select.&#xA;  Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_custom_preamble_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl_tx_custom_preamble_enable.&#xA;  0 - Normal operation&#xA;  1 - When it is set, the use of tx_preamblein as a custom preamble instead of inserting a standard preamble. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_prbs31_test_pattern_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx prbs31 test pattern enable.&#xA;  Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="23"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="23"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0014"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000033"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx enable.&#xA;  0 - The RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data.&#xA;  1 - Normal operation &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_delete_fcs">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx delete fcs.&#xA;  0 - the core does not remove the FCS of the incoming packet.&#xA;  1 - the core deletes the FCS to the received packet. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_ignore_fcs">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx ignore fcs.&#xA;  0 - A packet received with an FCS error is sent with the rx_axis_tuser pin asserted during the last transfer (rx_axis_tlast sampled 1).&#xA;  1 - The core does not flag an FCS error at the AXI4-Stream interface.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_process_lfi">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx process lfi.&#xA;  0 - the RX core ignores LF control codes coming in from the transceiver. &#xA;  1 - the RX core expects and processes LF control codes coming in from the transceiver.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_sfd">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check sfd.&#xA;  0 - Normal operation&#xA;  1 - this input causes the MAC to check the Start of Frame Delimiter of the received frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_preamble">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check preamble.&#xA;  0 - Normal operation&#xA;  1 - this input causes the MAC to check the preamble of the received frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_force_resync">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx force resync.&#xA;  0 - Normal operation&#xA;  1 - forces the reset operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_test_pattern">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Test pattern checking enable for the RX core.&#xA;  0 - Normal operation&#xA;  1 - Enables test mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_test_pattern_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Test pattern enable for the RX core.&#xA;  0 - Normal operation&#xA;  1 - Enables test mode. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_data_pattern_select">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Data pattern select for RX core.&#xA;  Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_custom_preamble_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl_rx_custom_preamble_enable.&#xA;  0 - Normal operation&#xA;  1 - This signal causes the side band of a packet presented on the AXI4-Stream to be the preamble as it appears on the line. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_prbs31_test_pattern_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx prbs31 test pattern enable.&#xA;  Corresponds to MDIO register 3.34 through to 3.37 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_MTU">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_MTU"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0018"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x25800040"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_min_packet_len">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx min packet len.&#xA;  Any packet shorter than this value is considered to be undersized.&#xA;  If a packet has a size less than this value, the rx_axis_tuser signal is asserted during the rx_axis_tlast asserted cycle.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_max_packet_len">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx max packet len.&#xA;  Any packet longer than this value is considered to be oversized.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="15"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_VL_LENGTH_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_VL_LENGTH_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x001C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x4fff4fff"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_vl_length_minus1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx vl length minus1.&#xA;  Normally set to 20479 (decimal). The normal value is equivalent to (16,383 x 5 -4) = 81,916.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_vl_length_minus1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx vl length minus1.&#xA;  Normally set to 20,479 (4FFF hex). The normal value is equivalent to (16,383 x 5 -4) = 81,916.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TSN_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TSN_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x019C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00030101"/>
+              <FIELDS>
+                <FIELD NAME="ctl_en_preempt">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl en preempt.&#xA;  1 - It allows preemption.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_hold_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl hold request.&#xA;  1 - preempt traffic is withheld.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_disable_verify">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl disable verify.&#xA;  1 - It inhibits the verification process.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_restart_verify">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl restart verify.&#xA;  A 0-to-1 transition will trigger Verification if ctl_disable_verify = 1’b0.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_addfrag_size">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl addfrag size.&#xA;  Fragment size remaining to enable pre-emption.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="ctl_verify_time">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl verify time.&#xA;  Verification time-out value in milliseconds.&#xA;  Integer range 1-128.&#xA;  Default is 1 ms.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="ctl_verify_limit">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl verify limit.&#xA;  Number of times core attempts Verification.&#xA;  Integer range 1-15.&#xA;  Default is 3.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TICK_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="TICK_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0020"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="tick_reg">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="tick reg.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_REVISION_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_REVISION_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0024"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000301"/>
+              <FIELDS>
+                <FIELD NAME="major_rev">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="major revision.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="minor_rev">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="minor revision.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="patch_rev">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="patch revision.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_TEST_PAT_SEED_A_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_TEST_PAT_SEED_A_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0028"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_test_pattern_seed_a_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx test pattern seed a.&#xA;  Corresponds to MDIO registers 3.34 through to 3.37 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_TEST_PAT_SEED_A_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_TEST_PAT_SEED_A_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x002C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_test_pattern_seed_a_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx test pattern seed a.&#xA;  Corresponds to MDIO registers 3.34 through to 3.37 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_TEST_PAT_SEED_B_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_TEST_PAT_SEED_B_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0030"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_test_pattern_seed_b_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx test pattern seed b.&#xA;  Corresponds to MDIO registers 3.38 through to 3.41 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_TEST_PAT_SEED_B_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_TEST_PAT_SEED_B_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0034"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_test_pattern_seed_b_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx test pattern seed b.&#xA;  Corresponds to MDIO registers 3.38 through to 3.41 as defined in Clause 45.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_1588_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_1588_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x013C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_ptp_1step_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx ptp 1step enable.&#xA;  1 - this bit enables 1-step operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_ptp_transpclk_mode">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl ptp transpclk mode&#xA;  1 - This input places the timestamping logic into transparent clock mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_ptp_latency_adjust">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx ptp latency adjust.&#xA;  This bus can be used to adjust the 1-step TX timestamp with respect to the 2-step timestamp.&#xA;  The units of bits [10:3] are nanoseconds and bits [2:0] are fractional nanoseconds.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="11"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_lat_adj_enb">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx lat adj enb.&#xA;  1 - The delay computation on the TX path takes into account the value provided by the ctl_tx_latency_0 register.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_lat_adj_enb">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx lat adj enb&#xA;  1 - The delay computation on the RX path takes into account the value provided by the ctl_rx_latency_0 register.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_timstamp_adj_enb">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx timstamp adj enb.&#xA;  1 - The delay computation on the TX path takes into account the value obtained from GT DRP read for latency of the TX gearbox FIFO.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_timstamp_adj_enb">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx timstamp adj enb.&#xA;  1 - The delay computation on the RX path takes into account the value obtained from the GT DRP read for latency of the RX gearbox FIFO.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_core_speed">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl core speed.&#xA;  This signal indicates the speed with which the core is working.&#xA;  0 - 25G&#xA;  1 - 10G&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0040"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="TX pause enable signal.&#xA;  This input is used to enable the processing of the pause quanta for the corresponding priority.&#xA;  This signal gates transmission of pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="9"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0044"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_refresh_timer0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer0.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_refresh_timer1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer1.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0048"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_refresh_timer2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer2.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_refres_timer3">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer3.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x004C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_refresh_timer4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer4.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_refresh_timer5">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer5.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0050"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_refresh_timer6">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer6.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_refresh_timer7">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer7.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0054"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_refresh_timer8">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause refresh timer8.&#xA;  This bus sets the retransmission time of pause packets for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0058"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_quanta0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta0.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_quanta1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta1.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x005C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_quanta2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta2.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_quanta3">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta3.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0060"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_quanta4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta4.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_quanta5">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta5.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0064"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_quanta6">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta6.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_pause_quanta7">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta7.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0068"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_pause_quanta8">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx pause quanta8.&#xA;  These buses indicate the quanta to be transmitted for each of the eight priorities in priority-based pause operation and the global pause operation.&#xA;  The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_PPP_ETYPE_OP_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_PPP_ETYPE_OP_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x006C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x010185EC"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_ethertype_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx ethertype ppp.&#xA;  Ethertype for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_opcode_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx opcode ppp.&#xA;  Opcode for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_GPP_ETYPE_OP_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_GPP_ETYPE_OP_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0070"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000185EC"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_ethertype_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx ethertype gpp.&#xA;  Ethertype for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_tx_opcode_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx opcode gpp.&#xA;  Opcode for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0074"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_da_gpp_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx da gpp.&#xA;  Destination address for transmitting global pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0078"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_da_gpp_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx da gpp.&#xA;  Destination address for transmitting global pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x007C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_sa_gpp_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx sa gpp.&#xA;  Source address for transmitting global pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0080"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_sa_gpp_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx sa gpp.&#xA;  Source address for transmitting global pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0084"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_da_ppp_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx da ppp.&#xA;  Destination address for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0088"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_da_ppp_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx da ppp.&#xA;  Destination address for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x008C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_sa_ppp_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx sa ppp.&#xA;  Source address for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0090"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_sa_ppp_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx sa ppp.&#xA;  Source address for transmitting priority pause packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0094"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_pause_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Rx pause enable.&#xA;  This input is used to enable the processing of the pause quanta for the corresponding priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="9"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_forward_control">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx forward control.&#xA;  0 - causes core to drop control packets.&#xA;  1 - Indicates that the core forwards control packets. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_enable_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx enable gcp.&#xA;  1 - Enables global control packet processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_enable_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx enable pcp.&#xA;  1 - Enables priority control packet processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_enable_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx enable gpp.&#xA;  1 - Enables global pause packet processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_enable_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx enable ppp.&#xA;  1 - Enables priority pause packet processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_ack">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check ack.&#xA;  0 - ctl_rx_pause_ack[8:0] is not used.&#xA;  1 - the core uses the ctl_rx_pause_ack[8:0] bus for pause processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_REG2">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_REG2"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0098"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_check_mcast_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check mcast gcp.&#xA;  0 - Normal operation&#xA;  1 - Enables global control multicast destination address processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_ucast_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check ucast gcp.&#xA;  0 - Normal operation&#xA;  1 - Enables global control unicast destination address processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_sa_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check sa gcp.&#xA;  0 - Normal operation&#xA;  1 - Enables global control source address processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_etype_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check etype gcp.&#xA;  0 - Normal operation&#xA;  1 - Enables global control ethertype processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_opcode_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check opcode gcp.&#xA;  0 - Normal operation&#xA;  1 - Enables global control opcodeprocessing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_mcast_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check mcast pcp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority control multicast destination address processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_ucast_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check ucast pcp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority control unicast destination address processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_sa_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check sa pcp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority control source address processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_etype_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check etype pcp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority control ethertype processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_opcode_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check opcode pcp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority control opcode processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_mcast_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check mcast gpp.&#xA;  0 - Normal operation&#xA;  1 - Enables global pause multicast destination address processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_ucast_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check ucast gpp.&#xA;  0 - Normal operation&#xA;  1 - Enables global pause unicast destination address processing&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_sa_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check sa gpp.&#xA;  0 - Normal operation&#xA;  1 - Enables global pause source address processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_etype_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check etype gpp.&#xA;  0 - Normal operation&#xA;  1 - Enables global pause ethertype processing&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_opcode_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check opcode gpp.&#xA;  0 - Normal operation&#xA;  1 - Enables global pause opcode processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_mcast_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check mcast ppp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority pause multicast destination address processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="15"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="15"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_ucast_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check ucast ppp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority pause unicast destination address processing. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_sa_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check sa ppp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority pause source address processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_etype_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check etype ppp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority pause ethertype processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_check_opcode_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx check opcode ppp.&#xA;  0 - Normal operation&#xA;  1 - Enables priority pause opcode processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="19"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="19"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_PPP_ETYPE_OP_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_PPP_ETYPE_OP_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x009C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x01018808"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_etype_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx etype ppp.&#xA;  Ethertype field for priority pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_opcode_ppp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx opcode ppp.&#xA;  Priority pause opcode value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_GPP_ETYPE_OP_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_GPP_ETYPE_OP_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00A0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00018808"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_etype_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx etype gpp.&#xA;  Ethertype field for global pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_opcode_gpp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx opcode gpp.&#xA;  Global pause opcode value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_GCP_PCP_TYPE_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_GCP_PCP_TYPE_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00A4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x88088808"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_etype_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx etype gcp.&#xA;  Ethertype field for global control processing&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_etype_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx etype pcp.&#xA;  Ethertype field for priority control processing&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_PCP_OP_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_PCP_OP_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00A8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x01010101"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_opcode_min_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx opcode min pcp.&#xA;  Minimum priority control opcode value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_opcode_max_pcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx opcode max pcp.&#xA;  Maximum priority control opcode value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_GCP_OP_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_GCP_OP_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00AC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00060001"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_opcode_min_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx opcode min gcp.&#xA;  Minimum global control opcode value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_opcode_max_gcp">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx opcode max gcp.&#xA;  Maximum global control opcode value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00B0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_pause_da_ucast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx pause da ucast.&#xA;  Unicast destination address for pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00B4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_pause_da_ucast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx pause da ucast.&#xA;  Unicast destination address for pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00B8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_pause_da_mcast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx pause da mcast.&#xA;  Multicast destination address for pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00BC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_pause_da_mcast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx pause da mcast.&#xA;  Multicast destination address for pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00C0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_pause_sa_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx pause sa.&#xA;  Source address for pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00C4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_pause_sa_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx pause sa.&#xA;  Source address for pause processing.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_RSFEC_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_RSFEC_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00D0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rsfec_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rsfec enable.&#xA;  0 - Normal operation&#xA;  1 - Enable RS-FEC function.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rsfec_consortium_25g">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rsfec consortium 25g.&#xA;  This signal switches between IEEE Clause 108 and 25G Ethernet Consortium modes.&#xA;  0 - IEEE 802.3by mode.&#xA;  1 - 25G Consortium specification mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_rsfec_enable_indication">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx rsfec enable indication.&#xA;  0 - Bypass the error indication function (see IEEE Std 802.3by section 91.5.3.3).&#xA;  1 - Decoder indicates errors to the PCS sublayer&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rx_rsfec_enable_correction">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx rsfec enable correction.&#xA;  0 - Decoder performs error detection without error correction (see IEEE 802.3by Clause 91.5.3.3).&#xA;  1 - Decoder also performs error correction.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_rsfec_ieee_error_indication_mode">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rsfec ieee error indication mode.&#xA;  0 - If ctl_rx_rsfec_enable_correction and ctl_rx_rsfec_enable_indication are set to zero, the RS decoder is bypassed.&#xA;  1 - Core conforms to the IEEE RS-FEC specification.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_FEC_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_FEC_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00D4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_fec_rx_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl fec rx enable.&#xA;  0 - Normal operation&#xA;  1 - Enable the clause 74 FEC decoding of the received data.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_fec_tx_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl fec tx enable.&#xA;  0 - Normal operation&#xA;  1 - Enable the clause 74 FEC encoding on the transmitted data.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_fec_enable_error_to_pcs">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl fec enable error to pcs.&#xA;  0 - Normal operation&#xA;  1 - Clause 74 FEC enable error to PCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_AN_CONTROL_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_AN_CONTROL_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00E0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000002"/>
+              <FIELDS>
+                <FIELD NAME="ctl_autoneg_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl autoneg enable.&#xA;  0 - Normal operation&#xA;  1 - Enable signal for auto-negotiation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_autoneg_bypass">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl autoneg bypass.&#xA;  0 - Normal operation&#xA;  1 - Auto-negotiation is turned off, but the PCS is connected to the output to allow operation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_nonce_seed">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an nonce seed.&#xA;  8-bit seed to initialize the nonce field Polynomial generator.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_pseudo_sel">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an pseudo sel.&#xA;  Selects the polynomial generator  for the bit 49 random bit generator.&#xA;  0 - The polynomial is x7+x3+1.&#xA;  1 - The polynomial is x7+x6+1.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_restart_negotiation">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl restart negotiation.&#xA;  This input is used to trigger a restart of the auto-negotiation, regardless of what state the circuit is currently in.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_local_fault">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an local fault.&#xA;  This input signal is used to set the local_fault bit of the transmit link codeword.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_AN_CONTROL_REG2">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_AN_CONTROL_REG2"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00E4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_an_pause">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an pause.&#xA;  This is used to set the PAUSE bit, (C0), of the transmit link codeword.&#xA;  This signal might not be present if the core does not support pause.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_asmdir">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an asmdir.&#xA;  This is used to set the ASMDIR bit, (C1), of the transmit link codeword.&#xA;  This signal might not be present if the core does not support pause.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_fec_10g_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an fec 10g request.&#xA;  This signal is used to signal the link partner that the local station is requesting clause 74 FEC on the 10Gb/s lane protocols.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_fec_ability_override">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an fec ability override.&#xA;  1 - Then the FEC ability bit in the transmit link codeword is cleared.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_cl91_fec_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an cl91 fec request.&#xA;  This bit is used to request clause 91 FEC.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_cl91_fec_ability">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an cl91 fec ability.&#xA;  This bit is used to indicate clause 91 FEC ability.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="19"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="19"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_fec_25g_rs_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an fec 25g rs request.&#xA;  This signal is used to signal the link partner that the local station is requesting rs FEC (clause 91 or 108) on the 25Gb/s lane protocols.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="20"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="20"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_fec_25g_baser_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an fec 25g baser request.&#xA;  Indicates the baser FEC request.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="21"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="21"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_AN_ABILITY">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_AN_ABILITY"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00F8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_an_ability_1000base_kx">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 1000base kx.&#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_10gbase_kx4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 10gbase kx4. &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_10gbase_kr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 10gbase kr.  &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_40gbase_kr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 40gbase kr4. &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_40gbase_cr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 40gbase cr4. &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_100gbase_cr10">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl_an_ability_100gbase_cr10. &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_100gbase_kp4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 100gbase kp4. &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_100gbase_kr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 100gbase kr4. &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_100gbase_cr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 100gbase cr4. &#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_25gbase_krcr_s">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 25gbase krcr s.&#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_25gbase_krcr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 25gbase krcr.&#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_25gbase_kr1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 25gbase kr1.&#xA;   0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;   1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_25gbase_cr1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 25gbase cr1.&#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_50gbase_kr2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 50gbase kr2.&#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_an_ability_50gbase_cr2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl an ability 50gbase cr2.&#xA;  0 - Indicates that the interface advertises that it doesn't supports the protocol.&#xA;  1 - Indicates that the interface advertises that it supports the protocol.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_LT_CONTROL_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_LT_CONTROL_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0100"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_lt_training_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt training enable.&#xA;  0 - When link training is disabled, all PCS lanes function in mission mode.&#xA;  1 - Enabled link training &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ctl_lt_restart_training">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt restart training.&#xA;  0 - Normal operation&#xA;  1 - This signal triggers a restart of link training regardless of the current state.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_LT_TRAINED_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_LT_TRAINED_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0104"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_lt_rx_trained">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt rx trained.&#xA;  1 - Indicates that the receiver finite impulse response (FIR) filter coefficients have all been set, and that the receiver portion of training is complete. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_LT_PRESET_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_LT_PRESET_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0108"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_lt_preset_to_tx">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt preset to tx.&#xA;  0 - Normal operation. Doesn't set any value the preset bit.&#xA;  1 - set the value of the preset bit that is transmitted to the link partner in the control block of the training frame. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_LT_INIT_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_LT_INIT_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x010C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_lt_initialize_to_tx">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt initialize to tx.&#xA;  To set the value of the initialize bit that is transmitted to the link partner in the control block of the training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_LT_SEED_REG0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_LT_SEED_REG0"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0110"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_lt_pseudo_seed0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt pseudo seed0.&#xA;  This 11-bit signal seeds the training pattern generator.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="11"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CONFIGURATION_LT_COEFFICIENT_REG0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="CONFIGURATION_LT_COEFFICIENT_REG0"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0130"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_lt_k_p1_to_tx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt k p1 to tx0.&#xA;  This 2-bit field is used to set the value of the k+1 coefficient update field that is transmitted to the link partner in the control block of the training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="ctl_lt_k0_to_tx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl ltk0 to tx0.&#xA;  This 2-bit field is used to set the value of the k0 coefficient update field that is transmitted to the link partner in the control block of the training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="ctl_lt_k_m1_to_tx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt k m1 to tx0.&#xA;  This 2-bit field is used to set the value of the k-1 coefficient update field that  is transmitted to the link partner in the control block of the training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="ctl_lt_stat_p1_to_tx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt stat p1 to tx0.&#xA;  This 2-bit field is used to set the value of the k+1 coefficient update status that is transmitted to the link partner in the status block of the training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="ctl_lt_stat0_to_tx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl lt stat0 to tx0.&#xA;  This 2-bit field is used to set the value of the k0 coefficient update status that is transmitted to the link partner in the status block of the training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="ctl_lt_stat_m1_to_tx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl_lt_stat_m1_to_tx0.&#xA;  This 2-bit field is used to set the value of the k-1 coefficient update status  that is transmitted to the link partner in the status block of the training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="USER_REG_0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="USER_REG_0"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0134"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="user_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="user register0.&#xA;  User-defined signal from the AXI4-Reg map user_reg0 register.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="SWITCH_CORE_SPEED_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="SWITCH_CORE_SPEED_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0138"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="axi_ctl_core_mode_switch">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="axi ctl core mode switch.&#xA;  0 - Normal operation&#xA;  1 - Enables the mode switch line rate from 10G and 25G and vice versa.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TX_CONFIGURATION_1588_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="TX_CONFIGURATION_1588_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0140"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="ctl_tx_latency">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl tx latency&#xA;  This is the static latency of the TX path of the core including the GT.&#xA;  The MSB 16 bits indicate the delay in ns and the LSB 16 bits indicate sub ns values.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="RX_CONFIGURATION_1588_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="RX_CONFIGURATION_1588_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0144"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="ctl_rx_latency">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="ctl rx latency&#xA;  This is the static latency of the RX path of the core including the GT.&#xA;  The MSB 16 bits indicate the delay in ns and the LSB 16 bits indicate sub ns values.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_STATUS_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_STATUS_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0400"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_local_fault">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx local fault.&#xA;  0 - Normal operation&#xA;  1 - Indicates the receive decoder state machine is in the TX_INIT state. This output is level sensitive. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_tx_gmii_fifo_ovf_1h_r_out">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx gmii fifo ovf 1h r out.&#xA;  TX FIFO overflow.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_tx_gmii_fifo_unf_1h_r_out">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx gmii fifo unf 1h r out.&#xA;  TX FIFO underflow.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_tx_bad_parity">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx bad parity.&#xA;  Increment on any clock cycle where the  user-generated parity is calculated as  incorrect by the Tx parity checking logic.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_STATUS_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_STATUS_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0404"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_hi_ber">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx hi ber.&#xA;  High Bit Error Rate Indicator.&#xA;  1 - the BER is too high as defined by IEEE Std. 802.3. Corresponds to MDIO register bit 3.32.1 as defined in Clause 49.2.14.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_remote_fault">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx remote fault.&#xA;   0 - Remote fault condition does not exist.&#xA;   1 - It indicates a remote fault condition was detected. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_local_fault">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx local fault.&#xA;  1 - indicates the receive decoder state machine is in the RX_INIT state.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_internal_local_fault">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx internal local fault.&#xA;  1 - when an internal local fault is generated due to test pattern generation or high bit error rate. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_received_local_fault">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx received local fault.&#xA;  0 - Normal operation&#xA;  1 - when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine.&#xA;      Remains High as long as the fault condition persists.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_bad_preamble">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx bad preamble.&#xA;  0 - Indicates that an invalid preamble was not received.&#xA;  1 - Indicates that an invalid preamble was received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_bad_sfd">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx bad sfd.&#xA;  Increment bad SFD.&#xA;  0 - Indicates that an invalid SFD was not received.&#xA;  1 - Indicates that an invalid SFD was received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_got_signal_os">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx got signal os.&#xA;  Signal OS indication.&#xA;  1 - It indicates that a signal OS word was received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_STATUS_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_STATUS_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0408"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_fifo_error">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx fifo error.&#xA;  Transmit clock compensation FIFO error indicator.&#xA;  0 - Normal operation&#xA;  1 - Indicates the clock compensation FIFO under or overflowed.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_tx_ptp_fifo_read_error">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx ptp fifo read error.&#xA;  Transmit PTP FIFO read error.&#xA;  0 - Normal operation&#xA;  1 - Indicates that an error occurred during the PTP Tag read.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_tx_ptp_fifo_write_error">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx ptp fifo write error.&#xA;  Transmit PTP FIFO write error.&#xA;  0 - Normal operation&#xA;  1 - Indicates that an error occurred during the PTP Tag write. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_fifo_error">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx fifo error.&#xA;  Receive clock compensation FIFO error indicator.&#xA;  0 - Normal operation&#xA;  1 - Indicates the clock compensation FIFO under or overflowed.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_BLOCK_LOCK_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_BLOCK_LOCK_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x040C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000001"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_block_lock">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx block lock&#xA;  Block lock status.&#xA;  1 - Indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_RSFEC_STATUS_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_RSFEC_STATUS_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x043C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000003"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_rsfec_lane_alignment_status">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec lane alignment status.&#xA;  1 - Indicates that the RX RS-FEC block has achieved alignment on the data from the transceiver. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_rsfec_hi_ser">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec hi ser.&#xA;  Indicates high symbol error.&#xA;  1 - If the number of RS-FEC symbol errors in a window of 8192 codewords exceeds the threshold of 417.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_FEC_STATUS_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_FEC_STATUS_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0448"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00010001"/>
+              <FIELDS>
+                <FIELD NAME="stat_fec_rx_lock">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat fec rx lock.&#xA;  1 - while the ctl_fec_rx_enable is asserted when the FEC decoder detects the frame boundary.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_fec_lock_error">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat fec lock error.&#xA;  1 - If the FEC decoder has been unable to detect the frame boundary after about 5 ms. It is cleared when the frame boundary is detected.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_RSFEC_STATUS_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_RSFEC_STATUS_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x044C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000001"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_rsfec_lane_alignment_status">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx rsfec lane alignment status.&#xA;  1 - Indicates that the TX RS-FEC block has achieved alignment on the incoming PCS data.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TSN_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TSN_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x049C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_mm_verify">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx mm verify.&#xA;  Indicates verification status.&#xA;  0 - Indicates that verification is complete.&#xA;  1 - Indicates that verification is successful.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_FLOW_CONTROL_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_FLOW_CONTROL_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0450"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_pause_valid">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx pause valid.&#xA;  If a bit of this bus is set to 1, the core has transmitted a pause packet. If bit[8] is set to 1, a global pause packet is transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="9"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_FLOW_CONTROL_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_FLOW_CONTROL_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0454"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_pause_req">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx pause req.&#xA;  Pause request signal.&#xA;  When the RX receives a valid pause frame, it sets the corresponding bit of this bus to a 1 and keep it at 1 until the pause packet has been processed.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="9"/>
+                </FIELD>
+                <FIELD NAME="stat_rx_pause_valid">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx pause valid.&#xA;  This bus indicates that a pause packet was received and the associated quanta on the stat_rx_pause_quanta[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x Ethernet MAC Pause packet is received, bit[8] is set to 1.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="9"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_AN_STATUS">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_AN_STATUS"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0458"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_an_fec_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an fec enable.&#xA;  Used to enable the use of clause 74 FEC on the link.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_rs_fec_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an rs fec enable.&#xA;  Used to enable the use of clause 91 FEC on the link.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_autoneg_complete">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an autoneg complete.&#xA;  1 - Indicates the auto-negotiation is complete and rx link status from the PCS has been received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_parallel_detection_fault">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an parallel detection fault.&#xA;  1 - Indicated a parallel detection fault during auto-negotiation.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_tx_pause_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an tx pause enable.&#xA;  1 - Enable station-to-station (global) pause packet generation in the transmit path to control data flow in the receive path.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_rx_pause_enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an rx pause enable.&#xA;  1 - Enable station-to-station (global) pause packet interpretation in the receive path, in order to control data flow from the transmitter.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_valid">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability valid.&#xA;  1 - Indicates when all of the link partner advertisements become valid.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_autoneg_able">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp autoneg able.&#xA;  1 - Indicates that the link partner is able to perform auto-negotiation.&#xA;      It becomes valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_pause">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp pause.&#xA;  1 - Indicates the advertised value of the PAUSE bit, (C0), in the receive link codeword from the link partner.&#xA;      It becomes valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_asm_dir">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp asm dir.&#xA;  1 - Indicates the advertised value of the ASMDIR bit, (C1), in the receive link codeword from the link partner.&#xA;      It becomes valid when the output signal  stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_rf">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp rf.&#xA;  1 - Indicates link partner remote fault.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_fec_10g_ability">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp fec 10g ability.&#xA;  1 - Indicates the clause 74 FEC ability associated with 10Gb/s lane protocols that is being advertised by the link partner.&#xA;      It becomes valid when the output signal stat_an_lp_ability_valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_fec_10g_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp fec 10g request.&#xA;  1 - Indicates that the link partner is requesting that the clause 74 FEC be used on the 10Gb/s lane protocols.&#xA;      It becomes valid when the output signal stat_an_lp_ability_valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_extended_ability_valid">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp extended ability valid.&#xA;  1 - It indicates that the detected extended abilities are valid.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_extended_fec">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability extended fec.&#xA;  Indicates the extended FEC abilities as defined in Schedule 3.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_fec_25g_rs_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp fec 25g rs request.&#xA;  1 - Indicates that the link partner is requesting the clause 91 (or 108) rs FEC be used for the 25gb/s lane protocols. &#xA;      It becomes valid when the output signal stat_an_lp_ability_valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_fec_25g_baser_request">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp fec 25g baser request.&#xA;  1 - Indicates that the link partner is requesting the clause 74 FEC be used for the 25Gb/s lane base-r protocols.&#xA;      It becomes valid when the output signal stat_an_lp_ability_valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="19"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="19"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_AN_ABILITY">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_AN_ABILITY"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x045C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_an_lp_ability_1000base_kx">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 1000base kx.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_10gbase_kx4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 10gbase kx4.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_10gbase_kr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 10gbase kr.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_40gbase_kr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 40gbase kr4.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_40gbase_cr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 40gbase cr4.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_100gbase_cr10">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 100gbase cr10.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_100gbase_kp4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 100gbase kp4.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_100gbase_kr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 100gbase kr4.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_100gbase_cr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 100gbase cr4.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_25gbase_krcr_s">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 25gbase krcr_s.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_25gbase_krcr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 25gbase krcr.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_25gbase_kr1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 25gbase kr1.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_25gbase_cr1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 25gbase cr1.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_50gbase_kr2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 50gbase kr2.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_an_lp_ability_50gbase_cr2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an lp ability 50gbase cr2.&#xA;  1 - Indicates that the protocol is advertised as supported by the link partner.&#xA;      They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_AN_LINK_CTL">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_AN_LINK_CTL"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0460"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_an_link_cntl_1000base_kx">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 1000base kx.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_10gbase_kx4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 10gbase kx4.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_10gbase_kr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 10gbase kr.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_40gbase_kr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 40gbase kr4.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_40gbase_cr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 40gbase cr4.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_100gbase_cr10">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 100gbase cr10.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_100gbase_kp4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 100gbase kp4.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_100gbase_kr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 100gbase kr4.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_100gbase_cr4">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 100gbase cr4.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_25gbase_krcr_s">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 25gbase krcr_s.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_25gbase_krcr">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 25gbase krcr.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="20"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="20"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_25gbase_kr1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 25gbase kr1.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="22"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="22"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_25gbase_cr1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 25gbase cr1.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_50gbase_kr2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 50gbase kr2.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="26"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="26"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_an_link_cntl_50gbase_cr2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat an link cntl 50gbase cr2.&#xA;  Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. &#xA;  Settings are as follows:&#xA;    00 - DISABLE; PCS is disconnected&#xA;    01 - SCAN_FOR_CARRIER; RX is connected to PCS&#xA;    11 - ENABLE; PCS is connected for mission mode operation&#xA;    10 - not used&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="28"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="28"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_LT_STATUS_REG1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_LT_STATUS_REG1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0464"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_lt_initialize_from_rx">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt initialize from rx.&#xA;  This signal reflects the value of the initialize control bit received in the control block from the link partner.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_preset_from_rx">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt preset from rx.&#xA;  This signal reflects the value of the preset control bit received in the control block from the link partner.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_LT_STATUS_REG2">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_LT_STATUS_REG2"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0468"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_lt_training">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt training.&#xA;  1 - Indicates when the respective link training state machine is performing link training.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_frame_lock">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt frame lock.&#xA;  1 - Asserted when link training has begun.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_LT_STATUS_REG3">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_LT_STATUS_REG3"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x046C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_lt_signal_detect">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt signal detect.&#xA;  1 - Indicates when the respective link training state machine has entered the SEND_DATA state, in which normal PCS operation can resume.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_training_fail">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt training fail.&#xA;  1 - Asserted during link training if the corresponding link training state machine detects a time-out during the training period.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_LT_STATUS_REG4">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_LT_STATUS_REG4"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0470"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_lt_rx_sof">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt rx sof.&#xA;  1 - For 1 RX SerDes clock cycle to indicate the start of the link training frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_LT_COEFFICIENT0_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_LT_COEFFICIENT0_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0474"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_lt_k_p1_from_rx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt k p1 from rx0.&#xA;  This 2-bit field indicates the update control bits for the k+1 coefficient, as received from the link partner in the control block.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_k0_from_rx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt k0 from rx0.&#xA;  This 2-bit field indicates the update control bits for the k0 coefficient, as received from the link partner in the control block.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_k_m1_from_rx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt k m1 from rx0.&#xA;  This 2-bit field indicates the update control bits for the k-1 coefficient, as received from the link partner in the control block.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_stat_p1_from_rx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt stat p1 from rx0.&#xA;  This 2-bit field indicates the update status bits for the k+1 coefficient, as received from the link partner in the status block.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_stat0_from_rx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt stat0 from rx0.&#xA;  This 2-bit field indicates the update status bits for the k0 coefficient, as received from the link partner in the status block.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="stat_lt_stat_m1_from_rx0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat lt stat m1 from rx0.&#xA;  This 2-bit field indicates the update status bits for the k-1 coefficient, as received from the link partner in the status block.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_VALID_CTRL_CODE">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_VALID_CTRL_CODE"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0494"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_valid_ctrl_code">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx valid ctrl code.&#xA;  1 - Indicates that a PCS block with a valid control code was received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_CORE_SPEED_REG">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_CORE_SPEED_REG"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0498"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_core_speed">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat core speed.&#xA;  0 - Standalone 25G&#xA;  1 - Standalone 10G&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="runtime_switchable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="runtime switchable.&#xA;  0 - Runtime Switchable 25G&#xA;  1 - Runtime Switchable 10G&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STATUS_CYCLE_COUNT_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STATUS_CYCLE_COUNT_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0500"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_cycle_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat cycle reg0.&#xA;  Contains a count of the number of RX core clock cycles between TICK_REG writes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STATUS_CYCLE_COUNT_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STATUS_CYCLE_COUNT_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0504"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_cycle_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat cycle reg1.&#xA;  Contains a count of the number of RX core clock cycles between TICK_REG writes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_FRAMING_ERR_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_FRAMING_ERR_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0648"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_framing_err_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx framing err reg0.&#xA;  RX sync header bits framing error.&#xA;  Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane.&#xA;  The value of the bus is only valid when the corresponding stat_rx_framing_err_valid is a 1.&#xA;  The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_FRAMING_ERR_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_FRAMING_ERR_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x064C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_framing_err_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx framing err reg1.&#xA;  RX sync header bits framing error.&#xA;  Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane.&#xA;  The value of the bus is only valid when the corresponding stat_rx_framing_err_valid is a 1.&#xA;  The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_BAD_CODE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_BAD_CODE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0660"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_bad_code_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx bad code reg0.&#xA;  Increment for 64B/66B code violations.&#xA;  This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3-2015. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_BAD_CODE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_BAD_CODE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0664"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_bad_code_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx bad code reg1.&#xA;  Increment for 64B/66B code violations.&#xA;  This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3-2015.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_ERROR_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_ERROR_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0668"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_error_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx error reg0.&#xA;  Test pattern mismatch increment.&#xA;  A non-zero value in any cycle indicates a mismatch occurred for the test pattern in the RX core.&#xA;  This output is only active when ctl_rx_test_pattern is set.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_ERROR_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_ERROR_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x066C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_error_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx error reg1.&#xA;  Test pattern mismatch increment.&#xA;  A non-zero value in any cycle indicates a mismatch occurred for the test pattern in the RX core.&#xA;  This output is only active when ctl_rx_test_pattern is set.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_RSFEC_CORRECTED_CW_INC_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_RSFEC_CORRECTED_CW_INC_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0670"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_rsfec_corrected_cw_inc_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec corrected cw inc reg0.&#xA;  Increment for corrected errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_RSFEC_CORRECTED_CW_INC_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_RSFEC_CORRECTED_CW_INC_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0674"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_rsfec_corrected_cw_inc_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec corrected cw inc reg1.&#xA;  Increment for corrected errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_RSFEC_UNCORRECTED_CW_INC_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_RSFEC_UNCORRECTED_CW_INC_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0678"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_rsfec_uncorrected_cw_inc_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec uncorrected cw inc reg0.&#xA;  Increment for uncorrected errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_RSFEC_UNCORRECTED_CW_INC_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_RSFEC_UNCORRECTED_CW_INC_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x067C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_rsfec_uncorrected_cw_inc_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec uncorrected cw inc reg1.&#xA;  Increment for uncorrected errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_RSFEC_ERR_COUNT0_INC_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_RSFEC_ERR_COUNT0_INC_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0680"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_rsfec_err_count0_inc_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec err count inc reg0.&#xA;  Increment for detected errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_RSFEC_ERR_COUNT0_INC_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_RSFEC_ERR_COUNT0_INC_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0684"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_rsfec_err_count0_inc_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx rsfec err count inc reg1.&#xA;  Increment for detected errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_FRAME_ERROR_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_FRAME_ERROR_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x06A0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_frame_error_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx frame error reg0.&#xA;  Increment for packets with tx_axis_tuser set to indicate an End of Packet(EOP) abort.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_FRAME_ERROR_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_FRAME_ERROR_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x06A4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_frame_error_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx frame error reg1.&#xA;  Increment for packets with tx_axis_tuser set to indicate an End of Packet(EOP) abort.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_PACKETS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_PACKETS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0700"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_packets_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total packets reg0.&#xA;  Increment for the total number of packets transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_PACKETS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_PACKETS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0704"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_packets_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total packets reg1.&#xA;  Increment for the total number of packets transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_GOOD_PACKETS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_GOOD_PACKETS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0708"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_good_packets_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total good packets reg0.&#xA;  Increment for the total number of good packets transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_GOOD_PACKETS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_GOOD_PACKETS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x070C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_good_packets_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total good packets reg1.&#xA;  Increment for the total number of good packets transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0710"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total bytes reg0.&#xA;  Increment for the total number of bytes transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0714"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total bytes reg1.&#xA;  Increment for the total number of bytes transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_GOOD_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_GOOD_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0718"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_good_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total good bytes reg0.&#xA;  Increment for the total number of good bytes transmitted.&#xA;  This value is only non-zero when a packet is transmitted completely and contains no errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_TOTAL_GOOD_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_TOTAL_GOOD_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x071C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_total_good_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx total good bytes reg1.&#xA;  Increment for the total number of good bytes transmitted.&#xA;  This value is only non-zero when a packet is transmitted completely and contains no errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_64_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_64_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0720"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_64_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 64 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 64 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_64_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_64_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0724"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_64_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 64 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 64 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_65_127_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_65_127_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0728"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_65_127_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 65 - 127 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 65 to 127 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_65_127_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_65_127_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x072C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_65_127_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 65-127 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 65 to 127 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_128_255_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_128_255_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0730"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_128_255_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 128-255 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 128 to 255 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_128_255_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_128_255_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0734"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_128_255_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 128-255 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 128 to 255 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_256_511_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_256_511_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0738"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_256_511_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 256-511 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 256 to 511 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_256_511_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_256_511_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x073C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_256_511_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 256-511 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 256 to 511 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_512_1023_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_512_1023_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0740"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_512_1023_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 512-1023 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 512 to 1,023 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_512_1023_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_512_1023_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0744"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_512_1023_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 512-1023 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 512 to 1,023 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1024_1518_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1024_1518_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0748"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1024_1518_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1024-1518 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1024_1518_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1024_1518_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x074C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1024_1518_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1024-1518 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1519_1522_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1519_1522_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0750"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1519_1522_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1519-1522 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1519_1522_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1519_1522_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0754"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1519_1522_bytes__reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1519-1522 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1523_1548_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1523_1548_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0758"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1523_1548_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1523-1548 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1523_1548_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1523_1548_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x075C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1523_1548_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1523-1548 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1549_2047_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1549_2047_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0760"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1549_2047_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1549-2047 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_1549_2047_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_1549_2047_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0764"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_1549_2047_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 1549-2047 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_2048_4095_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_2048_4095_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0768"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_2048_4095_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 2048-4095 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 2,048 to 4,095 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_2048_4095_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_2048_4095_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x076C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_2048_4095_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 2048-4095 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 2,048 to 4,095 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_4096_8191_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_4096_8191_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0770"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_4096_8191_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 4096-8191 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_4096_8191_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_4096_8191_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0774"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_4096_8191_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 4096-8191 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_8192_9215_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_8192_9215_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0778"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_8192_9215_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 8192-9215 bytes reg0.&#xA;  Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_8192_9215_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_8192_9215_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x077C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_8192_9215_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet 8192-9215 bytes reg1.&#xA;  Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_LARGE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_LARGE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0780"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_large_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet large reg0.&#xA;  Increment for all packets that are more than 9,215 bytes long.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_LARGE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_LARGE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0784"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_large_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet large reg1.&#xA;  Increment for all packets that are more than 9,215 bytes long.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_SMALL_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_SMALL_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0788"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_small_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet small reg0.&#xA;  Increment for all packets that are less than 64 bytes long.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PACKET_SMALL_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PACKET_SMALL_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x078C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_packet_small_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx packet small reg1.&#xA;  Increment for all packets that are less than 64 bytes long.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_BAD_FCS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_BAD_FCS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07B8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_bad_fcs_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx bad fcs reg0.&#xA;  Increment for packets greater than 64 bytes that have FCS errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_BAD_FCS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_BAD_FCS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07BC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_bad_fcs_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx bad fcs reg1.&#xA;  Increment for packets greater than 64 bytes that have FCS errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_UNICAST_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_UNICAST_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07D0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_unicast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx unicast reg0.&#xA;  Increment for good unicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_UNICAST_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_UNICAST_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07D4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_unicast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx unicast reg1.&#xA;  Increment for good unicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MULTICAST_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MULTICAST_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07D8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_multicast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx multicast reg0.&#xA;  Increment for good multicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MULTICAST_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MULTICAST_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07DC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_multicast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx multicast reg1.&#xA;  Increment for good multicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_BROADCAST_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_BROADCAST_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07E0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_broadcast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx broadcast reg0.&#xA;  Increment for good broadcast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_BROADCAST_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_BROADCAST_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07E4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_broadcast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx broadcast reg1.&#xA;  Increment for good broadcast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_VLAN_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_VLAN_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07E8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_vlan_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx vlan reg0.&#xA;  Increment for good 802.1Q tagged VLAN packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_VLAN_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_VLAN_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07EC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_vlan_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx vlan reg1.&#xA;  Increment for good 802.1Q tagged VLAN packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PAUSE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PAUSE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07F0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_pause_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx pause reg0.&#xA;  Increment for 802.3x MAC Pause Packet with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_PAUSE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_PAUSE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07F4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_pause_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx pause reg1.&#xA;  Increment for 802.3x MAC Pause Packet with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_USER_PAUSE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_USER_PAUSE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07F8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_user_pause_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx user pause reg0.&#xA;  Increment for Priority based pause packets with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_USER_PAUSE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_USER_PAUSE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x07FC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_user_pause_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx user pause reg1.&#xA;  Increment for Priority based pause packets with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_PACKETS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_PACKETS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0808"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_packets_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total packets reg0.&#xA;  Increment for the total number of packets received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_PACKETS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_PACKETS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x080C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_packets_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total packets reg1.&#xA;  Increment for the total number of packets received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_GOOD_PACKETS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_GOOD_PACKETS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0810"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_good_packets_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total good packets reg0.&#xA;  Increment for the total number of good bytes received.&#xA;  This value is only non-zero when a packet is received completely and contains no errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_GOOD_PACKETS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_GOOD_PACKETS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0814"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_good_packets_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total good packets reg1.&#xA;  Increment for the total number of good bytes received.&#xA;  This value is only non-zero when a packet is received completely and contains no errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0818"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total bytes reg0.&#xA;  Increment for the total number of bytes received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x081C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total bytes reg1.&#xA;  Increment for the total number of bytes received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_GOOD_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_GOOD_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0820"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_good_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total good bytes reg0.&#xA;  Increment for the total number of good bytes received.&#xA;  This value is only non-zero when a packet is received completely and contains no errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOTAL_GOOD_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOTAL_GOOD_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0824"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_total_good_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx total good bytes reg1.&#xA;  Increment for the total number of good bytes received.&#xA;  This value is only non-zero when a packet is received completely and contains no errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_64_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_64_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0828"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_64_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 64 bytes reg0.&#xA;  Increment for good and bad packets received that contain 64 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_64_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_64_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x082C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_64_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 64 bytes reg1.&#xA;  Increment for good and bad packets received that contain 64 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_65_127_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_65_127_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0830"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_65_127_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 65-127 bytes reg0.&#xA;  Increment for good and bad packets received that contain 65 to 127 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_65_127_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_65_127_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0834"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_65_127_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 65-127 bytes reg1.&#xA;  Increment for good and bad packets received that contain 65 to 127 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_128_255_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_128_255_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0838"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_128_255_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 128-255 bytes reg0.&#xA;  Increment for good and bad packets received that contain 128 to 255 bytes. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_128_255_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_128_255_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x083C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_128_255_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 128-255 bytes reg1.&#xA;  Increment for good and bad packets received that contain 128 to 255 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_256_511_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_256_511_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0840"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_256_511_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 256-511 bytes reg0.&#xA;  Increment for good and bad packets received that contain 256 to 511 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_256_511_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_256_511_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0844"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_256_511_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 256-511 bytes reg1.&#xA;  Increment for good and bad packets received that contain 256 to 511 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_512_1023_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_512_1023_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0848"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_512_1023_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 512-1023 bytes reg0.&#xA;  Increment for good and bad packets received that contain 512 to 1,023 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_512_1023_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_512_1023_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x084C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_512_1023_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 512-1023 bytes reg1.&#xA;  Increment for good and bad packets received that contain 512 to 1,023 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1024_1518_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1024_1518_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0850"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1024_1518_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1024-1518 bytes reg0.&#xA;  Increment for good and bad packets received that contain 1,024 to 1,518 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1024_1518_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1024_1518_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0854"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1024_1518_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1024-1518 bytes reg1.&#xA;  Increment for good and bad packets received that contain 1,024 to 1,518 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1519_1522_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1519_1522_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0858"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1519_1522_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1519-1522 bytes reg0.&#xA;  Increment for good and bad packets received that contain 1519 to 1522 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1519_1522_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1519_1522_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x085C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1519_1522_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1519-1522 bytes reg1.&#xA;  Increment for good and bad packets received that contain 1519 to 1522 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1523_1548_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1523_1548_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0860"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1523_1548_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1523-1548 bytes reg0.&#xA;  Increment for good and bad packets received that contain 1,523 to 1,548 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1523_1548_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1523_1548_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0864"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1523_1548_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1523-1548 bytes reg1.&#xA;  Increment for good and bad packets received that contain 1,523 to 1,548 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1549_2047_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1549_2047_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0868"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1549_2047_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1549-2047 bytes reg0.&#xA;  Increment for good and bad packets received that contain 1,549 to 2,047 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_1549_2047_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_1549_2047_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x086C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_1549_2047_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 1549-2047 bytes reg1.&#xA;  Increment for good and bad packets received that contain 1,549 to 2,047 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_2048_4095_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_2048_4095_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0870"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_2048_4095_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 2048-4095 bytes reg0.&#xA;  Increment for good and bad packets received that contain 2,048 to 4,095 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_2048_4095_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_2048_4095_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0874"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_2048_4095_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 2048-4095 bytes reg1.&#xA;  Increment for good and bad packets received that contain 2,048 to 4,095 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_4096_8191_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_4096_8191_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0878"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_4096_8191_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 4096-8191 bytes reg0.&#xA;  Increment for good and bad packets received that contain 4,096 to 8,191 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_4096_8191_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_4096_8191_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x087C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_4096_8191_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 4096-8191 bytes reg1.&#xA;  Increment for good and bad packets received that contain 4,096 to 8,191 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_8192_9215_BYTES_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_8192_9215_BYTES_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0880"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_8192_9215_bytes_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 8192-9215 bytes reg0.&#xA;  Increment for good and bad packets received that contain 8,192 to 9,215 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_8192_9215_BYTES_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_8192_9215_BYTES_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0884"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_8192_9215_bytes_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet 8192-9215 bytes reg1.&#xA;  Increment for good and bad packets received that contain 8,192 to 9,215 bytes.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_LARGE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_LARGE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0888"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_large_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet large reg0.&#xA;  Increment for all packets that are more than 9,215 bytes long.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_LARGE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_LARGE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x088C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_large_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet large reg1.&#xA;  Increment for all packets that are more than 9,215 bytes long.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_SMALL_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_SMALL_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0890"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_small_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet small reg0.&#xA;  Increment for all packets that are less than 64 bytes long.&#xA;  Packets that are less than four bytes are dropped.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_SMALL_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_SMALL_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0894"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_small_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet small reg1.&#xA;  Increment for all packets that are less than 64 bytes long.&#xA;  Packets that are less than four bytes are dropped.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_UNDERSIZE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_UNDERSIZE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0898"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_undersize_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx undersize reg0.&#xA;  Increment for packets shorter than ctl_rx_min_packet_len with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_UNDERSIZE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_UNDERSIZE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x089C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_undersize_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx undersize reg1.&#xA;  Increment for packets shorter than ctl_rx_min_packet_len with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_FRAGMENT_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_FRAGMENT_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8A0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_fragment_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx fragment reg0.&#xA;  Increment for packets shorter than ctl_rx_min_packet_len with bad FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_FRAGMENT_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_FRAGMENT_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8A4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_fragment_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx fragment reg1.&#xA;  Increment for packets shorter than ctl_rx_min_packet_len with bad FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_OVERSIZE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_OVERSIZE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08A8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_oversize_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx oversize reg0.&#xA;  Increment for packets longer than ctl_rx_max_packet_len with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_OVERSIZE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_OVERSIZE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08AC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_oversize_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx oversize reg1.&#xA;  Increment for packets longer than ctl_rx_max_packet_len with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOOLONG_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOOLONG_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08B0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_toolong_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx toolong reg0.&#xA;  Increment for packets longer than ctl_rx_max_packet_len with good and bad FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TOOLONG_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TOOLONG_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08B4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_toolong_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx toolong reg1.&#xA;  Increment for packets longer than ctl_rx_max_packet_len with good and bad FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_JABBER_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_JABBER_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08B8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_jabber_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx jabber reg0.&#xA;  Increment for packets longer than ctl_rx_max_packet_len with bad FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_JABBER_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_JABBER_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08BC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_jabber_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx jabber reg1.&#xA;  Increment for packets longer than ctl_rx_max_packet_len with bad FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_BAD_FCS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_BAD_FCS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08C0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_bad_fcs_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx bad fcs reg0.&#xA;  Bad FCS indicator.&#xA;  The value on this bus indicates packets received with a bad FCS, but not a stomped FCS during a cycle.&#xA;  This output is pulsed for one clock cycle to indicate an error condition.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_BAD_FCS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_BAD_FCS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08C4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_bad_fcs_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx bad fcs reg1.&#xA;  Bad FCS indicator.&#xA;  The value on this bus indicates packets received with a bad FCS, but not a stomped FCS during a cycle.&#xA;  This output is pulsed for one clock cycle to indicate an error condition.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_BAD_FCS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_BAD_FCS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08C8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_bad_fcs_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet bad fcs reg0.&#xA;  Increment for packets between 64 and ctl_rx_max_packet_len bytes that have Frame Check Sequence (FCS) errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PACKET_BAD_FCS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PACKET_BAD_FCS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08CC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_packet_bad_fcs_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx packet bad fcs reg1.&#xA;  Increment for packets between 64 and ctl_rx_max_packet_len bytes that have Frame Check Sequence (FCS) errors.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_STOMPED_FCS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_STOMPED_FCS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08D0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_stomped_fcs_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx stomped fcs reg0.&#xA;  Stomped FCS indicator.&#xA;  The value on this bus indicates the packets were received with a stomped FCS.&#xA;  A stomped FCS is defined as the bitwise inverse of the expected good FCS.&#xA;  This output is pulsed for one clock cycle to indicate the stomped condition.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_STOMPED_FCS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_STOMPED_FCS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08D4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_stomped_fcs_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx stomped fcs reg1.&#xA;  Stomped FCS indicator.&#xA;  The value on this bus indicates the packets were received with a stomped FCS.&#xA;  A stomped FCS is defined as the bitwise inverse of the expected good FCS.&#xA;  This output is pulsed for one clock cycle to indicate the stomped condition.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_UNICAST_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_UNICAST_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08D8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_unicast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx unicast reg0.&#xA;  Increment for good unicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_UNICAST_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_UNICAST_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08DC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_unicast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx unicast reg1.&#xA;  Increment for good unicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MULTICAST_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MULTICAST_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08E0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_multicast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx multicast reg0.&#xA;  Increment for good multicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MULTICAST_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MULTICAST_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08E4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_multicast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx multicast reg1.&#xA;  Increment for good multicast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_BROADCAST_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_BROADCAST_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08E8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_broadcast_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx broadcast reg0.&#xA;  Increment for good broadcast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_BROADCAST_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_BROADCAST_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08EC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_broadcast_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx broadcast reg1.&#xA;  Increment for good broadcast packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_VLAN_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_VLAN_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08F0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_vlan_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx vlan reg0.&#xA;  Increment for good 802.1Q tagged VLAN packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_VLAN_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_VLAN_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08F4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_vlan_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx vlan reg1.&#xA;  Increment for good 802.1Q tagged VLAN packets.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PAUSE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PAUSE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08F8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_pause_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx pause reg0.&#xA;  Increment for 802.3x MAC Pause packet with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_PAUSE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_PAUSE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08FC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_pause_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx pause reg1.&#xA;  Increment for 802.3x MAC Pause packet with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_USER_PAUSE_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_USER_PAUSE_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0900"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_user_pause_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx user pause reg0.&#xA;  Increment for priority based pause packets with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_USER_PAUSE_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_USER_PAUSE_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0904"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_user_pause_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx user pause reg1.&#xA;  Increment for priority based pause packets with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_INRANGEERR_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_INRANGEERR_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0908"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_inrangeerr_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx inrangeerr reg0.&#xA;  Increment for packets with Length field error but with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_INRANGEERR_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_INRANGEERR_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x090C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_inrangeerr_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx inrangeerr reg1.&#xA;  Increment for packets with Length field error but with good FCS.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TRUNCATED_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TRUNCATED_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0910"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_truncated_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx truncated reg0.&#xA;  Packet truncation indicator.&#xA;  1 - Indicates that the current packet in flight is truncated due to its length exceeding ctl_rx_max_packet_len[14:0].&#xA;      This output is pulsed for one clock cycle to indicate the truncated condition.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TRUNCATED_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TRUNCATED_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0914"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_truncated_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx truncated reg1.&#xA;  Packet truncation indicator.&#xA;  1 - Indicates that the current packet in flight is truncated due to its length exceeding ctl_rx_max_packet_len[14:0].&#xA;      This output is pulsed for one clock cycle to indicate the truncated condition.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TEST_PATTERN_MISMATCH_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TEST_PATTERN_MISMATCH_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0918"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_test_pattern_mismatch_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx test pattern mismatch reg0.&#xA;  Test pattern mismatch increment.&#xA;  A non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core.&#xA;  This output is only active when ctl_rx_test_pattern is set to a 1.&#xA;  This output can be used to generate MDIO register as defined in Clause 45.&#xA;  This output is pulsed for one clock cycle.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_TEST_PATTERN_MISMATCH_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_TEST_PATTERN_MISMATCH_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x091C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_test_pattern_mismatch_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx test pattern mismatch reg1.&#xA;  Test pattern mismatch increment.&#xA;  A non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core.&#xA;  This output is only active when ctl_rx_test_pattern is set to a 1.&#xA;  This output can be used to generate MDIO register as defined in Clause 45.&#xA;  This output is pulsed for one clock cycle.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_FEC_INC_CORRECT_COUNT_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_FEC_INC_CORRECT_COUNT_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0920"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_fec_inc_correct_count_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat fec inc correct count reg0.&#xA;  This signal will be asserted roughly every 32 words, while the ctl_rx_fec_enable is asserted, if the FEC decoder detected and corrected a bit errors in the corresponding frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_FEC_INC_CORRECT_COUNT_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_FEC_INC_CORRECT_COUNT_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0924"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_fec_inc_correct_count_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat fec inc correct count reg1.&#xA;  This signal will be asserted roughly every 32 words, while the ctl_rx_fec_enable is asserted, if the FEC decoder detected and corrected a bit errors in the corresponding frame.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_FEC_INC_CANT_CORRECT_COUNT_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_FEC_INC_CANT_CORRECT_COUNT_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0928"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_fec_inc_cant_correct_count_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat fec inc cant correct count reg0.&#xA;  This signal will be asserted roughly every 32 words, while the ctl_rx_fec_enable is asserted, if the FEC decoder detected bit.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_FEC_INC_CANT_CORRECT_COUNT_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_FEC_INC_CANT_CORRECT_COUNT_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x092C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_fec_inc_cant_correct_count_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat fec inc cant correct count reg1.&#xA;  This signal will be asserted roughly every 32 words, while the ctl_rx_fec_enable is asserted, if the FEC decoder detected bit.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MM_STATUS_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MM_STATUS_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0980"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_mm_status_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx mm status.&#xA;  1 - when a preemptable packet (initial fragment or complete packet) is transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MM_STATUS_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MM_STATUS_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0984"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_mm_status_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx mm status.&#xA;  1 - when a preemptable packet (initial fragment or complete packet) is transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MM_FRAGMENT_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MM_FRAGMENT_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0988"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_mm_fragment_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx mm fragment.&#xA;  1 - when a continuation fragment of an preemptable packet is transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MM_FRAGMENT_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MM_FRAGMENT_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x098C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_mm_fragment_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx mm fragment.&#xA;  1 - when a continuation fragment of an preemptable packet is transmitted.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MM_HOLD_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MM_HOLD_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0990"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_mm_hold_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx mm hold.&#xA;  Asserted when ctl_hold_request transitions from 1’b0 to 1’b1.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_TX_MM_HOLD_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_TX_MM_HOLD_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0994"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_tx_mm_hold_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat tx mm hold.&#xA;  Asserted when ctl_hold_request transitions from 1’b0 to 1’b1.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_ASSEMBLY_ERROR_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_ASSEMBLY_ERROR_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0998"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_assembly_error_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm assembly error.&#xA;  Asserted when errors are detected during fragment assembly.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_ASSEMBLY_ERROR_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_ASSEMBLY_ERROR_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x099C"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_assembly_error_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm assembly error.&#xA;  Asserted when errors are detected during fragment assembly.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_FRAME_SMD_ERROR_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_FRAME_SMD_ERROR_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x09A0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_frame_smd_error_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm frame smd error.&#xA;  Asserted when the frame fragment is rejected due to an incorrect SMD value or arriving with SMD-C when no frame is in progress.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_FRAME_SMD_ERROR_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_FRAME_SMD_ERROR_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x09A4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_frame_smd_error_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm frame smd error.&#xA;  Asserted when the frame fragment is rejected due to an incorrect SMD value or arriving with SMD-C when no frame is in progress.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_FRAME_ASSEMBLY_OK_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_FRAME_ASSEMBLY_OK_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x09A8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_frame_assembly_ok_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm frame assembly ok.&#xA;  Asserted when all the preemptable frame fragments have been assembled and presented.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_FRAME_ASSEMBLY_OK_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_FRAME_ASSEMBLY_OK_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x09AC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_frame_assembly_ok_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm frame assembly ok.&#xA;  Asserted when all the preemptable frame fragments have been assembled and presented.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_FRAGMENT_LSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_FRAGMENT_LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x09B0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_fragment_reg0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm fragment.&#xA;  Asserted when a fragment frame is received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="STAT_RX_MM_FRAGMENT_MSB">
+              <PROPERTY NAME="DESCRIPTION" VALUE="STAT_RX_MM_FRAGMENT_MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x09B4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000"/>
+              <FIELDS>
+                <FIELD NAME="stat_rx_mm_fragment_reg1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="stat rx mm fragment.&#xA;  Asserted when a fragment frame is received.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+          </REGISTERS>
+        </ADDRESSBLOCK>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_CORE" VALUE="Ethernet MAC+PCS/PMA 64-bit"/>
+        <PARAMETER NAME="C_XGMII_INTERFACE" VALUE="1"/>
+        <PARAMETER NAME="C_LINE_RATE" VALUE="10"/>
+        <PARAMETER NAME="C_NUM_OF_CORES" VALUE="1"/>
+        <PARAMETER NAME="C_CLOCKING" VALUE="Asynchronous"/>
+        <PARAMETER NAME="C_DATA_PATH_INTERFACE" VALUE="AXI Stream"/>
+        <PARAMETER NAME="C_RUNTIME_SWITCH" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_PREEMPTION" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_PREEMPTION_FIFO" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_DATAPATH_PARITY" VALUE="0"/>
+        <PARAMETER NAME="C_BASE_R_KR" VALUE="BASE-R"/>
+        <PARAMETER NAME="C_INCLUDE_FEC_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_RSFEC_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_HYBRID_CMAC_RSFEC_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_AUTO_NEG_LT_LOGIC" VALUE="None"/>
+        <PARAMETER NAME="C_ANLT_CLK_IN_MHZ" VALUE="100"/>
+        <PARAMETER NAME="C_INCLUDE_AXI4_INTERFACE" VALUE="1"/>
+        <PARAMETER NAME="C_INCLUDE_STATISTICS_COUNTERS" VALUE="1"/>
+        <PARAMETER NAME="C_STATISTICS_REGS_TYPE" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_USER_FIFO" VALUE="1"/>
+        <PARAMETER NAME="C_ENABLE_TX_FLOW_CONTROL_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_RX_FLOW_CONTROL_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_TIME_STAMPING" VALUE="0"/>
+        <PARAMETER NAME="C_PTP_OPERATION_MODE" VALUE="2"/>
+        <PARAMETER NAME="C_PTP_CLOCKING_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_TX_LATENCY_ADJUST" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_VLANE_ADJUST_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_SYS_CLK" VALUE="4000"/>
+        <PARAMETER NAME="C_GT_LOCATION" VALUE="1"/>
+        <PARAMETER NAME="C_GT_REF_CLK_FREQ" VALUE="156.25"/>
+        <PARAMETER NAME="C_GT_DRP_CLK" VALUE="100.00"/>
+        <PARAMETER NAME="C_GT_TYPE" VALUE="GTH"/>
+        <PARAMETER NAME="C_GT_GROUP_SELECT" VALUE="Quad X0Y0"/>
+        <PARAMETER NAME="C_LANE1_GT_LOC" VALUE="X0Y0"/>
+        <PARAMETER NAME="C_LANE2_GT_LOC" VALUE="NA"/>
+        <PARAMETER NAME="C_LANE3_GT_LOC" VALUE="NA"/>
+        <PARAMETER NAME="C_LANE4_GT_LOC" VALUE="NA"/>
+        <PARAMETER NAME="C_INS_LOSS_NYQ" VALUE="30"/>
+        <PARAMETER NAME="C_RX_EQ_MODE" VALUE="AUTO"/>
+        <PARAMETER NAME="C_ENABLE_PIPELINE_REG" VALUE="0"/>
+        <PARAMETER NAME="C_ADD_GT_CNTRL_STS_PORTS" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_SHARED_LOGIC" VALUE="1"/>
+        <PARAMETER NAME="C_FAST_SIM_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_SWITCH_1_10_25G" VALUE="0"/>
+        <PARAMETER NAME="C_FAMILY_CHK" VALUE="zynquplus"/>
+        <PARAMETER NAME="IS_BOARD_PROJECT" VALUE="0"/>
+        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_AXIS_TKEEP_WIDTH" VALUE="7"/>
+        <PARAMETER NAME="C_TX_TOTAL_BYTES_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_GT_DIFFCTRL_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_MII_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_MII_CTRL_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_GTM_GROUP_SELECT" VALUE="NA"/>
+        <PARAMETER NAME="C_CMAC_CORE_SELECT" VALUE="CMACE4_X0Y0"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_xxv_ethernet_0_0"/>
+        <PARAMETER NAME="CORE" VALUE="Ethernet MAC+PCS/PMA 64-bit"/>
+        <PARAMETER NAME="XGMII_INTERFACE" VALUE="1"/>
+        <PARAMETER NAME="LINE_RATE" VALUE="10"/>
+        <PARAMETER NAME="NUM_OF_CORES" VALUE="1"/>
+        <PARAMETER NAME="CLOCKING" VALUE="Asynchronous"/>
+        <PARAMETER NAME="DATA_PATH_INTERFACE" VALUE="AXI Stream"/>
+        <PARAMETER NAME="RUNTIME_SWITCH" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PREEMPTION" VALUE="0"/>
+        <PARAMETER NAME="BASE_R_KR" VALUE="BASE-R"/>
+        <PARAMETER NAME="INCLUDE_FEC_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="INCLUDE_RSFEC_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="INCLUDE_HYBRID_CMAC_RSFEC_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="INCLUDE_AUTO_NEG_LT_LOGIC" VALUE="None"/>
+        <PARAMETER NAME="ANLT_CLK_IN_MHZ" VALUE="100"/>
+        <PARAMETER NAME="INCLUDE_AXI4_INTERFACE" VALUE="1"/>
+        <PARAMETER NAME="INCLUDE_STATISTICS_COUNTERS" VALUE="1"/>
+        <PARAMETER NAME="STATISTICS_REGS_TYPE" VALUE="0"/>
+        <PARAMETER NAME="INCLUDE_USER_FIFO" VALUE="1"/>
+        <PARAMETER NAME="ENABLE_TX_FLOW_CONTROL_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_RX_FLOW_CONTROL_LOGIC" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_TIME_STAMPING" VALUE="0"/>
+        <PARAMETER NAME="PTP_OPERATION_MODE" VALUE="2"/>
+        <PARAMETER NAME="PTP_CLOCKING_MODE" VALUE="0"/>
+        <PARAMETER NAME="TX_LATENCY_ADJUST" VALUE="0"/>
+        <PARAMETER NAME="SYS_CLK" VALUE="4000"/>
+        <PARAMETER NAME="ENABLE_VLANE_ADJUST_MODE" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PREEMPTION_FIFO" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_DATAPATH_PARITY" VALUE="0"/>
+        <PARAMETER NAME="GT_LOCATION" VALUE="1"/>
+        <PARAMETER NAME="RX_EQ_MODE" VALUE="AUTO"/>
+        <PARAMETER NAME="INS_LOSS_NYQ" VALUE="30"/>
+        <PARAMETER NAME="GT_REF_CLK_FREQ" VALUE="156.25"/>
+        <PARAMETER NAME="GT_DRP_CLK" VALUE="100.00"/>
+        <PARAMETER NAME="GT_TYPE" VALUE="GTH"/>
+        <PARAMETER NAME="GT_GROUP_SELECT" VALUE="Quad_X0Y0"/>
+        <PARAMETER NAME="LANE1_GT_LOC" VALUE="X0Y0"/>
+        <PARAMETER NAME="LANE2_GT_LOC" VALUE="NA"/>
+        <PARAMETER NAME="LANE3_GT_LOC" VALUE="NA"/>
+        <PARAMETER NAME="LANE4_GT_LOC" VALUE="NA"/>
+        <PARAMETER NAME="ENABLE_PIPELINE_REG" VALUE="0"/>
+        <PARAMETER NAME="ADD_GT_CNTRL_STS_PORTS" VALUE="0"/>
+        <PARAMETER NAME="INCLUDE_SHARED_LOGIC" VALUE="1"/>
+        <PARAMETER NAME="FAST_SIM_MODE" VALUE="0"/>
+        <PARAMETER NAME="SWITCH_1_10_25G" VALUE="0"/>
+        <PARAMETER NAME="CMAC_CORE_SELECT" VALUE="CMACE4_X0Y0"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+        <PARAMETER NAME="ETHERNET_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="DIFFCLK_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="GTM_GROUP_SELECT" VALUE="NA"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x80010000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x8001FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="gt_rxp_in_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxp_in_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="pl_eth_10g_imp" PORT="gt_rx_gt_port_0_p"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="gt_rxn_in_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxn_in_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="pl_eth_10g_imp" PORT="gt_rx_gt_port_0_n"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="gt_txp_out_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_txp_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="pl_eth_10g_imp" PORT="gt_tx_gt_port_0_p"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="gt_txn_out_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_txn_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="pl_eth_10g_imp" PORT="gt_tx_gt_port_0_n"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="I" NAME="rx_core_clk_0" SIGIS="clk" SIGNAME="xxv_ethernet_0_rx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_clk_out_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="txoutclksel_in_0" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_2_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconstant_2" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="rxoutclksel_in_0" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_2_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconstant_2" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="gtwiz_reset_tx_datapath_0" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="zups_util_vector_logic_0_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_util_vector_logic_0" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="gtwiz_reset_rx_datapath_0" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="zups_util_vector_logic_0_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_util_vector_logic_0" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="O" NAME="rxrecclkout_0" SIGIS="clk"/>
+        <PORT DIR="I" NAME="sys_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="124998749" DIR="I" NAME="dclk" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="O" NAME="tx_clk_out_0" SIGIS="clk" SIGNAME="xxv_ethernet_0_tx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_aclk"/>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="s_axis_aclk"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S01_ACLK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="O" NAME="rx_clk_out_0" SIGIS="clk" SIGNAME="xxv_ethernet_0_rx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="s_axis_aclk"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_core_clk_0"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S02_ACLK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="gt_refclk_p" SIGIS="clk" SIGNAME="xxv_ethernet_0_gt_refclk_p">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="pl_eth_10g_imp" PORT="gt_ref_clk_clk_p"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="gt_refclk_n" SIGIS="clk" SIGNAME="xxv_ethernet_0_gt_refclk_n">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="pl_eth_10g_imp" PORT="gt_ref_clk_clk_n"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="156250000" DIR="O" NAME="gt_refclk_out" SIGIS="clk"/>
+        <PORT DIR="O" NAME="gtpowergood_out_0" SIGIS="undef"/>
+        <PORT CLKFREQUENCY="124998749" DIR="I" NAME="s_axi_aclk_0" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn_0" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="pm_tick_0" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_awaddr_0" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_awaddr_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_awvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_awready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata_0" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wdata_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb_0" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wstrb_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp_0" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_bresp_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_bvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_bready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_araddr_0" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_araddr_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_arvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_arready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata_0" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rdata_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp_0" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rresp_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready_0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="rx_reset_0" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="dma_rx_rst_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dma_rx_rst" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="user_rx_reset_0" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="xxv_ethernet_0_user_rx_reset_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_rst_n" PORT="Op1"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="rx_axis_tvalid_0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="s_axis_tvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="63" NAME="rx_axis_tdata_0" RIGHT="0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="s_axis_tdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="rx_axis_tlast_0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="s_axis_tlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="rx_axis_tkeep_0" RIGHT="0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="s_axis_tkeep"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="rx_axis_tuser_0" SIGIS="undef" SIGNAME="rx_data_fifo_s_axis_tuser">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_data_fifo" PORT="s_axis_tuser"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="stat_rx_framing_err_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_framing_err_valid_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_local_fault_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_block_lock_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_valid_ctrl_code_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_status_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_remote_fault_0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="1" NAME="stat_rx_bad_fcs_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="1" NAME="stat_rx_stomped_fcs_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_truncated_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_internal_local_fault_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_received_local_fault_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_hi_ber_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_got_signal_os_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_test_pattern_mismatch_0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="3" NAME="stat_rx_total_bytes_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="1" NAME="stat_rx_total_packets_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="13" NAME="stat_rx_total_good_bytes_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_total_good_packets_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_bad_fcs_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_64_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_65_127_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_128_255_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_256_511_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_512_1023_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_1024_1518_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_1519_1522_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_1523_1548_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_1549_2047_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_2048_4095_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_4096_8191_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_8192_9215_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_small_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_packet_large_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_unicast_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_multicast_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_broadcast_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_oversize_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_toolong_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_undersize_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_fragment_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_vlan_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_inrangeerr_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_jabber_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_bad_code_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_bad_sfd_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_rx_bad_preamble_0" SIGIS="undef"/>
+        <PORT DIR="I" NAME="tx_reset_0" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="dma_tx_rst_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dma_tx_rst" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="user_tx_reset_0" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="xxv_ethernet_0_user_tx_reset_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_rst_n" PORT="Op1"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="tx_axis_tready_0" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="m_axis_tready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="tx_axis_tvalid_0" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="m_axis_tvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="63" NAME="tx_axis_tdata_0" RIGHT="0" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="m_axis_tdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="tx_axis_tlast_0" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="m_axis_tlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="tx_axis_tkeep_0" RIGHT="0" SIGIS="undef" SIGNAME="tx_data_fifo_m_axis_tkeep">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_data_fifo" PORT="m_axis_tkeep"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="tx_axis_tuser_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="tx_unfout_0" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="55" NAME="tx_preamblein_0" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_0_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconstant_0" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="55" NAME="rx_preambleout_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_local_fault_0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="3" NAME="stat_tx_total_bytes_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_total_packets_0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="13" NAME="stat_tx_total_good_bytes_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_total_good_packets_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_bad_fcs_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_64_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_65_127_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_128_255_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_256_511_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_512_1023_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_1024_1518_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_1519_1522_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_1523_1548_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_1549_2047_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_2048_4095_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_4096_8191_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_8192_9215_bytes_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_small_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_packet_large_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_unicast_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_multicast_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_broadcast_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_vlan_0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="stat_tx_frame_error_0" SIGIS="undef"/>
+        <PORT DIR="I" NAME="ctl_tx_send_rfi_0" SIGIS="undef" SIGNAME="xlconstant_1_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconstant_1" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ctl_tx_send_lfi_0" SIGIS="undef" SIGNAME="xlconstant_1_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconstant_1" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ctl_tx_send_idle_0" SIGIS="undef" SIGNAME="xlconstant_1_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconstant_1" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="user_reg0_0" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="I" NAME="qpllreset_in_0" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="External_Interface_gt_ref_clk" NAME="gt_ref_clk" TYPE="TARGET" VLNV="xilinx.com:interface:diff_clock:1.0">
+          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="CLK_N" PHYSICAL="gt_refclk_n"/>
+            <PORTMAP LOGICAL="CLK_P" PHYSICAL="gt_refclk_p"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="xxv_ethernet_0_gt_tx" NAME="gt_tx" TYPE="INITIATOR" VLNV="xilinx.com:display_xxv_ethernet:gt_ports_int:2.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="gt_port_0_n" PHYSICAL="gt_txn_out_0"/>
+            <PORTMAP LOGICAL="gt_port_0_p" PHYSICAL="gt_txp_out_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="External_Interface_gt_rx" NAME="gt_rx" TYPE="TARGET" VLNV="xilinx.com:display_xxv_ethernet:gt_ports_int:2.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="gt_port_0_n" PHYSICAL="gt_rxn_in_0"/>
+            <PORTMAP LOGICAL="gt_port_0_p" PHYSICAL="gt_rxp_in_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="zups_ps_axi_periph_M01_AXI" DATAWIDTH="32" NAME="s_axi_0" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="124998749"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr_0"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready_0"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid_0"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr_0"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready_0"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid_0"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready_0"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp_0"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid_0"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata_0"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready_0"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp_0"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid_0"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata_0"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready_0"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb_0"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="xxv_ethernet_0_axis_rx_0" NAME="axis_rx_0" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="1"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="rx_axis_tdata_0"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="rx_axis_tkeep_0"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="rx_axis_tlast_0"/>
+            <PORTMAP LOGICAL="TUSER" PHYSICAL="rx_axis_tuser_0"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="rx_axis_tvalid_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="tx_data_fifo_M_AXIS" NAME="axis_tx_0" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
+          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
+          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="TUSER_WIDTH" VALUE="1"/>
+          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="156250000"/>
+          <PARAMETER NAME="PHASE" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TDATA" PHYSICAL="tx_axis_tdata_0"/>
+            <PORTMAP LOGICAL="TKEEP" PHYSICAL="tx_axis_tkeep_0"/>
+            <PORTMAP LOGICAL="TLAST" PHYSICAL="tx_axis_tlast_0"/>
+            <PORTMAP LOGICAL="TREADY" PHYSICAL="tx_axis_tready_0"/>
+            <PORTMAP LOGICAL="TUSER" PHYSICAL="tx_axis_tuser_0"/>
+            <PORTMAP LOGICAL="TVALID" PHYSICAL="tx_axis_tvalid_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" NAME="ctl_tx_0" TYPE="TARGET" VLNV="xilinx.com:display_xxv_ethernet:ctrl_ports_int:2.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ctl_tx_send_idle" PHYSICAL="ctl_tx_send_idle_0"/>
+            <PORTMAP LOGICAL="ctl_tx_send_lfi" PHYSICAL="ctl_tx_send_lfi_0"/>
+            <PORTMAP LOGICAL="ctl_tx_send_rfi" PHYSICAL="ctl_tx_send_rfi_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" NAME="stat_tx_0" TYPE="INITIATOR" VLNV="xilinx.com:display_xxv_ethernet:statistics_ports_int:2.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="stat_tx_bad_fcs" PHYSICAL="stat_tx_bad_fcs_0"/>
+            <PORTMAP LOGICAL="stat_tx_broadcast" PHYSICAL="stat_tx_broadcast_0"/>
+            <PORTMAP LOGICAL="stat_tx_frame_error" PHYSICAL="stat_tx_frame_error_0"/>
+            <PORTMAP LOGICAL="stat_tx_local_fault" PHYSICAL="stat_tx_local_fault_0"/>
+            <PORTMAP LOGICAL="stat_tx_multicast" PHYSICAL="stat_tx_multicast_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_64_bytes" PHYSICAL="stat_tx_packet_64_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_65_127_bytes" PHYSICAL="stat_tx_packet_65_127_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_128_255_bytes" PHYSICAL="stat_tx_packet_128_255_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_256_511_bytes" PHYSICAL="stat_tx_packet_256_511_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_512_1023_bytes" PHYSICAL="stat_tx_packet_512_1023_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_1024_1518_bytes" PHYSICAL="stat_tx_packet_1024_1518_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_1519_1522_bytes" PHYSICAL="stat_tx_packet_1519_1522_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_1523_1548_bytes" PHYSICAL="stat_tx_packet_1523_1548_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_1549_2047_bytes" PHYSICAL="stat_tx_packet_1549_2047_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_2048_4095_bytes" PHYSICAL="stat_tx_packet_2048_4095_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_4096_8191_bytes" PHYSICAL="stat_tx_packet_4096_8191_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_8192_9215_bytes" PHYSICAL="stat_tx_packet_8192_9215_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_large" PHYSICAL="stat_tx_packet_large_0"/>
+            <PORTMAP LOGICAL="stat_tx_packet_small" PHYSICAL="stat_tx_packet_small_0"/>
+            <PORTMAP LOGICAL="stat_tx_total_bytes" PHYSICAL="stat_tx_total_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_total_good_bytes" PHYSICAL="stat_tx_total_good_bytes_0"/>
+            <PORTMAP LOGICAL="stat_tx_total_good_packets" PHYSICAL="stat_tx_total_good_packets_0"/>
+            <PORTMAP LOGICAL="stat_tx_total_packets" PHYSICAL="stat_tx_total_packets_0"/>
+            <PORTMAP LOGICAL="stat_tx_unicast" PHYSICAL="stat_tx_unicast_0"/>
+            <PORTMAP LOGICAL="stat_tx_vlan" PHYSICAL="stat_tx_vlan_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" NAME="stat_rx_0" TYPE="INITIATOR" VLNV="xilinx.com:display_xxv_ethernet:statistics_ports_int:2.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="stat_rx_bad_code" PHYSICAL="stat_rx_bad_code_0"/>
+            <PORTMAP LOGICAL="stat_rx_bad_fcs" PHYSICAL="stat_rx_bad_fcs_0"/>
+            <PORTMAP LOGICAL="stat_rx_bad_preamble" PHYSICAL="stat_rx_bad_preamble_0"/>
+            <PORTMAP LOGICAL="stat_rx_bad_sfd" PHYSICAL="stat_rx_bad_sfd_0"/>
+            <PORTMAP LOGICAL="stat_rx_block_lock" PHYSICAL="stat_rx_block_lock_0"/>
+            <PORTMAP LOGICAL="stat_rx_broadcast" PHYSICAL="stat_rx_broadcast_0"/>
+            <PORTMAP LOGICAL="stat_rx_fragment" PHYSICAL="stat_rx_fragment_0"/>
+            <PORTMAP LOGICAL="stat_rx_framing_err" PHYSICAL="stat_rx_framing_err_0"/>
+            <PORTMAP LOGICAL="stat_rx_framing_err_valid" PHYSICAL="stat_rx_framing_err_valid_0"/>
+            <PORTMAP LOGICAL="stat_rx_got_signal_os" PHYSICAL="stat_rx_got_signal_os_0"/>
+            <PORTMAP LOGICAL="stat_rx_hi_ber" PHYSICAL="stat_rx_hi_ber_0"/>
+            <PORTMAP LOGICAL="stat_rx_inrangeerr" PHYSICAL="stat_rx_inrangeerr_0"/>
+            <PORTMAP LOGICAL="stat_rx_internal_local_fault" PHYSICAL="stat_rx_internal_local_fault_0"/>
+            <PORTMAP LOGICAL="stat_rx_jabber" PHYSICAL="stat_rx_jabber_0"/>
+            <PORTMAP LOGICAL="stat_rx_local_fault" PHYSICAL="stat_rx_local_fault_0"/>
+            <PORTMAP LOGICAL="stat_rx_multicast" PHYSICAL="stat_rx_multicast_0"/>
+            <PORTMAP LOGICAL="stat_rx_oversize" PHYSICAL="stat_rx_oversize_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_64_bytes" PHYSICAL="stat_rx_packet_64_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_65_127_bytes" PHYSICAL="stat_rx_packet_65_127_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_128_255_bytes" PHYSICAL="stat_rx_packet_128_255_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_256_511_bytes" PHYSICAL="stat_rx_packet_256_511_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_512_1023_bytes" PHYSICAL="stat_rx_packet_512_1023_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_1024_1518_bytes" PHYSICAL="stat_rx_packet_1024_1518_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_1519_1522_bytes" PHYSICAL="stat_rx_packet_1519_1522_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_1523_1548_bytes" PHYSICAL="stat_rx_packet_1523_1548_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_1549_2047_bytes" PHYSICAL="stat_rx_packet_1549_2047_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_2048_4095_bytes" PHYSICAL="stat_rx_packet_2048_4095_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_4096_8191_bytes" PHYSICAL="stat_rx_packet_4096_8191_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_8192_9215_bytes" PHYSICAL="stat_rx_packet_8192_9215_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_bad_fcs" PHYSICAL="stat_rx_packet_bad_fcs_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_large" PHYSICAL="stat_rx_packet_large_0"/>
+            <PORTMAP LOGICAL="stat_rx_packet_small" PHYSICAL="stat_rx_packet_small_0"/>
+            <PORTMAP LOGICAL="stat_rx_received_local_fault" PHYSICAL="stat_rx_received_local_fault_0"/>
+            <PORTMAP LOGICAL="stat_rx_remote_fault" PHYSICAL="stat_rx_remote_fault_0"/>
+            <PORTMAP LOGICAL="stat_rx_stomped_fcs" PHYSICAL="stat_rx_stomped_fcs_0"/>
+            <PORTMAP LOGICAL="stat_rx_test_pattern_mismatch" PHYSICAL="stat_rx_test_pattern_mismatch_0"/>
+            <PORTMAP LOGICAL="stat_rx_toolong" PHYSICAL="stat_rx_toolong_0"/>
+            <PORTMAP LOGICAL="stat_rx_total_bytes" PHYSICAL="stat_rx_total_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_total_good_bytes" PHYSICAL="stat_rx_total_good_bytes_0"/>
+            <PORTMAP LOGICAL="stat_rx_total_good_packets" PHYSICAL="stat_rx_total_good_packets_0"/>
+            <PORTMAP LOGICAL="stat_rx_total_packets" PHYSICAL="stat_rx_total_packets_0"/>
+            <PORTMAP LOGICAL="stat_rx_truncated" PHYSICAL="stat_rx_truncated_0"/>
+            <PORTMAP LOGICAL="stat_rx_undersize" PHYSICAL="stat_rx_undersize_0"/>
+            <PORTMAP LOGICAL="stat_rx_unicast" PHYSICAL="stat_rx_unicast_0"/>
+            <PORTMAP LOGICAL="stat_rx_valid_ctrl_code" PHYSICAL="stat_rx_valid_ctrl_code_0"/>
+            <PORTMAP LOGICAL="stat_rx_vlan" PHYSICAL="stat_rx_vlan_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="23" FULLNAME="/zups/axi_pl_ps" HWVERSION="2.1" INSTANCE="zups_axi_pl_ps" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="NUM_SI" VALUE="3"/>
+        <PARAMETER NAME="NUM_MI" VALUE="1"/>
+        <PARAMETER NAME="STRATEGY" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
+        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+        <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_axi_pl_ps_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="interconnect_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S01_ACLK" SIGIS="clk" SIGNAME="xxv_ethernet_0_tx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="tx_clk_out_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S01_ARESETN" SIGIS="rst" SIGNAME="tx_rst_n_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="tx_rst_n" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S02_ACLK" SIGIS="clk" SIGNAME="xxv_ethernet_0_rx_clk_out_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="rx_clk_out_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S02_ARESETN" SIGIS="rst" SIGNAME="rx_rst_n_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rx_rst_n" PORT="Res"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="127" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="127" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S02_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S02_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S02_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S02_AXI_awlock" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="S02_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S02_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S02_AXI_awqos" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S02_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S02_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="63" NAME="S02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S02_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S02_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S02_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S02_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S02_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S01_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S01_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S01_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="S01_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="63" NAME="S01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_SG" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="zups_axi_pl_ps_M00_AXI" DATAWIDTH="128" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="M00_AXI_awid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="M00_AXI_bid"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="M00_AXI_arid"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M00_AXI_arregion"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="M00_AXI_rid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_MM2S" DATAWIDTH="64" NAME="S01_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S01_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S01_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S01_AXI_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S01_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S01_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S01_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S01_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S01_AXI_arqos"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S01_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S01_AXI_arready"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S01_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S01_AXI_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="S01_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S01_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S01_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_S2MM" DATAWIDTH="64" NAME="S02_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S02_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S02_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S02_AXI_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S02_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S02_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S02_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S02_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S02_AXI_awqos"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S02_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S02_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S02_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S02_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="S02_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S02_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S02_AXI_wready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S02_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S02_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S02_AXI_bready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="23" FULLNAME="/zups/ps_axi_periph" HWVERSION="2.1" INSTANCE="zups_ps_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="NUM_SI" VALUE="1"/>
+        <PARAMETER NAME="NUM_MI" VALUE="3"/>
+        <PARAMETER NAME="STRATEGY" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
+        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+        <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_ps_axi_periph_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="interconnect_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_ARESETN" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="39" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="S00_AXI_awuser" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awuser">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awuser"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="127" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="39" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="S00_AXI_aruser" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_aruser">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_aruser"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="127" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxigp2_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="39" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="39" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_awaddr_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_awaddr_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M01_AXI_awvalid" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_awvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_awvalid_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_awready" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_awready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_awready_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wdata_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_wdata_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wstrb_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_wstrb_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_wvalid" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_wvalid_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_wready" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_wready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_wready_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_bresp_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_bresp_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_bvalid" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_bvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_bvalid_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_bready" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_bready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_bready_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_araddr_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_araddr_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M01_AXI_arvalid" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_arvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_arvalid_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_arready" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_arready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_arready_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rdata_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_rdata_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rresp_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_rresp_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_rvalid" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rvalid_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_rvalid_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_rready" SIGIS="undef" SIGNAME="xxv_ethernet_0_s_axi_rready_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_rready_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_awid" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awaddr" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awlen" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awsize" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awburst" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awlock" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awcache" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awprot" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awregion" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awqos" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awuser" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_awvalid" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_awready" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_wdata" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_wstrb" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_wlast" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_wvalid" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_wready" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_bid" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_bresp" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_bvalid" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_bready" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arid" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_araddr" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arlen" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arsize" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arburst" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arlock" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arcache" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arprot" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arregion" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arqos" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_aruser" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_arvalid" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_arready" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_rid" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_rdata" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_rresp" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_rlast" SIGIS="undef"/>
+        <PORT DIR="I" NAME="M02_AXI_rvalid" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M02_AXI_rready" SIGIS="undef"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="zups_zynq_ultra_ps_e_0_M_AXI_HPM0_LPD" DATAWIDTH="128" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
+            <PORTMAP LOGICAL="AWUSER" PHYSICAL="S00_AXI_awuser"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
+            <PORTMAP LOGICAL="ARUSER" PHYSICAL="S00_AXI_aruser"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="zups_ps_axi_periph_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="zups_ps_axi_periph_M01_AXI" DATAWIDTH="32" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M01_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M01_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" NAME="M02_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="M02_AXI_awid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M02_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M02_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M02_AXI_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M02_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M02_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M02_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M02_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M02_AXI_awregion"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M02_AXI_awqos"/>
+            <PORTMAP LOGICAL="AWUSER" PHYSICAL="M02_AXI_awuser"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M02_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M02_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M02_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M02_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="M02_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M02_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M02_AXI_wready"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="M02_AXI_bid"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M02_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M02_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M02_AXI_bready"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="M02_AXI_arid"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M02_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M02_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M02_AXI_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M02_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M02_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M02_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M02_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M02_AXI_arregion"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M02_AXI_arqos"/>
+            <PORTMAP LOGICAL="ARUSER" PHYSICAL="M02_AXI_aruser"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M02_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M02_AXI_arready"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="M02_AXI_rid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M02_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M02_AXI_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="M02_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M02_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M02_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="13" FULLNAME="/zups/rst_ps8_0_99M" HWVERSION="5.0" INSTANCE="zups_rst_ps8_0_99M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
+        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
+        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
+        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_rst_ps8_0_99M_0"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="124998749" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zups_zynq_ultra_ps_e_0_pl_resetn0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
+        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
+        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
+        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
+        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="sys_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="ARESETN"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="zups_rst_ps8_0_99M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_aresetn_0"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_ARESETN"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_ARESETN"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_ARESETN"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_ARESETN"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M02_ARESETN"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="1" FULLNAME="/zups/util_vector_logic_0" HWVERSION="2.0" INSTANCE="zups_util_vector_logic_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="util_vector_logic" VLNV="xilinx.com:ip:util_vector_logic:2.0">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="C_OPERATION" VALUE="not"/>
+        <PARAMETER NAME="C_SIZE" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_util_vector_logic_0_0"/>
+        <PARAMETER NAME="LOGO_FILE" VALUE="data/sym_notgate.png"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="Op1" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="undef" SIGNAME="zups_zynq_ultra_ps_e_0_pl_resetn0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Res" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="undef" SIGNAME="zups_util_vector_logic_0_Res">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gtwiz_reset_rx_datapath_0"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gtwiz_reset_tx_datapath_0"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="4" FULLNAME="/zups/xlconcat_0" HWVERSION="2.1" INSTANCE="zups_xlconcat_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconcat" VLNV="xilinx.com:ip:xlconcat:2.1">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="IN0_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN1_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN2_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN3_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN4_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN5_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN6_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN7_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN8_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN9_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN10_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN11_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN12_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN13_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN14_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN15_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN16_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN17_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN18_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN19_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN20_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN21_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN22_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN23_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN24_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN25_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN26_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN27_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN28_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN29_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN30_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN31_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN32_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN33_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN34_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN35_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN36_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN37_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN38_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN39_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN40_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN41_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN42_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN43_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN44_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN45_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN46_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN47_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN48_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN49_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN50_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN51_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN52_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN53_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN54_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN55_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN56_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN57_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN58_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN59_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN60_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN61_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN62_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN63_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN64_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN65_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN66_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN67_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN68_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN69_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN70_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN71_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN72_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN73_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN74_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN75_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN76_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN77_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN78_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN79_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN80_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN81_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN82_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN83_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN84_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN85_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN86_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN87_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN88_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN89_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN90_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN91_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN92_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN93_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN94_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN95_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN96_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN97_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN98_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN99_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN100_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN101_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN102_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN103_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN104_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN105_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN106_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN107_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN108_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN109_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN110_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN111_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN112_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN113_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN114_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN115_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN116_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN117_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN118_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN119_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN120_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN121_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN122_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN123_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN124_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN125_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN126_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN127_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="dout_width" VALUE="2"/>
+        <PARAMETER NAME="NUM_PORTS" VALUE="2"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_xlconcat_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="In0" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_mm2s_introut">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="mm2s_introut"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="In1" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s2mm_introut">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s2mm_introut"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="zups_xlconcat_0_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_ps_irq0"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE CONFIGURABLE="TRUE" COREREVISION="3" FULLNAME="/zups/zynq_ultra_ps_e_0" HWVERSION="3.3" INSTANCE="zups_zynq_ultra_ps_e_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" IS_PL="FALSE" MODTYPE="zynq_ultra_ps_e" VLNV="xilinx.com:ip:zynq_ultra_ps_e:3.3">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=zynq_ultra_ps_e;v=v3_3;d=pg201-zynq-ultrascale-plus-processing-system.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="" INTERFACE="SAXIGP2" NAME="HP0_DDR_LOW" RANGE="0x80000000" USAGE="memory"/>
+      </ADDRESSBLOCKS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="" INTERFACE="SAXIGP2" NAME="HP0_PCIE_LOW" RANGE="0x10000000" USAGE="memory"/>
+      </ADDRESSBLOCKS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="" INTERFACE="SAXIGP2" NAME="HP0_QSPI" RANGE="0x20000000" USAGE="memory"/>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_DP_USE_AUDIO" VALUE="0"/>
+        <PARAMETER NAME="C_DP_USE_VIDEO" VALUE="0"/>
+        <PARAMETER NAME="C_MAXIGP0_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_MAXIGP1_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_MAXIGP2_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_SAXIGP0_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_SAXIGP1_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_SAXIGP2_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_SAXIGP3_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_SAXIGP4_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_SAXIGP5_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_SAXIGP6_DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP0" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP1" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP2" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP3" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP4" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP5" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP6" VALUE="0"/>
+        <PARAMETER NAME="C_EN_FIFO_ENET0" VALUE="0"/>
+        <PARAMETER NAME="C_EN_FIFO_ENET1" VALUE="0"/>
+        <PARAMETER NAME="C_EN_FIFO_ENET2" VALUE="0"/>
+        <PARAMETER NAME="C_EN_FIFO_ENET3" VALUE="0"/>
+        <PARAMETER NAME="C_PL_CLK0_BUF" VALUE="TRUE"/>
+        <PARAMETER NAME="C_PL_CLK1_BUF" VALUE="TRUE"/>
+        <PARAMETER NAME="C_PL_CLK2_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="C_PL_CLK3_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="C_TRACE_PIPELINE_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C_EN_EMIO_TRACE" VALUE="0"/>
+        <PARAMETER NAME="C_TRACE_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_USE_DEBUG_TEST" VALUE="0"/>
+        <PARAMETER NAME="C_SD0_INTERNAL_BUS_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C_SD1_INTERNAL_BUS_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C_NUM_F2P_0_INTR_INPUTS" VALUE="2"/>
+        <PARAMETER NAME="C_NUM_F2P_1_INTR_INPUTS" VALUE="1"/>
+        <PARAMETER NAME="C_EMIO_GPIO_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_FABRIC_RESETS" VALUE="1"/>
+        <PARAMETER NAME="PSU_VALUE_SILVERSION" VALUE="3"/>
+        <PARAMETER NAME="PSU__USE__DDR_INTF_REQUESTED" VALUE="0"/>
+        <PARAMETER NAME="PSU__EN_AXI_STATUS_PORTS" VALUE="0"/>
+        <PARAMETER NAME="PSU__PSS_REF_CLK__FREQMHZ" VALUE="33.333"/>
+        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__FREQMHZ" VALUE="33.333"/>
+        <PARAMETER NAME="PSU__VIDEO_REF_CLK__FREQMHZ" VALUE="33.333"/>
+        <PARAMETER NAME="PSU__AUX_REF_CLK__FREQMHZ" VALUE="33.333"/>
+        <PARAMETER NAME="PSU__GT_REF_CLK__FREQMHZ" VALUE="33.333"/>
+        <PARAMETER NAME="PSU__VIDEO_REF_CLK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__VIDEO_REF_CLK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CAN0__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CAN0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CAN0__GRP_CLK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CAN0__GRP_CLK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CAN1__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__CAN1__PERIPHERAL__IO" VALUE="MIO 24 .. 25"/>
+        <PARAMETER NAME="PSU__CAN1__GRP_CLK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CAN1__GRP_CLK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CAN0_LOOP_CAN1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DPAUX__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__DPAUX__PERIPHERAL__IO" VALUE="MIO 27 .. 30"/>
+        <PARAMETER NAME="PSU__ENET0__GRP_MDIO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ACT_DDR_FREQ_MHZ" VALUE="1066.656006"/>
+        <PARAMETER NAME="PSU__ENET0__GRP_MDIO__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM__TSU__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM__TSU__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__ENET0__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET0__FIFO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET0__PTP__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__ENET1__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET1__FIFO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET1__PTP__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__ENET1__GRP_MDIO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__FPGA_PL0_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__FPGA_PL1_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__FPGA_PL2_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__FPGA_PL3_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET1__GRP_MDIO__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__ENET2__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET2__FIFO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET2__PTP__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET2__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__ENET2__GRP_MDIO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET2__GRP_MDIO__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__ENET3__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__ENET3__FIFO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET3__PTP__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET3__PERIPHERAL__IO" VALUE="MIO 64 .. 75"/>
+        <PARAMETER NAME="PSU__ENET3__GRP_MDIO__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__ENET3__GRP_MDIO__IO" VALUE="MIO 76 .. 77"/>
+        <PARAMETER NAME="PSU__GPIO_EMIO__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__GPIO_EMIO__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GPIO0_MIO__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__GPIO0_MIO__IO" VALUE="MIO 0 .. 25"/>
+        <PARAMETER NAME="PSU__GPIO1_MIO__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__GPIO1_MIO__IO" VALUE="MIO 26 .. 51"/>
+        <PARAMETER NAME="PSU__GPIO2_MIO__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__GPIO2_MIO__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__I2C0__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__I2C0__PERIPHERAL__IO" VALUE="MIO 14 .. 15"/>
+        <PARAMETER NAME="PSU__I2C0__GRP_INT__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__I2C0__GRP_INT__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__I2C1__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__I2C1__PERIPHERAL__IO" VALUE="MIO 16 .. 17"/>
+        <PARAMETER NAME="PSU__I2C1__GRP_INT__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__I2C1__GRP_INT__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__I2C0_LOOP_I2C1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TESTSCAN__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENDPOINT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ROOTPORT_IO" VALUE="MIO 31"/>
+        <PARAMETER NAME="PSU__PCIE__LANE0__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PCIE__LANE0__IO" VALUE="GT Lane0"/>
+        <PARAMETER NAME="PSU__PCIE__LANE1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__LANE1__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__LANE2__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__LANE2__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__LANE3__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__LANE3__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__RESET__POLARITY" VALUE="Active Low"/>
+        <PARAMETER NAME="PSU__GT__LINK_SPEED" VALUE="HBR"/>
+        <PARAMETER NAME="PSU__GT__VLT_SWNG_LVL_4" VALUE="0"/>
+        <PARAMETER NAME="PSU__GT__PRE_EMPH_LVL_4" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB0__REF_CLK_SEL" VALUE="Ref Clk2"/>
+        <PARAMETER NAME="PSU__USB0__REF_CLK_FREQ" VALUE="26"/>
+        <PARAMETER NAME="PSU__USB1__REF_CLK_SEL" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__USB1__REF_CLK_FREQ" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM0__REF_CLK_SEL" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM0__REF_CLK_FREQ" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM1__REF_CLK_SEL" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM1__REF_CLK_FREQ" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM2__REF_CLK_SEL" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM2__REF_CLK_FREQ" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM3__REF_CLK_SEL" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEM3__REF_CLK_FREQ" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DP__REF_CLK_SEL" VALUE="Ref Clk3"/>
+        <PARAMETER NAME="PSU__DP__REF_CLK_FREQ" VALUE="27"/>
+        <PARAMETER NAME="PSU__SATA__REF_CLK_SEL" VALUE="Ref Clk1"/>
+        <PARAMETER NAME="PSU__SATA__REF_CLK_FREQ" VALUE="125"/>
+        <PARAMETER NAME="PSU__PCIE__REF_CLK_SEL" VALUE="Ref Clk0"/>
+        <PARAMETER NAME="PSU__PCIE__REF_CLK_FREQ" VALUE="100"/>
+        <PARAMETER NAME="PSU__DP__LANE_SEL" VALUE="Single Lower"/>
+        <PARAMETER NAME="PSU__PCIE__DEVICE_PORT_TYPE" VALUE="Root Port"/>
+        <PARAMETER NAME="PSU__PCIE__MAXIMUM_LINK_WIDTH" VALUE="x1"/>
+        <PARAMETER NAME="PSU__PCIE__LINK_SPEED" VALUE="5.0 Gb/s"/>
+        <PARAMETER NAME="PSU__PCIE__INTERFACE_WIDTH" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR0_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR0_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR0_SCALE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR0_64BIT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR0_SIZE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR0_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR0_PREFETCHABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR1_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR1_SCALE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR1_64BIT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR1_SIZE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR1_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR1_PREFETCHABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR2_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR2_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR2_SCALE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR2_64BIT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR2_SIZE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR2_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR2_PREFETCHABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR3_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR3_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR3_SCALE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR3_64BIT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR3_SIZE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR3_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR3_PREFETCHABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR4_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR4_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR4_SCALE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR4_64BIT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR4_SIZE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR4_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR4_PREFETCHABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR5_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR5_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR5_SCALE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR5_64BIT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR5_SIZE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__BAR5_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__BAR5_PREFETCHABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__EROM_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__EROM_SCALE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__EROM_SIZE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__EROM_VAL" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__CAP_SLOT_IMPLEMENTED" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__MAX_PAYLOAD_SIZE" VALUE="256 bytes"/>
+        <PARAMETER NAME="PSU__PCIE__LEGACY_INTERRUPT" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__VENDOR_ID" VALUE="0x10EE"/>
+        <PARAMETER NAME="PSU__PCIE__DEVICE_ID" VALUE="0xD011"/>
+        <PARAMETER NAME="PSU__PCIE__REVISION_ID" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__SUBSYSTEM_VENDOR_ID" VALUE="0x10EE"/>
+        <PARAMETER NAME="PSU__PCIE__SUBSYSTEM_ID" VALUE="0x7"/>
+        <PARAMETER NAME="PSU__PCIE__BASE_CLASS_MENU" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__SUB_CLASS_INTERFACE_MENU" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_BASE" VALUE="0x06"/>
+        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_SUB" VALUE="0x80"/>
+        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_INTERFACE" VALUE="0x0"/>
+        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_VALUE" VALUE="0x68000"/>
+        <PARAMETER NAME="PSU__PCIE__AER_CAPABILITY" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__CORRECTABLE_INT_ERR" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__HEADER_LOG_OVERFLOW" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__RECEIVER_ERR" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__SURPRISE_DOWN" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__FLOW_CONTROL_ERR" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__COMPLTION_TIMEOUT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__COMPLETER_ABORT" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__RECEIVER_OVERFLOW" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__ECRC_ERR" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__ACS_VIOLAION" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__UNCORRECTABL_INT_ERR" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MC_BLOCKED_TLP" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__ATOMICOP_EGRESS_BLOCKED" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__TLP_PREFIX_BLOCKED" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__ACS_VIOLATION" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MULTIHEADER" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__ECRC_CHECK" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__ECRC_GEN" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__PERM_ROOT_ERR_UPDATE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__CRS_SW_VISIBILITY" VALUE="1"/>
+        <PARAMETER NAME="PSU__PCIE__INTX_GENERATION" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__INTX_PIN" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__MSI_CAPABILITY" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MSI_64BIT_ADDR_CAPABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PCIE__MSIX_CAPABILITY" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MSIX_TABLE_SIZE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MSIX_TABLE_OFFSET" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MSIX_BAR_INDICATOR"/>
+        <PARAMETER NAME="PSU__PCIE__MSIX_PBA_OFFSET" VALUE="0"/>
+        <PARAMETER NAME="PSU__PCIE__MSIX_PBA_BAR_INDICATOR"/>
+        <PARAMETER NAME="PSU__PCIE__BRIDGE_BAR_INDICATOR" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU_IMPORT_BOARD_PRESET"/>
+        <PARAMETER NAME="PSU__PROTECTION__SUBSYSTEMS" VALUE="PMU Firmware:PMU"/>
+        <PARAMETER NAME="PSU__PROTECTION__MASTERS_TZ" VALUE="GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure"/>
+        <PARAMETER NAME="PSU__PROTECTION__MASTERS" VALUE="USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1"/>
+        <PARAMETER NAME="PSU__PROTECTION__DDR_SEGMENTS" VALUE="NONE"/>
+        <PARAMETER NAME="PSU__PROTECTION__OCM_SEGMENTS" VALUE="NONE"/>
+        <PARAMETER NAME="PSU__PROTECTION__LPD_SEGMENTS" VALUE="SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware"/>
+        <PARAMETER NAME="PSU__PROTECTION__FPD_SEGMENTS" VALUE="SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware"/>
+        <PARAMETER NAME="PSU__PROTECTION__DEBUG" VALUE="0"/>
+        <PARAMETER NAME="PSU__PROTECTION__SLAVES" VALUE="LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1"/>
+        <PARAMETER NAME="PSU__PROTECTION__PRESUBSYSTEMS" VALUE="NONE"/>
+        <PARAMETER NAME="PSU__PROTECTION__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDR_SW_REFRESH_ENABLED" VALUE="1"/>
+        <PARAMETER NAME="PSU__PROTECTION__LOCK_UNUSED_SEGMENTS" VALUE="0"/>
+        <PARAMETER NAME="PSU__EP__IP" VALUE="0"/>
+        <PARAMETER NAME="PSU__ACTUAL__IP" VALUE="1"/>
+        <PARAMETER NAME="SUBPRESET1" VALUE="Custom"/>
+        <PARAMETER NAME="SUBPRESET2" VALUE="Custom"/>
+        <PARAMETER NAME="PSU_UIPARAM_GENERATE_SUMMARY" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU_MIO_TREE_PERIPHERALS" VALUE="Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3"/>
+        <PARAMETER NAME="PSU_MIO_TREE_SIGNALS" VALUE="sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out"/>
+        <PARAMETER NAME="PSU_PERIPHERAL_BOARD_PRESET"/>
+        <PARAMETER NAME="PSU__NAND__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__NAND__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND__READY_BUSY__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND__READY0_BUSY__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND__READY1_BUSY__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND__READY_BUSY__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__NAND__READY0_BUSY__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__NAND__READY1_BUSY__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__NAND__CHIP_ENABLE__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND__CHIP_ENABLE__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__NAND__DATA_STROBE__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND__DATA_STROBE__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PJTAG__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PJTAG__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__AIBACK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__PLERROR__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PMU__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__EMIO_GPI__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__EMIO_GPO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__GPI0__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__GPI1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__GPI2__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__GPI3__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__GPI4__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__GPI5__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU__GPO0__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PMU__GPO1__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PMU__GPO2__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PMU__GPO3__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PMU__GPO4__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PMU__GPO5__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__PMU__GPI0__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__GPI1__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__GPI2__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__GPI3__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__GPI4__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__GPI5__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__PMU__GPO0__IO" VALUE="MIO 32"/>
+        <PARAMETER NAME="PSU__PMU__GPO1__IO" VALUE="MIO 33"/>
+        <PARAMETER NAME="PSU__PMU__GPO2__IO" VALUE="MIO 34"/>
+        <PARAMETER NAME="PSU__PMU__GPO3__IO" VALUE="MIO 35"/>
+        <PARAMETER NAME="PSU__PMU__GPO4__IO" VALUE="MIO 36"/>
+        <PARAMETER NAME="PSU__PMU__GPO5__IO" VALUE="MIO 37"/>
+        <PARAMETER NAME="PSU__PMU__GPO2__POLARITY" VALUE="low"/>
+        <PARAMETER NAME="PSU__PMU__GPO3__POLARITY" VALUE="low"/>
+        <PARAMETER NAME="PSU__PMU__GPO4__POLARITY" VALUE="low"/>
+        <PARAMETER NAME="PSU__PMU__GPO5__POLARITY" VALUE="low"/>
+        <PARAMETER NAME="PSU__CSU__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__IO" VALUE="MIO 0 .. 12"/>
+        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__MODE" VALUE="Dual Parallel"/>
+        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__DATA_MODE" VALUE="x4"/>
+        <PARAMETER NAME="PSU__QSPI__GRP_FBCLK__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__QSPI__GRP_FBCLK__IO" VALUE="MIO 6"/>
+        <PARAMETER NAME="PSU__SD0__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SD0__GRP_CD__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD0__GRP_CD__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SD0__GRP_POW__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD0__GRP_POW__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SD0__GRP_WP__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD0__GRP_WP__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SD0__SLOT_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SD0__RESET__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD0__DATA_TRANSFER_MODE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SD1__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SD1__PERIPHERAL__IO" VALUE="MIO 39 .. 51"/>
+        <PARAMETER NAME="PSU__SD1__GRP_CD__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SD1__GRP_CD__IO" VALUE="MIO 45"/>
+        <PARAMETER NAME="PSU__SD1__GRP_POW__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SD1__GRP_POW__IO" VALUE="MIO 43"/>
+        <PARAMETER NAME="PSU__SD1__GRP_WP__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SD1__GRP_WP__IO" VALUE="MIO 44"/>
+        <PARAMETER NAME="PSU__SD1__SLOT_TYPE" VALUE="SD 3.0"/>
+        <PARAMETER NAME="PSU__SD1__RESET__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD1__DATA_TRANSFER_MODE" VALUE="8Bit"/>
+        <PARAMETER NAME="PSU__DEVICE_TYPE" VALUE="EV"/>
+        <PARAMETER NAME="PSU_SMC_CYCLE_T0" VALUE="NA"/>
+        <PARAMETER NAME="PSU_SMC_CYCLE_T1" VALUE="NA"/>
+        <PARAMETER NAME="PSU_SMC_CYCLE_T2" VALUE="NA"/>
+        <PARAMETER NAME="PSU_SMC_CYCLE_T3" VALUE="NA"/>
+        <PARAMETER NAME="PSU_SMC_CYCLE_T4" VALUE="NA"/>
+        <PARAMETER NAME="PSU_SMC_CYCLE_T5" VALUE="NA"/>
+        <PARAMETER NAME="PSU_SMC_CYCLE_T6" VALUE="NA"/>
+        <PARAMETER NAME="PSU__SPI0__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI0__GRP_SS0__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI0__GRP_SS0__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI0__GRP_SS1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI0__GRP_SS1__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI0__GRP_SS2__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI0__GRP_SS2__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI1__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI1__GRP_SS0__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI1__GRP_SS0__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI1__GRP_SS1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI1__GRP_SS1__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI1__GRP_SS2__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SPI1__GRP_SS2__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SPI0_LOOP_SPI1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT" VALUE="APB"/>
+        <PARAMETER NAME="PSU__SWDT0__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SWDT0__CLOCK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SWDT0__RESET__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SWDT0__PERIPHERAL__IO" VALUE="EMIO"/>
+        <PARAMETER NAME="PSU__SWDT0__CLOCK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SWDT0__RESET__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SWDT1__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SWDT1__CLOCK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SWDT1__RESET__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SWDT1__PERIPHERAL__IO" VALUE="EMIO"/>
+        <PARAMETER NAME="PSU__SWDT1__CLOCK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SWDT1__RESET__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__UART0__BAUD_RATE" VALUE="115200"/>
+        <PARAMETER NAME="PSU__TRACE__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TRACE__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TRACE__WIDTH" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TRACE__INTERNAL_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="PSU_SD0_INTERNAL_BUS_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="PSU__TTC0__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__TTC0__CLOCK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC0__WAVEOUT__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC0__CLOCK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TTC0__WAVEOUT__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TTC0__PERIPHERAL__IO" VALUE="EMIO"/>
+        <PARAMETER NAME="PSU__TTC1__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__TTC1__PERIPHERAL__IO" VALUE="EMIO"/>
+        <PARAMETER NAME="PSU__UART1__BAUD_RATE" VALUE="115200"/>
+        <PARAMETER NAME="PSU__TTC1__CLOCK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC1__WAVEOUT__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC1__CLOCK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TTC1__WAVEOUT__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TTC2__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__TTC2__PERIPHERAL__IO" VALUE="EMIO"/>
+        <PARAMETER NAME="PSU__TTC2__CLOCK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC2__WAVEOUT__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC2__CLOCK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TTC2__WAVEOUT__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TTC3__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__TTC3__PERIPHERAL__IO" VALUE="EMIO"/>
+        <PARAMETER NAME="PSU__TTC3__CLOCK__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC3__WAVEOUT__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TTC3__CLOCK__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__TTC3__WAVEOUT__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSUPMU__PERIPHERAL__VALID" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDRC__AL" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__BANK_ADDR_COUNT" VALUE="2"/>
+        <PARAMETER NAME="PSU__DDRC__BUS_WIDTH" VALUE="64 Bit"/>
+        <PARAMETER NAME="PSU__DDRC__CL" VALUE="15"/>
+        <PARAMETER NAME="PSU__DDRC__CLOCK_STOP_EN" VALUE="0"/>
+        <PARAMETER NAME="PSU_DYNAMIC_DDR_CONFIG_EN" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__COL_ADDR_COUNT" VALUE="10"/>
+        <PARAMETER NAME="PSU__DDRC__RANK_ADDR_COUNT" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__CWL" VALUE="14"/>
+        <PARAMETER NAME="PSU__DDRC__BG_ADDR_COUNT" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDRC__DEVICE_CAPACITY" VALUE="8192 MBits"/>
+        <PARAMETER NAME="PSU__DDRC__DRAM_WIDTH" VALUE="16 Bits"/>
+        <PARAMETER NAME="PSU__DDRC__ECC" VALUE="Disabled"/>
+        <PARAMETER NAME="PSU__DDRC__ECC_SCRUB" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDRC__FREQ_MHZ" VALUE="1066.50"/>
+        <PARAMETER NAME="PSU__DDRC__HIGH_TEMP" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDRC__MEMORY_TYPE" VALUE="DDR 4"/>
+        <PARAMETER NAME="PSU__DDRC__PARTNO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDRC__ROW_ADDR_COUNT" VALUE="16"/>
+        <PARAMETER NAME="PSU__DDRC__SPEED_BIN" VALUE="DDR4_2133P"/>
+        <PARAMETER NAME="PSU__DDRC__T_FAW" VALUE="30.0"/>
+        <PARAMETER NAME="PSU__DDRC__T_RAS_MIN" VALUE="33"/>
+        <PARAMETER NAME="PSU__DDRC__T_RC" VALUE="47.06"/>
+        <PARAMETER NAME="PSU__DDRC__T_RCD" VALUE="15"/>
+        <PARAMETER NAME="PSU__DDRC__T_RP" VALUE="15"/>
+        <PARAMETER NAME="PSU__DDRC__TRAIN_DATA_EYE" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDRC__TRAIN_READ_GATE" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDRC__TRAIN_WRITE_LEVEL" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDRC__VREF" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDRC__VIDEO_BUFFER_SIZE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__BRC_MAPPING" VALUE="ROW_BANK_COL"/>
+        <PARAMETER NAME="PSU__DDRC__DIMM_ADDR_MIRROR" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__STATIC_RD_MODE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DDR4_MAXPWR_SAVING_EN" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__PWR_DOWN_EN" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DEEP_PWR_DOWN_EN" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__PLL_BYPASS" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DDR4_T_REF_MODE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DDR4_T_REF_RANGE" VALUE="Normal (0-85)"/>
+        <PARAMETER NAME="PSU__DDRC__DDR3_T_REF_RANGE" VALUE="NA"/>
+        <PARAMETER NAME="PSU__DDRC__DDR3L_T_REF_RANGE" VALUE="NA"/>
+        <PARAMETER NAME="PSU__DDRC__LPDDR3_T_REF_RANGE" VALUE="NA"/>
+        <PARAMETER NAME="PSU__DDRC__LPDDR4_T_REF_RANGE" VALUE="NA"/>
+        <PARAMETER NAME="PSU__DDRC__PHY_DBI_MODE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DM_DBI" VALUE="DM_NO_DBI"/>
+        <PARAMETER NAME="PSU__DDRC__COMPONENTS" VALUE="UDIMM"/>
+        <PARAMETER NAME="PSU__DDRC__PARITY_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DDR4_CAL_MODE_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DDR4_CRC_CONTROL" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__FGRM" VALUE="1X"/>
+        <PARAMETER NAME="PSU__DDRC__VENDOR_PART" VALUE="OTHERS"/>
+        <PARAMETER NAME="PSU__DDRC__SB_TARGET" VALUE="15-15-15"/>
+        <PARAMETER NAME="PSU__DDRC__LP_ASR" VALUE="manual normal"/>
+        <PARAMETER NAME="PSU__DDRC__DDR4_ADDR_MAPPING" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__SELF_REF_ABORT" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DERATE_INT_D" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDRC__ADDR_MIRROR" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__EN_2ND_CLK" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__LPDDR3_DUALRANK_SDP" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__PER_BANK_REFRESH" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__ENABLE_DP_SWITCH" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__ENABLE_LP4_SLOWBOOT" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__ENABLE_2T_TIMING" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__RD_DQS_CENTER" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_0_3" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_4_7" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_8_11" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_12_15" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_16_19" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_20_23" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_24_27" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_28_31" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_32_35" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_36_39" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_40_43" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_44_47" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_48_51" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_52_55" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_56_59" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_60_63" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_64_67" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDRC__DQMAP_68_71" VALUE="0"/>
+        <PARAMETER NAME="PSU_DDR_RAM_HIGHADDR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER NAME="PSU_DDR_RAM_HIGHADDR_OFFSET" VALUE="0x800000000"/>
+        <PARAMETER NAME="PSU_DDR_RAM_LOWADDR_OFFSET" VALUE="0x80000000"/>
+        <PARAMETER NAME="PSU__DDR_QOS_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT0_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT1_VN1_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT1_VN2_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT2_VN1_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT2_VN2_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT3_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT4_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_PORT5_TYPE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__DDR_QOS_RD_LPR_THRSHLD"/>
+        <PARAMETER NAME="PSU__DDR_QOS_RD_HPR_THRSHLD"/>
+        <PARAMETER NAME="PSU__DDR_QOS_WR_THRSHLD"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP0_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP0_WRQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP1_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP1_WRQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP2_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP2_WRQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP3_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_HP3_WRQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP0_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP0_WRQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP1_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP1_WRQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP2_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP2_WRQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP3_RDQOS"/>
+        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP3_WRQOS"/>
+        <PARAMETER NAME="PSU__OVERRIDE_HPX_QOS" VALUE="0"/>
+        <PARAMETER NAME="PSU__FP__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__PL__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__OCM_BANK0__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__OCM_BANK1__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__OCM_BANK2__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__OCM_BANK3__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__TCM0A__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__TCM0B__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__TCM1A__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__TCM1B__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__RPU__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__L2_BANK0__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__GPU_PP0__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__GPU_PP1__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__ACPU0__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__ACPU1__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__ACPU2__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__ACPU3__POWER__ON" VALUE="1"/>
+        <PARAMETER NAME="PSU__UART0__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__UART0__PERIPHERAL__IO" VALUE="MIO 18 .. 19"/>
+        <PARAMETER NAME="PSU__UART0__MODEM__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__UART1__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__UART1__PERIPHERAL__IO" VALUE="MIO 20 .. 21"/>
+        <PARAMETER NAME="PSU__UART1__MODEM__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__UART0_LOOP_UART1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB0__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__USB0__PERIPHERAL__IO" VALUE="MIO 52 .. 63"/>
+        <PARAMETER NAME="PSU__USB0__RESET__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB0__RESET__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__USB__RESET__MODE" VALUE="Boot Pin"/>
+        <PARAMETER NAME="PSU__USB__RESET__POLARITY" VALUE="Active Low"/>
+        <PARAMETER NAME="PSU__USB1__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__USB1__RESET__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB1__RESET__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__USB3_0__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__USB3_0__PERIPHERAL__IO" VALUE="GT Lane2"/>
+        <PARAMETER NAME="PSU__USB3_1__PERIPHERAL__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB3_1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__USB3_0__EMIO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB2_0__EMIO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB3_1__EMIO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB2_1__EMIO__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__USB3_0_HUB" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__USB3_1_HUB" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__ADMA" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__M_AXI_GP0" VALUE="0"/>
+        <PARAMETER NAME="PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST" VALUE="1"/>
+        <PARAMETER NAME="PSU__MAXIGP0__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__M_AXI_GP1" VALUE="0"/>
+        <PARAMETER NAME="PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST" VALUE="1"/>
+        <PARAMETER NAME="PSU__MAXIGP1__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__M_AXI_GP2" VALUE="1"/>
+        <PARAMETER NAME="PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST" VALUE="1"/>
+        <PARAMETER NAME="PSU__MAXIGP2__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_ACP" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_GP0" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP0" VALUE="0"/>
+        <PARAMETER NAME="PSU__SAXIGP0__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_GP1" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP1" VALUE="0"/>
+        <PARAMETER NAME="PSU__SAXIGP1__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_GP2" VALUE="1"/>
+        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP2" VALUE="0"/>
+        <PARAMETER NAME="PSU__SAXIGP2__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_GP3" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP3" VALUE="0"/>
+        <PARAMETER NAME="PSU__SAXIGP3__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_GP4" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP4" VALUE="0"/>
+        <PARAMETER NAME="PSU__SAXIGP4__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_GP5" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP5" VALUE="0"/>
+        <PARAMETER NAME="PSU__SAXIGP5__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_GP6" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP6" VALUE="0"/>
+        <PARAMETER NAME="PSU__SAXIGP6__DATA_WIDTH" VALUE="128"/>
+        <PARAMETER NAME="PSU__USE__S_AXI_ACE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TRACE_PIPELINE_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="PSU__EN_EMIO_TRACE" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__AUDIO" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__VIDEO" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__PROC_EVENT_BUS" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__FTM" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__CROSS_TRIGGER" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_IN_0" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_IN_1" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_IN_2" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_IN_3" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_OUT_0" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_OUT_1" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_OUT_2" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__CTI_OUT_3" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__GPO" VALUE="0"/>
+        <PARAMETER NAME="PSU__FTM__GPI" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__GDMA" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__IRQ" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__IRQ0" VALUE="1"/>
+        <PARAMETER NAME="PSU__USE__IRQ1" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__CLK0" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__CLK1" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__CLK2" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__CLK3" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__RST0" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__RST1" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__RST2" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__RST3" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__FABRIC__RST" VALUE="1"/>
+        <PARAMETER NAME="PSU__USE__RTC" VALUE="0"/>
+        <PARAMETER NAME="PSU__PRESET_APPLIED" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__EVENT_RPU" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__APU_LEGACY_INTERRUPT" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__RPU_LEGACY_INTERRUPT" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__STM" VALUE="0"/>
+        <PARAMETER NAME="PSU__USE__DEBUG__TEST" VALUE="0"/>
+        <PARAMETER NAME="PSU__HIGH_ADDRESS__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__DDR_HIGH_ADDRESS_GUI_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__EXPAND__LOWER_LPS_SLAVES" VALUE="0"/>
+        <PARAMETER NAME="PSU__EXPAND__CORESIGHT" VALUE="0"/>
+        <PARAMETER NAME="PSU__EXPAND__GIC" VALUE="0"/>
+        <PARAMETER NAME="PSU__EXPAND__FPD_SLAVES" VALUE="0"/>
+        <PARAMETER NAME="PSU__EXPAND__UPPER_LPS_SLAVES" VALUE="0"/>
+        <PARAMETER NAME="PSU_MIO_0_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_0_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_0_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_0_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_0_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_0_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_1_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_1_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_1_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_1_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_1_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_1_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_2_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_2_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_2_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_2_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_2_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_2_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_3_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_3_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_3_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_3_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_3_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_3_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_4_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_4_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_4_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_4_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_4_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_4_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_5_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_5_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_5_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_5_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_5_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_5_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_6_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_6_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_6_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_6_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_6_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_6_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_7_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_7_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_7_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_7_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_7_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_7_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_8_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_8_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_8_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_8_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_8_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_8_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_9_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_9_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_9_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_9_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_9_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_9_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_10_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_10_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_10_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_10_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_10_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_10_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_11_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_11_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_11_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_11_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_11_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_11_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_12_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_12_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_12_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_12_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_12_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_12_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_13_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_13_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_13_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_13_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_13_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_13_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_14_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_14_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_14_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_14_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_14_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_14_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_15_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_15_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_15_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_15_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_15_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_15_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_16_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_16_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_16_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_16_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_16_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_16_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_17_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_17_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_17_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_17_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_17_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_17_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_18_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_18_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_18_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_18_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_18_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_18_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_19_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_19_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_19_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_19_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_19_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_19_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_20_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_20_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_20_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_20_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_20_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_20_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_21_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_21_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_21_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_21_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_21_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_21_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_22_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_22_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_22_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_22_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_22_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_22_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_23_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_23_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_23_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_23_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_23_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_23_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_24_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_24_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_24_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_24_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_24_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_24_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_25_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_25_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_25_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_25_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_25_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_25_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_26_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_26_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_26_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_26_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_26_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_26_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_27_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_27_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_27_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_27_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_27_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_27_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_28_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_28_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_28_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_28_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_28_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_28_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_29_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_29_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_29_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_29_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_29_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_29_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_30_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_30_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_30_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_30_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_30_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_30_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_31_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_31_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_31_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_31_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_31_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_31_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_32_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_32_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_32_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_32_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_32_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_32_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_33_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_33_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_33_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_33_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_33_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_33_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_34_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_34_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_34_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_34_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_34_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_34_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_35_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_35_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_35_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_35_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_35_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_35_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_36_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_36_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_36_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_36_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_36_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_36_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_37_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_37_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_37_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_37_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_37_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_37_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_38_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_38_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_38_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_38_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_38_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_38_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_39_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_39_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_39_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_39_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_39_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_39_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_40_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_40_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_40_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_40_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_40_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_40_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_41_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_41_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_41_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_41_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_41_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_41_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_42_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_42_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_42_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_42_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_42_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_42_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_43_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_43_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_43_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_43_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_43_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_43_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_44_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_44_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_44_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_44_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_44_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_44_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_45_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_45_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_45_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_45_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_45_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_45_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_46_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_46_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_46_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_46_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_46_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_46_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_47_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_47_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_47_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_47_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_47_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_47_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_48_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_48_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_48_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_48_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_48_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_48_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_49_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_49_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_49_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_49_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_49_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_49_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_50_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_50_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_50_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_50_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_50_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_50_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_51_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_51_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_51_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_51_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_51_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_51_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_52_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_52_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_52_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_52_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_52_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_52_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_53_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_53_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_53_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_53_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_53_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_53_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_54_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_54_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_54_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_54_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_54_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_54_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_55_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_55_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_55_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_55_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_55_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_55_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_56_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_56_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_56_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_56_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_56_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_56_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_57_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_57_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_57_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_57_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_57_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_57_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_58_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_58_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_58_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_58_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_58_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_58_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_59_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_59_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_59_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_59_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_59_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_59_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_60_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_60_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_60_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_60_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_60_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_60_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_61_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_61_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_61_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_61_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_61_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_61_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_62_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_62_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_62_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_62_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_62_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_62_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_63_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_63_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_63_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_63_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_63_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_63_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_MIO_64_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_64_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_64_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_64_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_64_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_64_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_65_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_65_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_65_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_65_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_65_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_65_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_66_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_66_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_66_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_66_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_66_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_66_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_67_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_67_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_67_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_67_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_67_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_67_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_68_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_68_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_68_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_68_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_68_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_68_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_69_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_69_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_69_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_69_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_69_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_69_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_70_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_70_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_70_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_70_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_70_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_70_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_71_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_71_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_71_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_71_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_71_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_71_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_72_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_72_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_72_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_72_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_72_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_72_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_73_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_73_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_73_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_73_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_73_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_73_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_74_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_74_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_74_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_74_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_74_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_74_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_75_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_75_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_75_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_75_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_75_SLEW" VALUE="fast"/>
+        <PARAMETER NAME="PSU_MIO_75_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PSU_MIO_76_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_76_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_76_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_76_INPUT_TYPE" VALUE="cmos"/>
+        <PARAMETER NAME="PSU_MIO_76_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_76_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PSU_MIO_77_PULLUPDOWN" VALUE="pullup"/>
+        <PARAMETER NAME="PSU_MIO_77_DRIVE_STRENGTH" VALUE="12"/>
+        <PARAMETER NAME="PSU_MIO_77_POLARITY" VALUE="Default"/>
+        <PARAMETER NAME="PSU_MIO_77_INPUT_TYPE" VALUE="schmitt"/>
+        <PARAMETER NAME="PSU_MIO_77_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PSU_MIO_77_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PSU_BANK_0_IO_STANDARD" VALUE="LVCMOS18"/>
+        <PARAMETER NAME="PSU_BANK_1_IO_STANDARD" VALUE="LVCMOS18"/>
+        <PARAMETER NAME="PSU_BANK_2_IO_STANDARD" VALUE="LVCMOS18"/>
+        <PARAMETER NAME="PSU_BANK_3_IO_STANDARD" VALUE="LVCMOS33"/>
+        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FRACDATA" VALUE="0.000000"/>
+        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FRACDATA" VALUE="0.000000"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FRACDATA" VALUE="0.000000"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FRACDATA" VALUE="0.000000"/>
+        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FRACDATA" VALUE="0.000000"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__DIV2" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__DIV2" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__DIV2" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__DIV2" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__DIV2" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FBDIV" VALUE="72"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FBDIV" VALUE="64"/>
+        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FBDIV" VALUE="90"/>
+        <PARAMETER NAME="PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0" VALUE="5"/>
+        <PARAMETER NAME="PSU__DISPLAYPORT__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__DISPLAYPORT__LANE0__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__DISPLAYPORT__LANE0__IO" VALUE="GT Lane1"/>
+        <PARAMETER NAME="PSU__DISPLAYPORT__LANE1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__DISPLAYPORT__LANE1__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0" VALUE="5"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0" VALUE="20"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0" VALUE="19"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__SATA__PERIPHERAL__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SATA__LANE0__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__SATA__LANE0__IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__SATA__LANE1__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__SATA__LANE1__IO" VALUE="GT Lane3"/>
+        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0" VALUE="12"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0" VALUE="4"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0" VALUE="4"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0" VALUE="30"/>
+        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRL_APB__AFI6__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0" VALUE="25"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1" VALUE="3"/>
+        <PARAMETER NAME="PSU_USB3__DUAL_CLOCK_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB3__ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__USE__CLK" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0" VALUE="5"/>
+        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0" VALUE="-1"/>
+        <PARAMETER NAME="PSU__CRF_APB__GTGREF0__ENABLE" VALUE="NA"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FBDIV" VALUE="90"/>
+        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FBDIV" VALUE="90"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0" VALUE="12"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0" VALUE="12"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0" VALUE="12"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0" VALUE="12"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0" VALUE="6"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0" VALUE="6"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0" VALUE="6"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" VALUE="12"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0" VALUE="7"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0" VALUE="8"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0" VALUE="7"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0" VALUE="7"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0" VALUE="6"/>
+        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0" VALUE="6"/>
+        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0" VALUE="4"/>
+        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__DIVISOR0" VALUE="8"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0" VALUE="6"/>
+        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0" VALUE="15"/>
+        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0" VALUE="3"/>
+        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
+        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
+        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__SRCSEL" VALUE="APLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__SRCSEL" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" VALUE="VPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" VALUE="RPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" VALUE="RPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" VALUE="RPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__SRCSEL" VALUE="RPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__SRCSEL" VALUE="RPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__SRCSEL" VALUE="RPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" VALUE="APLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" VALUE="APLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" VALUE="DPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL" VALUE="NA"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
+        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL" VALUE="RPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__WDT_CLK_SEL__SELECT" VALUE="APB"/>
+        <PARAMETER NAME="PSU__FPD_SLCR__WDT_CLK_SEL__SELECT" VALUE="APB"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL" VALUE="APB"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL" VALUE="APB"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL" VALUE="APB"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL" VALUE="APB"/>
+        <PARAMETER NAME="PSU__CRF_APB__APLL_FRAC_CFG__ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__CRF_APB__ACPU__FRAC_ENABLED" VALUE="0"/>
+        <PARAMETER NAME="PSU__OVERRIDE__BASIC_CLOCK" VALUE="0"/>
+        <PARAMETER NAME="PSU__DLL__ISUSED" VALUE="1"/>
+        <PARAMETER NAME="PSU__PL_CLK0_BUF" VALUE="TRUE"/>
+        <PARAMETER NAME="PSU__PL_CLK1_BUF" VALUE="TRUE"/>
+        <PARAMETER NAME="PSU__PL_CLK2_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="PSU__PL_CLK3_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FRACFREQ" VALUE="27.138"/>
+        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FRACFREQ" VALUE="27.138"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FRACFREQ" VALUE="27.138"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FRACFREQ" VALUE="27.138"/>
+        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FRACFREQ" VALUE="27.138"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC0__ACT_FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC1__ACT_FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC2__ACT_FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC3__ACT_FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__WDT0__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__FPD_SLCR__WDT1__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ" VALUE="1199.988037"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ" VALUE="299.997009"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ" VALUE="24.999750"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ" VALUE="26.315527"/>
+        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ" VALUE="533.328003"/>
+        <PARAMETER NAME="PSU__DDR__INTERFACE__FREQMHZ" VALUE="533.500"/>
+        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ" VALUE="499.994995"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ" VALUE="124.998749"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ" VALUE="599.994019"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ" VALUE="599.994019"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ" VALUE="533.328003"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ" VALUE="-1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ" VALUE="124.998749"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" VALUE="124.998749"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" VALUE="187.498123"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ" VALUE="214"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ" VALUE="214"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ" VALUE="1000"/>
+        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ" VALUE="499.994995"/>
+        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ" VALUE="187.498123"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ" VALUE="499.994995"/>
+        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
+        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ" VALUE="499.994995"/>
+        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ" VALUE="1499.984985"/>
+        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ" VALUE="49.999500"/>
+        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" VALUE="19.999800"/>
+        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__FREQMHZ" VALUE="1200"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__FREQMHZ" VALUE="1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ" VALUE="300"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ" VALUE="25"/>
+        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ" VALUE="27"/>
+        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__FREQMHZ" VALUE="1067"/>
+        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ" VALUE="667"/>
+        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ" VALUE="600"/>
+        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ" VALUE="600"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" VALUE="533.333"/>
+        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ" VALUE="-1"/>
+        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ" VALUE="1000"/>
+        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ" VALUE="400"/>
+        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ" VALUE="1500"/>
+        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" VALUE="20"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC0__FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC1__FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC2__FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__TTC3__FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__IOU_SLCR__WDT0__FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__FPD_SLCR__WDT1__FREQMHZ" VALUE="99.999001"/>
+        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU__FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__RESPONSE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__GEN_IPI_0__MASTER" VALUE="APU"/>
+        <PARAMETER NAME="PSU__GEN_IPI_1__MASTER" VALUE="RPU0"/>
+        <PARAMETER NAME="PSU__GEN_IPI_2__MASTER" VALUE="RPU1"/>
+        <PARAMETER NAME="PSU__GEN_IPI_3__MASTER" VALUE="PMU"/>
+        <PARAMETER NAME="PSU__GEN_IPI_4__MASTER" VALUE="PMU"/>
+        <PARAMETER NAME="PSU__GEN_IPI_5__MASTER" VALUE="PMU"/>
+        <PARAMETER NAME="PSU__GEN_IPI_6__MASTER" VALUE="PMU"/>
+        <PARAMETER NAME="PSU__GEN_IPI_7__MASTER" VALUE="NONE"/>
+        <PARAMETER NAME="PSU__GEN_IPI_8__MASTER" VALUE="NONE"/>
+        <PARAMETER NAME="PSU__GEN_IPI_9__MASTER" VALUE="NONE"/>
+        <PARAMETER NAME="PSU__GEN_IPI_10__MASTER" VALUE="NONE"/>
+        <PARAMETER NAME="PSU__GEN_IPI__TRUSTZONE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_RPU_PERMON__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_OCM_ERR__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_LPD_APB__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_NAND__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_QSPI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_GPIO__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_I2C0__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_I2C1__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_SPI0__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_SPI1__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_UART0__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_UART1__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_CAN0__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_CAN1__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_LPD_APM__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_RTC_ALARM__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_RTC_SECONDS__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_CLKMON__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_PL_IPI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_RPU_IPI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_IPI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT0" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT1" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT2" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT0" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT1" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT2" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT0" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT1" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT2" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT0" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT1" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT2" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_SDIO0__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_SDIO1__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_SDIO0_WAKE__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_SDIO1_WAKE__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_LP_WDT__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_CSUPMU_WDT__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ATB_LPD__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_AIB_AXI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_AMS__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT0__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT0_WAKEUP__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT1__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT1_WAKEUP__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT2__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT2_WAKEUP__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT3__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ENT3_WAKEUP__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_USB3_ENDPOINT__INT0" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_USB3_OTG__INT0" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_USB3_ENDPOINT__INT1" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_USB3_OTG__INT1" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_ADMA_CHAN__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_CSU__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_CSU_DMA__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_EFUSE__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_XMPU_LPD__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_DDR_SS__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_FP_WDT__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_MSI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_LEGACY__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_DMA__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_MSC__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_DPORT__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_FPD_APB__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_FPD_ATB_ERR__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_DPDMA__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APM_FPD__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_GDMA_CHAN__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_GPU__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_SATA__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_XMPU_FPD__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_CPUMNT__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_CTI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_PMU__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_COMM__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_L2ERR__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_EXTERR__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F_APU_REGS__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F__INTF_PPD_CCI__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__IRQ_P2F__INTF_FPD_SMMU__INT" VALUE="0"/>
+        <PARAMETER NAME="PSU__NUM_F2P0__INTR__INPUTS" VALUE="2"/>
+        <PARAMETER NAME="PSU__NUM_F2P1__INTR__INPUTS" VALUE="1"/>
+        <PARAMETER NAME="PSU__NUM_FABRIC_RESETS" VALUE="1"/>
+        <PARAMETER NAME="PSU__GPIO_EMIO_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="PSU__HPM0_FPD__NUM_WRITE_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PSU__HPM0_FPD__NUM_READ_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PSU__HPM1_FPD__NUM_WRITE_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PSU__HPM1_FPD__NUM_READ_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PSU__HPM0_LPD__NUM_WRITE_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PSU__HPM0_LPD__NUM_READ_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PSU__TRISTATE__INVERTED" VALUE="1"/>
+        <PARAMETER NAME="PSU__GPIO_EMIO__WIDTH" VALUE="[94:0]"/>
+        <PARAMETER NAME="PSU__REPORT__DBGLOG" VALUE="0"/>
+        <PARAMETER NAME="IIC0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="IIC1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="QSPI_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="NAND_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="SD0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="SD1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="CAN0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="CAN1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="PJTAG_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="PMU_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="CSU_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="SPI0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="SPI1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="UART0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="UART1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="GPIO_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="SWDT0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="SWDT1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="TRACE_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="TTC0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="TTC1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="TTC2_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="TTC3_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="GEM0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="GEM1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="GEM2_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="GEM3_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="USB0_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="USB1_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="PCIE_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="DP_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="SATA_BOARD_INTERFACE" VALUE="custom"/>
+        <PARAMETER NAME="preset" VALUE="None"/>
+        <PARAMETER NAME="PSU__SD0_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD1_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__QSPI_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM0_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM1_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM2_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM3_ROUTE_THROUGH_FPD" VALUE="0"/>
+        <PARAMETER NAME="PSU__RPU_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__PMU_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__CSU_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB0_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__USB1_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA0_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA1_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA2_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA3_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA4_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA5_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA6_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__LPDMA7_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD0_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__SD1_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__NAND_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__QSPI_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET0__TSU__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET1__TSU__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET2__TSU__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENET3__TSU__ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PSU__TSU__BUFG_PORT_PAIR" VALUE="0"/>
+        <PARAMETER NAME="PSU__TSU__BUFG_PORT_LOOPBACK" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM0_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM1_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM2_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__GEM3_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__AFI0_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__AFI1_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__FPDMASTERS_COHERENCY" VALUE="0"/>
+        <PARAMETER NAME="PSU__ENABLE__DDR__REFRESH__SIGNALS" VALUE="0"/>
+        <PARAMETER NAME="PSU__M_AXI_GP0__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU__M_AXI_GP1__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU__M_AXI_GP2__FREQMHZ" VALUE="124.998749"/>
+        <PARAMETER NAME="PSU__S_AXI_GP0__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU__S_AXI_GP1__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU__S_AXI_GP2__FREQMHZ" VALUE="124.998749"/>
+        <PARAMETER NAME="PSU__S_AXI_GP3__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU__S_AXI_GP4__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU__S_AXI_GP5__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU__S_AXI_GP6__FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PSU_SD1_INTERNAL_BUS_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="Component_Name" VALUE="pl_eth_10g_zynq_ultra_ps_e_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0xFF000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0xFFFFFFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="124998749" DIR="I" NAME="maxihpm0_lpd_aclk" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="maxigp2_awid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="39" NAME="maxigp2_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="maxigp2_awlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="maxigp2_awsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="maxigp2_awburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_awlock" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="maxigp2_awcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="maxigp2_awprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_awvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="maxigp2_awuser" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awuser">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awuser"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="maxigp2_awready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="127" NAME="maxigp2_wdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="maxigp2_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_wlast" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_wvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="maxigp2_wready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="maxigp2_bid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="maxigp2_bresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="maxigp2_bvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_bready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="maxigp2_arid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="39" NAME="maxigp2_araddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="maxigp2_arlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="maxigp2_arsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="maxigp2_arburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_arlock" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="maxigp2_arcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="maxigp2_arprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_arvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="15" NAME="maxigp2_aruser" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_aruser">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_aruser"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="maxigp2_arready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="maxigp2_rid" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="127" NAME="maxigp2_rdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="maxigp2_rresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="maxigp2_rlast" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="maxigp2_rvalid" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="maxigp2_rready" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="maxigp2_awqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="maxigp2_arqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_ps_axi_periph_S00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="124998749" DIR="I" NAME="saxihp0_fpd_aclk" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="pl_clk0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_aruser" SIGIS="undef"/>
+        <PORT DIR="I" NAME="saxigp2_awuser" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="5" NAME="saxigp2_awid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="48" NAME="saxigp2_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="saxigp2_awlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="saxigp2_awsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="saxigp2_awburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_awlock" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="saxigp2_awcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="saxigp2_awprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_awvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="saxigp2_awready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="127" NAME="saxigp2_wdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="15" NAME="saxigp2_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_wlast" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_wvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="saxigp2_wready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="5" NAME="saxigp2_bid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="saxigp2_bresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="saxigp2_bvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_bready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="5" NAME="saxigp2_arid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="48" NAME="saxigp2_araddr" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="saxigp2_arlen" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="saxigp2_arsize" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="saxigp2_arburst" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_arlock" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="saxigp2_arcache" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="saxigp2_arprot" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_arvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="saxigp2_arready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="5" NAME="saxigp2_rid" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="127" NAME="saxigp2_rdata" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="saxigp2_rresp" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="saxigp2_rlast" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="saxigp2_rvalid" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="saxigp2_rready" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="saxigp2_awqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="saxigp2_arqos" RIGHT="0" SIGIS="undef" SIGNAME="zups_axi_pl_ps_M00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="pl_ps_irq0" RIGHT="0" SENSITIVITY="LEVEL_HIGH:LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="zups_xlconcat_0_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_xlconcat_0" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="pl_resetn0" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zups_zynq_ultra_ps_e_0_pl_resetn0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="ext_reset_in"/>
+            <CONNECTION INSTANCE="zups_util_vector_logic_0" PORT="Op1"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="124998749" DIR="O" NAME="pl_clk0" SIGIS="clk" SIGNAME="zups_zynq_ultra_ps_e_0_pl_clk0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_aclk"/>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_aclk"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="dclk"/>
+            <CONNECTION INSTANCE="xxv_ethernet_0" PORT="s_axi_aclk_0"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="ACLK"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="M00_ACLK"/>
+            <CONNECTION INSTANCE="zups_axi_pl_ps" PORT="S00_ACLK"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="ACLK"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M00_ACLK"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M01_ACLK"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="M02_ACLK"/>
+            <CONNECTION INSTANCE="zups_ps_axi_periph" PORT="S00_ACLK"/>
+            <CONNECTION INSTANCE="zups_rst_ps8_0_99M" PORT="slowest_sync_clk"/>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="maxihpm0_lpd_aclk"/>
+            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxihp0_fpd_aclk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="99999001" DIR="O" NAME="pl_clk1" SIGIS="clk"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="zups_zynq_ultra_ps_e_0_M_AXI_HPM0_LPD" DATAWIDTH="128" NAME="M_AXI_HPM0_LPD" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="124998749"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="16"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="16"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="16"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="maxigp2_awid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="maxigp2_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="maxigp2_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="maxigp2_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="maxigp2_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="maxigp2_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="maxigp2_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="maxigp2_awprot"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="maxigp2_awvalid"/>
+            <PORTMAP LOGICAL="AWUSER" PHYSICAL="maxigp2_awuser"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="maxigp2_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="maxigp2_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="maxigp2_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="maxigp2_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="maxigp2_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="maxigp2_wready"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="maxigp2_bid"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="maxigp2_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="maxigp2_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="maxigp2_bready"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="maxigp2_arid"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="maxigp2_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="maxigp2_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="maxigp2_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="maxigp2_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="maxigp2_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="maxigp2_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="maxigp2_arprot"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="maxigp2_arvalid"/>
+            <PORTMAP LOGICAL="ARUSER" PHYSICAL="maxigp2_aruser"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="maxigp2_arready"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="maxigp2_rid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="maxigp2_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="maxigp2_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="maxigp2_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="maxigp2_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="maxigp2_rready"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="maxigp2_awqos"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="maxigp2_arqos"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="zups_axi_pl_ps_M00_AXI" DATAWIDTH="128" NAME="S_AXI_HP0_FPD" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="124998749"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="49"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="32"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARUSER" PHYSICAL="saxigp2_aruser"/>
+            <PORTMAP LOGICAL="AWUSER" PHYSICAL="saxigp2_awuser"/>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="saxigp2_awid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="saxigp2_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="saxigp2_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="saxigp2_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="saxigp2_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="saxigp2_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="saxigp2_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="saxigp2_awprot"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="saxigp2_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="saxigp2_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="saxigp2_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="saxigp2_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="saxigp2_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="saxigp2_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="saxigp2_wready"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="saxigp2_bid"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="saxigp2_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="saxigp2_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="saxigp2_bready"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="saxigp2_arid"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="saxigp2_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="saxigp2_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="saxigp2_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="saxigp2_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="saxigp2_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="saxigp2_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="saxigp2_arprot"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="saxigp2_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="saxigp2_arready"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="saxigp2_rid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="saxigp2_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="saxigp2_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="saxigp2_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="saxigp2_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="saxigp2_rready"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="saxigp2_awqos"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="saxigp2_arqos"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8000FFFF" INSTANCE="axi_dma_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_LPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x80010000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8001FFFF" INSTANCE="xxv_ethernet_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_LPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi_0"/>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="axi_dma_0"/>
+        <PERIPHERAL INSTANCE="xxv_ethernet_0"/>
+      </PERIPHERALS>
+    </MODULE>
+  </MODULES>
+
+</EDKSYSTEM>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl
new file mode 100644
index 0000000..e5350bd
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl
@@ -0,0 +1,2060 @@
+
+################################################################
+# This is a generated script based on design: pl_eth_10g
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source pl_eth_10g_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu7ev-ffvc1156-2-e
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name pl_eth_10g
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+  # Add USER_COMMENTS on $design_name
+  set_property USER_COMMENTS.comment_0 "PL ETHERNET 10G" [get_bd_designs $design_name]
+  set_property USER_COMMENTS.comment_1 "PL ETHERNET 10G" [get_bd_designs $design_name]
+  set_property USER_COMMENTS.comment_2 "PL ETHERNET 10G" [get_bd_designs $design_name]
+  set_property USER_COMMENTS.comment_3 "PL ETHERNET 10G" [get_bd_designs $design_name]
+  set_property USER_COMMENTS.comment_4 "PL ETHERNET 10G" [get_bd_designs $design_name]
+  set_property USER_COMMENTS.comment_5 "PL ETHERNET 10G" [get_bd_designs $design_name]
+  set_property USER_COMMENTS.comment_6 "PL ETHERNET 10G" [get_bd_designs $design_name]
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: zups
+proc create_hier_cell_zups { parentCell nameHier } {
+
+  variable script_folder
+
+  if { $parentCell eq "" || $nameHier eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_zups() - Empty argument(s)!"}
+     return
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+  # Create cell and set as current instance
+  set hier_obj [create_bd_cell -type hier $nameHier]
+  current_bd_instance $hier_obj
+
+  # Create interface pins
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI
+
+  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
+
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXI
+
+  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXI
+
+
+  # Create pins
+  create_bd_pin -dir I -from 0 -to 0 In0
+  create_bd_pin -dir I -from 0 -to 0 In1
+  create_bd_pin -dir O -from 0 -to 0 Res
+  create_bd_pin -dir I -type clk S01_ACLK
+  create_bd_pin -dir I -type rst S01_ARESETN
+  create_bd_pin -dir I -type clk S02_ACLK
+  create_bd_pin -dir I -type rst S02_ARESETN
+  create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn
+  create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_reset
+  create_bd_pin -dir O -type clk pl_clk0
+
+  # Create instance: axi_pl_ps, and set properties
+  set axi_pl_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_pl_ps ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {1} \
+   CONFIG.NUM_SI {3} \
+   CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $axi_pl_ps
+
+  # Create instance: ps_axi_periph, and set properties
+  set ps_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {3} \
+   CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $ps_axi_periph
+
+  # Create instance: rst_ps8_0_99M, and set properties
+  set rst_ps8_0_99M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_99M ]
+
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: xlconcat_0, and set properties
+  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.CAN0_BOARD_INTERFACE {custom} \
+   CONFIG.CAN1_BOARD_INTERFACE {custom} \
+   CONFIG.CSU_BOARD_INTERFACE {custom} \
+   CONFIG.DP_BOARD_INTERFACE {custom} \
+   CONFIG.GEM0_BOARD_INTERFACE {custom} \
+   CONFIG.GEM1_BOARD_INTERFACE {custom} \
+   CONFIG.GEM2_BOARD_INTERFACE {custom} \
+   CONFIG.GEM3_BOARD_INTERFACE {custom} \
+   CONFIG.GPIO_BOARD_INTERFACE {custom} \
+   CONFIG.IIC0_BOARD_INTERFACE {custom} \
+   CONFIG.IIC1_BOARD_INTERFACE {custom} \
+   CONFIG.NAND_BOARD_INTERFACE {custom} \
+   CONFIG.PCIE_BOARD_INTERFACE {custom} \
+   CONFIG.PJTAG_BOARD_INTERFACE {custom} \
+   CONFIG.PMU_BOARD_INTERFACE {custom} \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_IMPORT_BOARD_PRESET {} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_0_SLEW {slow} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_10_SLEW {slow} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_11_SLEW {slow} \
+   CONFIG.PSU_MIO_12_DIRECTION {out} \
+   CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_12_SLEW {slow} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_13_SLEW {slow} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_14_SLEW {slow} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_15_SLEW {slow} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_16_SLEW {slow} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_17_SLEW {slow} \
+   CONFIG.PSU_MIO_18_DIRECTION {in} \
+   CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_18_SLEW {fast} \
+   CONFIG.PSU_MIO_19_DIRECTION {out} \
+   CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_19_SLEW {slow} \
+   CONFIG.PSU_MIO_1_DIRECTION {inout} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_1_SLEW {slow} \
+   CONFIG.PSU_MIO_20_DIRECTION {out} \
+   CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_20_SLEW {slow} \
+   CONFIG.PSU_MIO_21_DIRECTION {in} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_21_SLEW {fast} \
+   CONFIG.PSU_MIO_22_DIRECTION {inout} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_22_SLEW {slow} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_23_SLEW {slow} \
+   CONFIG.PSU_MIO_24_DIRECTION {out} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_24_SLEW {slow} \
+   CONFIG.PSU_MIO_25_DIRECTION {in} \
+   CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_25_SLEW {fast} \
+   CONFIG.PSU_MIO_26_DIRECTION {inout} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_26_SLEW {slow} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_27_SLEW {slow} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_29_SLEW {slow} \
+   CONFIG.PSU_MIO_2_DIRECTION {inout} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_2_SLEW {slow} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {out} \
+   CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_31_SLEW {slow} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_32_SLEW {slow} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_33_SLEW {slow} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_34_SLEW {slow} \
+   CONFIG.PSU_MIO_35_DIRECTION {out} \
+   CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_35_SLEW {slow} \
+   CONFIG.PSU_MIO_36_DIRECTION {out} \
+   CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_36_SLEW {slow} \
+   CONFIG.PSU_MIO_37_DIRECTION {out} \
+   CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_37_SLEW {slow} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_38_SLEW {slow} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_39_SLEW {slow} \
+   CONFIG.PSU_MIO_3_DIRECTION {inout} \
+   CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_3_SLEW {slow} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_40_SLEW {slow} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_41_SLEW {slow} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_42_SLEW {slow} \
+   CONFIG.PSU_MIO_43_DIRECTION {out} \
+   CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_43_SLEW {slow} \
+   CONFIG.PSU_MIO_44_DIRECTION {in} \
+   CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_44_SLEW {fast} \
+   CONFIG.PSU_MIO_45_DIRECTION {in} \
+   CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_45_SLEW {fast} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_46_SLEW {slow} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_47_SLEW {slow} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_48_SLEW {slow} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_49_SLEW {slow} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_4_SLEW {slow} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_50_SLEW {slow} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_51_SLEW {slow} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_54_SLEW {slow} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_56_SLEW {slow} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_57_SLEW {slow} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_58_SLEW {slow} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_59_SLEW {slow} \
+   CONFIG.PSU_MIO_5_DIRECTION {out} \
+   CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_5_SLEW {slow} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_60_SLEW {slow} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_61_SLEW {slow} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_62_SLEW {slow} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_63_SLEW {slow} \
+   CONFIG.PSU_MIO_64_DIRECTION {out} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_64_SLEW {slow} \
+   CONFIG.PSU_MIO_65_DIRECTION {out} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_65_SLEW {slow} \
+   CONFIG.PSU_MIO_66_DIRECTION {out} \
+   CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_66_SLEW {slow} \
+   CONFIG.PSU_MIO_67_DIRECTION {out} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_67_SLEW {slow} \
+   CONFIG.PSU_MIO_68_DIRECTION {out} \
+   CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_68_SLEW {slow} \
+   CONFIG.PSU_MIO_69_DIRECTION {out} \
+   CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_69_SLEW {slow} \
+   CONFIG.PSU_MIO_6_DIRECTION {out} \
+   CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_6_SLEW {slow} \
+   CONFIG.PSU_MIO_70_DIRECTION {in} \
+   CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_70_SLEW {fast} \
+   CONFIG.PSU_MIO_71_DIRECTION {in} \
+   CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_71_SLEW {fast} \
+   CONFIG.PSU_MIO_72_DIRECTION {in} \
+   CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_72_SLEW {fast} \
+   CONFIG.PSU_MIO_73_DIRECTION {in} \
+   CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_73_SLEW {fast} \
+   CONFIG.PSU_MIO_74_DIRECTION {in} \
+   CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_74_SLEW {fast} \
+   CONFIG.PSU_MIO_75_DIRECTION {in} \
+   CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_75_SLEW {fast} \
+   CONFIG.PSU_MIO_76_DIRECTION {out} \
+   CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_76_SLEW {slow} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_77_SLEW {slow} \
+   CONFIG.PSU_MIO_7_DIRECTION {out} \
+   CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_7_SLEW {slow} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_8_SLEW {slow} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+   CONFIG.PSU_MIO_9_SLEW {slow} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS { \
+     0#I2C 1#I2C \
+     0#UART 1#UART \
+     0#USB 0#Gem \
+     0#USB 0#Gem \
+     0#USB 0#Gem \
+     0#USB 0#Gem \
+     0#USB 0#Gem \
+     0#USB 0#Gem \
+     1#GPIO0 MIO#GPIO0 \
+     1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU \
+     1#SD 1#USB \
+     1#SD 1#USB \
+     1#SD 1#USB \
+     1#SD 1#USB \
+     1#SD 1#USB \
+     1#SD 1#USB \
+     1#UART 0#UART \
+     3#Gem 3#MDIO \
+     3#Gem 3#MDIO \
+     3#Gem 3#MDIO \
+     3#Gem 3#MDIO \
+     3#Gem 3#MDIO \
+     3#Gem 3#MDIO \
+     3#MDIO 3 \
+     Flash#Feedback Clk#Quad \
+     Flash#Quad SPI \
+     Flash#Quad SPI \
+     Flash#Quad SPI \
+     Flash#Quad SPI \
+     Flash#Quad SPI \
+     GPO 5#GPIO1 \
+     GPO 5#GPIO1 \
+     GPO 5#GPIO1 \
+     GPO 5#GPIO1 \
+     GPO 5#GPIO1 \
+     GPO 5#GPIO1 \
+     MIO#CAN 1#CAN \
+     MIO#I2C 0#I2C \
+     MIO#SD 1#SD \
+     Quad SPI \
+     SPI Flash#GPIO0 \
+     SPI Flash#GPIO0 \
+     SPI Flash#GPIO0 \
+     SPI Flash#GPIO0 \
+     SPI Flash#GPIO0 \
+     SPI Flash#GPIO0 \
+   } \
+   CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
+   CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \
+   CONFIG.PSU_SMC_CYCLE_T0 {NA} \
+   CONFIG.PSU_SMC_CYCLE_T1 {NA} \
+   CONFIG.PSU_SMC_CYCLE_T2 {NA} \
+   CONFIG.PSU_SMC_CYCLE_T3 {NA} \
+   CONFIG.PSU_SMC_CYCLE_T4 {NA} \
+   CONFIG.PSU_SMC_CYCLE_T5 {NA} \
+   CONFIG.PSU_SMC_CYCLE_T6 {NA} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU_VALUE_SILVERSION {3} \
+   CONFIG.PSU__ACPU0__POWER__ON {1} \
+   CONFIG.PSU__ACPU1__POWER__ON {1} \
+   CONFIG.PSU__ACPU2__POWER__ON {1} \
+   CONFIG.PSU__ACPU3__POWER__ON {1} \
+   CONFIG.PSU__ACTUAL__IP {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \
+   CONFIG.PSU__AFI0_COHERENCY {0} \
+   CONFIG.PSU__AFI1_COHERENCY {0} \
+   CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+   CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+   CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
+   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+   CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {20} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.315527} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {19} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
+   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
+   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
+   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
+   CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {124.998749} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {90} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__CSU_COHERENCY {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+   CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
+   CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+   CONFIG.PSU__DDRC__CL {15} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \
+   CONFIG.PSU__DDRC__CWL {14} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+   CONFIG.PSU__DDRC__ENABLE {1} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+   CONFIG.PSU__DDRC__FGRM {1X} \
+   CONFIG.PSU__DDRC__FREQ_MHZ {1066.50} \
+   CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+   CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+   CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {30.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+   CONFIG.PSU__DDRC__T_RC {47.06} \
+   CONFIG.PSU__DDRC__T_RCD {15} \
+   CONFIG.PSU__DDRC__T_RP {15} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+   CONFIG.PSU__DDRC__VREF {1} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
+   CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+   CONFIG.PSU__DEVICE_TYPE {EV} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Single Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+   CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
+   CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET0__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET0__TSU__ENABLE {0} \
+   CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET1__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET1__TSU__ENABLE {0} \
+   CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET2__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET2__TSU__ENABLE {0} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+   CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
+   CONFIG.PSU__EN_EMIO_TRACE {0} \
+   CONFIG.PSU__EP__IP {0} \
+   CONFIG.PSU__EXPAND__CORESIGHT {0} \
+   CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
+   CONFIG.PSU__EXPAND__GIC {0} \
+   CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
+   CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
+   CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__FP__POWER__ON {1} \
+   CONFIG.PSU__FTM__CTI_IN_0 {0} \
+   CONFIG.PSU__FTM__CTI_IN_1 {0} \
+   CONFIG.PSU__FTM__CTI_IN_2 {0} \
+   CONFIG.PSU__FTM__CTI_IN_3 {0} \
+   CONFIG.PSU__FTM__CTI_OUT_0 {0} \
+   CONFIG.PSU__FTM__CTI_OUT_1 {0} \
+   CONFIG.PSU__FTM__CTI_OUT_2 {0} \
+   CONFIG.PSU__FTM__CTI_OUT_3 {0} \
+   CONFIG.PSU__FTM__GPI {0} \
+   CONFIG.PSU__FTM__GPO {0} \
+   CONFIG.PSU__GEM0_COHERENCY {0} \
+   CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM1_COHERENCY {0} \
+   CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM2_COHERENCY {0} \
+   CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+   CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
+   CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
+   CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
+   CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+   CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+   CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+   CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+   CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
+   CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
+   CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
+   CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {<Select>} \
+   CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+   CONFIG.PSU__GPU_PP0__POWER__ON {1} \
+   CONFIG.PSU__GPU_PP1__POWER__ON {1} \
+   CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \
+   CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
+   CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
+   CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
+   CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
+   CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
+   CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
+   CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+   CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
+   CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
+   CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
+   CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
+   CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
+   CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \
+   CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
+   CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
+   CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
+   CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \
+   CONFIG.PSU__IRQ_P2F_CSU__INT {0} \
+   CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
+   CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
+   CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
+   CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
+   CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
+   CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
+   CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
+   CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
+   CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
+   CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
+   CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
+   CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
+   CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
+   CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
+   CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
+   CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
+   CONFIG.PSU__IRQ_P2F_NAND__INT {0} \
+   CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
+   CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
+   CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
+   CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
+   CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
+   CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
+   CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
+   CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
+   CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
+   CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
+   CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
+   CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
+   CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
+   CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
+   CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \
+   CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \
+   CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
+   CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
+   CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
+   CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
+   CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
+   CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
+   CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
+   CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
+   CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
+   CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
+   CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
+   CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
+   CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
+   CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
+   CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
+   CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
+   CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
+   CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+   CONFIG.PSU__LPDMA0_COHERENCY {0} \
+   CONFIG.PSU__LPDMA1_COHERENCY {0} \
+   CONFIG.PSU__LPDMA2_COHERENCY {0} \
+   CONFIG.PSU__LPDMA3_COHERENCY {0} \
+   CONFIG.PSU__LPDMA4_COHERENCY {0} \
+   CONFIG.PSU__LPDMA5_COHERENCY {0} \
+   CONFIG.PSU__LPDMA6_COHERENCY {0} \
+   CONFIG.PSU__LPDMA7_COHERENCY {0} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {128} \
+   CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
+   CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
+   CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
+   CONFIG.PSU__NAND_COHERENCY {0} \
+   CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
+   CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
+   CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
+   CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
+   CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+   CONFIG.PSU__NUM_FABRIC_RESETS {1} \
+   CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+   CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+   CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+   CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+   CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+   CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
+   CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
+   CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+   CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
+   CONFIG.PSU__PCIE__BAR0_64BIT {0} \
+   CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
+   CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
+   CONFIG.PSU__PCIE__BAR0_VAL {0x0} \
+   CONFIG.PSU__PCIE__BAR1_64BIT {0} \
+   CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
+   CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
+   CONFIG.PSU__PCIE__BAR1_VAL {0x0} \
+   CONFIG.PSU__PCIE__BAR2_64BIT {0} \
+   CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
+   CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
+   CONFIG.PSU__PCIE__BAR2_VAL {0x0} \
+   CONFIG.PSU__PCIE__BAR3_64BIT {0} \
+   CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
+   CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
+   CONFIG.PSU__PCIE__BAR3_VAL {0x0} \
+   CONFIG.PSU__PCIE__BAR4_64BIT {0} \
+   CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
+   CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
+   CONFIG.PSU__PCIE__BAR4_VAL {0x0} \
+   CONFIG.PSU__PCIE__BAR5_64BIT {0} \
+   CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
+   CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
+   CONFIG.PSU__PCIE__BAR5_VAL {0x0} \
+   CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
+   CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
+   CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x80} \
+   CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x68000} \
+   CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
+   CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
+   CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
+   CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
+   CONFIG.PSU__PCIE__DEVICE_ID {0xD011} \
+   CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
+   CONFIG.PSU__PCIE__ECRC_CHECK {0} \
+   CONFIG.PSU__PCIE__ECRC_ERR {0} \
+   CONFIG.PSU__PCIE__ECRC_GEN {0} \
+   CONFIG.PSU__PCIE__EROM_ENABLE {0} \
+   CONFIG.PSU__PCIE__EROM_VAL {0x0} \
+   CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
+   CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
+   CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
+   CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+   CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
+   CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
+   CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
+   CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
+   CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
+   CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
+   CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
+   CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \
+   CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
+   CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
+   CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+   CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
+   CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
+   CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
+   CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
+   CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
+   CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+   CONFIG.PSU__PCIE__MULTIHEADER {0} \
+   CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \
+   CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \
+   CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
+   CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
+   CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
+   CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
+   CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \
+   CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__PCIE__REVISION_ID {0x0} \
+   CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
+   CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
+   CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
+   CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
+   CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
+   CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
+   CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PL__POWER__ON {1} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__IO {<Select>} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI1__IO {<Select>} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__IO {<Select>} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__IO {<Select>} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__IO {<Select>} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__IO {<Select>} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {low} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO3__IO {MIO 35} \
+   CONFIG.PSU__PMU__GPO3__POLARITY {low} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO4__IO {MIO 36} \
+   CONFIG.PSU__PMU__GPO4__POLARITY {low} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO5__IO {MIO 37} \
+   CONFIG.PSU__PMU__GPO5__POLARITY {low} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {0} \
+   CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
+   CONFIG.PSU__PROTECTION__DEBUG {0} \
+   CONFIG.PSU__PROTECTION__ENABLE {0} \
+   CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
+   CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
+   CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \
+   CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
+   CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
+   CONFIG.PSU__PROTECTION__SLAVES { \
+     LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \
+   } \
+   CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \
+   CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
+   CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+   CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
+   CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
+   CONFIG.PSU__REPORT__DBGLOG {0} \
+   CONFIG.PSU__RPU_COHERENCY {0} \
+   CONFIG.PSU__RPU__POWER__ON {1} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+   CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+   CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
+   CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
+   CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {1} \
+   CONFIG.PSU__SD1__GRP_POW__IO {MIO 43} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
+   CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \
+   CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__IO {EMIO} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__IO {EMIO} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TCM0A__POWER__ON {1} \
+   CONFIG.PSU__TCM0B__POWER__ON {1} \
+   CONFIG.PSU__TCM1A__POWER__ON {1} \
+   CONFIG.PSU__TCM1B__POWER__ON {1} \
+   CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \
+   CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
+   CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__TRISTATE__INVERTED {1} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__PERIPHERAL__IO {EMIO} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__PERIPHERAL__IO {EMIO} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__PERIPHERAL__IO {EMIO} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__PERIPHERAL__IO {EMIO} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \
+   CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \
+   CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
+   CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
+   CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
+   CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \
+   CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \
+   CONFIG.PSU__USE__ADMA {0} \
+   CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
+   CONFIG.PSU__USE__AUDIO {0} \
+   CONFIG.PSU__USE__CLK {0} \
+   CONFIG.PSU__USE__CLK0 {0} \
+   CONFIG.PSU__USE__CLK1 {0} \
+   CONFIG.PSU__USE__CLK2 {0} \
+   CONFIG.PSU__USE__CLK3 {0} \
+   CONFIG.PSU__USE__CROSS_TRIGGER {0} \
+   CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
+   CONFIG.PSU__USE__DEBUG__TEST {0} \
+   CONFIG.PSU__USE__EVENT_RPU {0} \
+   CONFIG.PSU__USE__FABRIC__RST {1} \
+   CONFIG.PSU__USE__FTM {0} \
+   CONFIG.PSU__USE__GDMA {0} \
+   CONFIG.PSU__USE__IRQ {0} \
+   CONFIG.PSU__USE__IRQ0 {1} \
+   CONFIG.PSU__USE__IRQ1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {1} \
+   CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
+   CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
+   CONFIG.PSU__USE__RST0 {0} \
+   CONFIG.PSU__USE__RST1 {0} \
+   CONFIG.PSU__USE__RST2 {0} \
+   CONFIG.PSU__USE__RST3 {0} \
+   CONFIG.PSU__USE__RTC {0} \
+   CONFIG.PSU__USE__STM {0} \
+   CONFIG.PSU__USE__S_AXI_ACE {0} \
+   CONFIG.PSU__USE__S_AXI_ACP {0} \
+   CONFIG.PSU__USE__S_AXI_GP0 {0} \
+   CONFIG.PSU__USE__S_AXI_GP1 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {0} \
+   CONFIG.PSU__USE__S_AXI_GP4 {0} \
+   CONFIG.PSU__USE__S_AXI_GP5 {0} \
+   CONFIG.PSU__USE__S_AXI_GP6 {0} \
+   CONFIG.PSU__USE__USB3_0_HUB {0} \
+   CONFIG.PSU__USE__USB3_1_HUB {0} \
+   CONFIG.PSU__USE__VIDEO {0} \
+   CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
+   CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
+   CONFIG.QSPI_BOARD_INTERFACE {custom} \
+   CONFIG.SATA_BOARD_INTERFACE {custom} \
+   CONFIG.SD0_BOARD_INTERFACE {custom} \
+   CONFIG.SD1_BOARD_INTERFACE {custom} \
+   CONFIG.SPI0_BOARD_INTERFACE {custom} \
+   CONFIG.SPI1_BOARD_INTERFACE {custom} \
+   CONFIG.SUBPRESET1 {Custom} \
+   CONFIG.SUBPRESET2 {Custom} \
+   CONFIG.SWDT0_BOARD_INTERFACE {custom} \
+   CONFIG.SWDT1_BOARD_INTERFACE {custom} \
+   CONFIG.TRACE_BOARD_INTERFACE {custom} \
+   CONFIG.TTC0_BOARD_INTERFACE {custom} \
+   CONFIG.TTC1_BOARD_INTERFACE {custom} \
+   CONFIG.TTC2_BOARD_INTERFACE {custom} \
+   CONFIG.TTC3_BOARD_INTERFACE {custom} \
+   CONFIG.UART0_BOARD_INTERFACE {custom} \
+   CONFIG.UART1_BOARD_INTERFACE {custom} \
+   CONFIG.USB0_BOARD_INTERFACE {custom} \
+   CONFIG.USB1_BOARD_INTERFACE {custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S00_AXI] [get_bd_intf_pins axi_pl_ps/S00_AXI]
+  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S02_AXI] [get_bd_intf_pins axi_pl_ps/S02_AXI]
+  connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins S01_AXI] [get_bd_intf_pins axi_pl_ps/S01_AXI]
+  connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins M00_AXI] [get_bd_intf_pins ps_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins M01_AXI] [get_bd_intf_pins ps_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins ps_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+  connect_bd_intf_net -intf_net axi_pl_ps_M00_AXI [get_bd_intf_pins axi_pl_ps/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+
+  # Create port connections
+  connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins xlconcat_0/In0]
+  connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins xlconcat_0/In1]
+  connect_bd_net -net S01_ACLK_1 [get_bd_pins S01_ACLK] [get_bd_pins axi_pl_ps/S01_ACLK]
+  connect_bd_net -net S01_ARESETN_1 [get_bd_pins S01_ARESETN] [get_bd_pins axi_pl_ps/S01_ARESETN]
+  connect_bd_net -net S02_ACLK_1 [get_bd_pins S02_ACLK] [get_bd_pins axi_pl_ps/S02_ACLK]
+  connect_bd_net -net S02_ARESETN_1 [get_bd_pins S02_ARESETN] [get_bd_pins axi_pl_ps/S02_ARESETN]
+  connect_bd_net -net rst_ps8_0_99M_interconnect_aresetn [get_bd_pins axi_pl_ps/ARESETN] [get_bd_pins ps_axi_periph/ARESETN] [get_bd_pins rst_ps8_0_99M/interconnect_aresetn]
+  connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins axi_pl_ps/M00_ARESETN] [get_bd_pins axi_pl_ps/S00_ARESETN] [get_bd_pins ps_axi_periph/M00_ARESETN] [get_bd_pins ps_axi_periph/M01_ARESETN] [get_bd_pins ps_axi_periph/M02_ARESETN] [get_bd_pins ps_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_99M/peripheral_aresetn]
+  connect_bd_net -net rst_ps8_0_99M_peripheral_reset [get_bd_pins peripheral_reset] [get_bd_pins rst_ps8_0_99M/peripheral_reset]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins Res] [get_bd_pins util_vector_logic_0/Res]
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins pl_clk0] [get_bd_pins axi_pl_ps/ACLK] [get_bd_pins axi_pl_ps/M00_ACLK] [get_bd_pins axi_pl_ps/S00_ACLK] [get_bd_pins ps_axi_periph/ACLK] [get_bd_pins ps_axi_periph/M00_ACLK] [get_bd_pins ps_axi_periph/M01_ACLK] [get_bd_pins ps_axi_periph/M02_ACLK] [get_bd_pins ps_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_99M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_99M/ext_reset_in] [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set gt_ref_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt_ref_clk ]
+  set_property -dict [ list \
+   CONFIG.FREQ_HZ {156250000} \
+   ] $gt_ref_clk
+
+  set gt_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_xxv_ethernet:gt_ports:2.0 gt_rx ]
+
+  set gt_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_xxv_ethernet:gt_ports:2.0 gt_tx ]
+
+
+  # Create ports
+  set sfp_tx_dis [ create_bd_port -dir O -from 0 -to 0 sfp_tx_dis ]
+
+  # Create instance: axi_dma_0, and set properties
+  set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
+  set_property -dict [ list \
+   CONFIG.c_include_mm2s_dre {1} \
+   CONFIG.c_include_s2mm_dre {1} \
+   CONFIG.c_m_axi_mm2s_data_width {64} \
+   CONFIG.c_m_axis_mm2s_tdata_width {64} \
+   CONFIG.c_mm2s_burst_size {64} \
+   CONFIG.c_s2mm_burst_size {8} \
+   CONFIG.c_sg_include_stscntrl_strm {0} \
+   CONFIG.c_sg_length_width {16} \
+ ] $axi_dma_0
+
+  # Create instance: dma_rx_rst, and set properties
+  set dma_rx_rst [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 dma_rx_rst ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $dma_rx_rst
+
+  # Create instance: dma_tx_rst, and set properties
+  set dma_tx_rst [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 dma_tx_rst ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $dma_tx_rst
+
+  # Create instance: rx_data_fifo, and set properties
+  set rx_data_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 rx_data_fifo ]
+  set_property -dict [ list \
+   CONFIG.FIFO_DEPTH {32768} \
+   CONFIG.FIFO_MODE {2} \
+   CONFIG.HAS_RD_DATA_COUNT {1} \
+   CONFIG.HAS_TLAST {1} \
+   CONFIG.HAS_WR_DATA_COUNT {1} \
+   CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $rx_data_fifo
+
+  # Create instance: rx_rst_n, and set properties
+  set rx_rst_n [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_rst_n ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $rx_rst_n
+
+  # Create instance: sfp_tx_dis, and set properties
+  set sfp_tx_dis [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 sfp_tx_dis ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {1} \
+ ] $sfp_tx_dis
+
+  # Create instance: tx_data_fifo, and set properties
+  set tx_data_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 tx_data_fifo ]
+  set_property -dict [ list \
+   CONFIG.FIFO_DEPTH {32768} \
+   CONFIG.FIFO_MODE {2} \
+   CONFIG.HAS_RD_DATA_COUNT {1} \
+   CONFIG.HAS_TLAST {1} \
+   CONFIG.HAS_WR_DATA_COUNT {1} \
+   CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $tx_data_fifo
+
+  # Create instance: tx_rst_n, and set properties
+  set tx_rst_n [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 tx_rst_n ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $tx_rst_n
+
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {0} \
+   CONFIG.CONST_WIDTH {56} \
+ ] $xlconstant_0
+
+  # Create instance: xlconstant_1, and set properties
+  set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {0} \
+ ] $xlconstant_1
+
+  # Create instance: xlconstant_2, and set properties
+  set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {5} \
+   CONFIG.CONST_WIDTH {3} \
+ ] $xlconstant_2
+
+  # Create instance: xxv_ethernet_0, and set properties
+  set xxv_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xxv_ethernet:3.3 xxv_ethernet_0 ]
+  set_property -dict [ list \
+   CONFIG.BASE_R_KR {BASE-R} \
+   CONFIG.GT_GROUP_SELECT {Quad_X0Y0} \
+   CONFIG.INCLUDE_AXI4_INTERFACE {1} \
+   CONFIG.INCLUDE_STATISTICS_COUNTERS {1} \
+   CONFIG.LANE1_GT_LOC {X0Y0} \
+ ] $xxv_ethernet_0
+
+  # Create instance: zups
+  create_hier_cell_zups [current_bd_instance .] zups
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins tx_data_fifo/S_AXIS]
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins zups/S01_AXI]
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins zups/S02_AXI]
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_SG [get_bd_intf_pins axi_dma_0/M_AXI_SG] [get_bd_intf_pins zups/S00_AXI]
+  connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins tx_data_fifo/M_AXIS] [get_bd_intf_pins xxv_ethernet_0/axis_tx_0]
+  connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins rx_data_fifo/M_AXIS]
+  connect_bd_intf_net -intf_net gt_ref_clk_1 [get_bd_intf_ports gt_ref_clk] [get_bd_intf_pins xxv_ethernet_0/gt_ref_clk]
+  connect_bd_intf_net -intf_net gt_rx_1 [get_bd_intf_ports gt_rx] [get_bd_intf_pins xxv_ethernet_0/gt_rx]
+  connect_bd_intf_net -intf_net xxv_ethernet_0_axis_rx_0 [get_bd_intf_pins rx_data_fifo/S_AXIS] [get_bd_intf_pins xxv_ethernet_0/axis_rx_0]
+  connect_bd_intf_net -intf_net xxv_ethernet_0_gt_tx [get_bd_intf_ports gt_tx] [get_bd_intf_pins xxv_ethernet_0/gt_tx]
+  connect_bd_intf_net -intf_net zups_M00_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins zups/M00_AXI]
+  connect_bd_intf_net -intf_net zups_M01_AXI [get_bd_intf_pins xxv_ethernet_0/s_axi_0] [get_bd_intf_pins zups/M01_AXI]
+
+  # Create port connections
+  connect_bd_net -net Net [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins rx_data_fifo/s_axis_aclk] [get_bd_pins xxv_ethernet_0/rx_clk_out_0] [get_bd_pins xxv_ethernet_0/rx_core_clk_0] [get_bd_pins zups/S02_ACLK]
+  connect_bd_net -net Net1 [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins xxv_ethernet_0/dclk] [get_bd_pins xxv_ethernet_0/s_axi_aclk_0] [get_bd_pins zups/pl_clk0]
+  connect_bd_net -net Net2 [get_bd_pins xlconstant_2/dout] [get_bd_pins xxv_ethernet_0/rxoutclksel_in_0] [get_bd_pins xxv_ethernet_0/txoutclksel_in_0]
+  connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins zups/In0]
+  connect_bd_net -net axi_dma_0_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_0/mm2s_prmry_reset_out_n] [get_bd_pins dma_tx_rst/Op1]
+  connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins zups/In1]
+  connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_0/s2mm_prmry_reset_out_n] [get_bd_pins dma_rx_rst/Op1]
+  connect_bd_net -net dma_rx_rst_Res [get_bd_pins dma_rx_rst/Res] [get_bd_pins xxv_ethernet_0/rx_reset_0]
+  connect_bd_net -net dma_tx_rst_Res [get_bd_pins dma_tx_rst/Res] [get_bd_pins xxv_ethernet_0/tx_reset_0]
+  connect_bd_net -net tx_rst_n_Res [get_bd_pins rx_data_fifo/s_axis_aresetn] [get_bd_pins rx_rst_n/Res] [get_bd_pins zups/S02_ARESETN]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins tx_data_fifo/s_axis_aresetn] [get_bd_pins tx_rst_n/Res] [get_bd_pins zups/S01_ARESETN]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins xxv_ethernet_0/tx_preamblein_0]
+  connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconstant_1/dout] [get_bd_pins xxv_ethernet_0/ctl_tx_send_idle_0] [get_bd_pins xxv_ethernet_0/ctl_tx_send_lfi_0] [get_bd_pins xxv_ethernet_0/ctl_tx_send_rfi_0]
+  connect_bd_net -net xlconstant_2_dout [get_bd_ports sfp_tx_dis] [get_bd_pins sfp_tx_dis/dout]
+  connect_bd_net -net xxv_ethernet_0_tx_clk_out_0 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins tx_data_fifo/s_axis_aclk] [get_bd_pins xxv_ethernet_0/tx_clk_out_0] [get_bd_pins zups/S01_ACLK]
+  connect_bd_net -net xxv_ethernet_0_user_rx_reset_0 [get_bd_pins rx_rst_n/Op1] [get_bd_pins xxv_ethernet_0/user_rx_reset_0]
+  connect_bd_net -net xxv_ethernet_0_user_tx_reset_0 [get_bd_pins tx_rst_n/Op1] [get_bd_pins xxv_ethernet_0/user_tx_reset_0]
+  connect_bd_net -net zups_Res [get_bd_pins xxv_ethernet_0/gtwiz_reset_rx_datapath_0] [get_bd_pins xxv_ethernet_0/gtwiz_reset_tx_datapath_0] [get_bd_pins zups/Res]
+  connect_bd_net -net zups_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins xxv_ethernet_0/s_axi_aresetn_0] [get_bd_pins zups/peripheral_aresetn]
+  connect_bd_net -net zups_peripheral_reset [get_bd_pins xxv_ethernet_0/sys_reset] [get_bd_pins zups/peripheral_reset]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM] -force
+  assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_PCIE_LOW] -force
+  assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_PCIE_LOW] -force
+  assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_PCIE_LOW] -force
+  assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI] -force
+  assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI] -force
+  assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI] -force
+  assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zups/zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
+  assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zups/zynq_ultra_ps_e_0/Data] [get_bd_addr_segs xxv_ethernet_0/s_axi_0/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs zups/zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml
new file mode 100644
index 0000000..3d23f3b
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml
@@ -0,0 +1,4681 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_cc_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_CLK</spirit:name>
+      <spirit:displayName>SI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>s_axi_aclk frequency</spirit:displayName>
+          <spirit:description>s_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">156250000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_CLK</spirit:name>
+      <spirit:displayName>MI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>m_axi_aclk frequency</spirit:displayName>
+          <spirit:description>m_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">124998749</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF">M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET">M_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_RST</spirit:name>
+      <spirit:displayName>SI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
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+                  </spirit:parameter>
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+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
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+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
+          </spirit:transTypeDef>
+          <spirit:service>
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+            <spirit:serviceTypeDefs>
+              <spirit:serviceTypeDef>
+                <spirit:typeName>tlm</spirit:typeName>
+                <spirit:parameters>
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+                    <spirit:value>wr_socket</spirit:value>
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+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
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+        </spirit:transactional>
+      </spirit:port>
+      <spirit:port>
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+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+            <spirit:initiative>provides</spirit:initiative>
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+                <spirit:typeName>tlm</spirit:typeName>
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+                    <spirit:name>name</spirit:name>
+                    <spirit:value>rd_socket</spirit:value>
+                  </spirit:parameter>
+                </spirit:parameters>
+              </spirit:serviceTypeDef>
+            </spirit:serviceTypeDefs>
+          </spirit:service>
+          <spirit:connection>
+            <spirit:maxConnections>1</spirit:maxConnections>
+          </spirit:connection>
+        </spirit:transactional>
+      </spirit:port>
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+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
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+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynquplus</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">128</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S_AXI_ACLK_RATIO</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ACLK_RATIO">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_M_AXI_ACLK_RATIO</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ACLK_RATIO">2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_IS_ACLK_ASYNC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_IS_ACLK_ASYNC">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_PROTOCOL">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_SUPPORTS_USER_SIGNALS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SUPPORTS_USER_SIGNALS">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_AWUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_ARUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_WUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_RUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_BUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_SUPPORTS_WRITE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SUPPORTS_WRITE">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
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+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SUPPORTS_READ">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
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+      <spirit:name>ID_WIDTH</spirit:name>
+      <spirit:displayName>ID Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="6" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AWUSER_WIDTH" spirit:order="7" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ARUSER_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RUSER_WIDTH" spirit:order="9" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WUSER_WIDTH" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUSER_WIDTH" spirit:order="11" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_ASYNC</spirit:name>
+      <spirit:displayName>Is ACLK Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_ASYNC" spirit:choiceRef="choice_pairs_6e9436bb" spirit:order="12">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYNCHRONIZATION_STAGES</spirit:name>
+      <spirit:displayName>Synchronization Stages</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYNCHRONIZATION_STAGES" spirit:order="13" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_RATIO</spirit:name>
+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_RATIO" spirit:choiceRef="choice_list_42702293" spirit:order="1635284">1:2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pl_eth_10g_auto_cc_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI Clock Converter</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:systemCLibraries>
+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
+      </xilinx:systemCLibraries>
+      <xilinx:coreRevision>21</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_ASYNC" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b96317db"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cb3b8462"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="5f9a31f4"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="99129be2"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="9de7b80f"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc
new file mode 100644
index 0000000..4265305
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc
@@ -0,0 +1,33 @@
+###############################################################################################################
+# Core-Level Timing Constraints for axi_clock_converter Component "pl_eth_10g_auto_cc_0"
+###############################################################################################################
+#
+# This component is configured to perform asynchronous clock-domain-crossing.
+# In order for these core-level constraints to work properly, 
+# the following rules apply to your system-level timing constraints:
+#   1. Each of the nets connected to the s_axi_aclk and m_axi_aclk ports of this component
+#      must have exactly one clock defined on it, using either
+#      a) a create_clock command on a top-level clock pin specified in your system XDC file, or
+#      b) a create_generated_clock command, typically generated automatically by a core 
+#          producing a derived clock signal.
+#   2. The s_axi_aclk and m_axi_aclk ports of this component should not be connected to the
+#      same clock source.
+#
+set s_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
+set m_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance m_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
+set_false_path -from [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == O}] 
+set_false_path -from [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == O}] 
+create_waiver -internal -scope -type CDC -id CDC-10 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
+-description {Waiving CDC-10 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock.  Hence there should not be any issues cause by this logic}
+
+create_waiver -internal -scope -type CDC -id CDC-11 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
+-description {Waiving CDC-11 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock.  Hence there should not be any issues cause by this logic}
+
+create_waiver -internal -scope -type CDC -id CDC-15 -user axi_clock_converter -tags "1024442" -from [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_*/RAM*/CLK]\ 
+-to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg*/D]\
+-description {Waiving CDC-15 Timing constraints are processed during implementation, not synthesis. The xdc is marked only to be used during implementation, as advised by the XDC folks at the time.}
+
+create_waiver -internal -scope -type METHODOLOGY -id {LUTAR-1} -user "axi_clock_converter" -desc {the pathway is completely within fifo-gen, and that path is present dual-clock usage}\
+-tags "1024444"\
+ -objects [get_cells -hierarchical "*gen_clock_conv.gen_async_conv.asyncfifo_axi*"] \
+ -objects [get_pins -hierarchical * -filter "(NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg*/PRE) || (NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg*/PRE)"]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_ooc.xdc
new file mode 100644
index 0000000..5d033a7
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_ooc.xdc
@@ -0,0 +1,49 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.cpp
new file mode 100644
index 0000000..7b8153c
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.cpp
@@ -0,0 +1,1016 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_cc_0_sc.h"
+
+#include "pl_eth_10g_auto_cc_0.h"
+
+#include "axi_clock_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_cc_0::pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_cc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->S_TARGET_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->S_TARGET_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(m_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->M_INITIATOR_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_cc_0::pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_cc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->S_TARGET_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->S_TARGET_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(m_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->M_INITIATOR_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_cc_0::pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_cc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->S_TARGET_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->S_TARGET_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(m_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->M_INITIATOR_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_cc_0::pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_0_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(m_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_cc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->S_TARGET_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+    mp_impl->S_TARGET_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+    mp_impl->M_INITIATOR_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_cc_0::pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_0_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(m_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_cc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->S_TARGET_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+    mp_impl->S_TARGET_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->M_INITIATOR_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+    mp_impl->M_INITIATOR_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_cc_0::~pl_eth_10g_auto_cc_0()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_arlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    delete mp_S_AXI_wr_socket_stub;
+  }
+
+  delete mp_M_AXI_transactor;
+  delete mp_m_axi_arlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    delete mp_M_AXI_wr_socket_stub;
+  }
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_cc_0);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_cc_0);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_cc_0);
+SC_REGISTER_BV(128);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.h
new file mode 100644
index 0000000..fb548d1
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.h
@@ -0,0 +1,460 @@
+#ifndef IP_PL_ETH_10G_AUTO_CC_0_H_
+#define IP_PL_ETH_10G_AUTO_CC_0_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_cc_0_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_CC_0_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.v
new file mode 100644
index 0000000..f0679af
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0.v
@@ -0,0 +1,290 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
+// IP Revision: 21
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_cc_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_aclk,
+  m_axi_aresetn,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
+input wire m_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
+input wire m_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [127 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_clock_converter_v2_1_21_axi_clock_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(128),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(1),
+    .C_AXI_PROTOCOL(0),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_SUPPORTS_WRITE(0),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(32'H00000000),
+    .s_axi_awlen(8'H00),
+    .s_axi_awsize(3'H0),
+    .s_axi_awburst(2'H1),
+    .s_axi_awlock(1'H0),
+    .s_axi_awcache(4'H0),
+    .s_axi_awprot(3'H0),
+    .s_axi_awregion(4'H0),
+    .s_axi_awqos(4'H0),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(1'H0),
+    .s_axi_awready(),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(128'H00000000000000000000000000000000),
+    .s_axi_wstrb(16'HFFFF),
+    .s_axi_wlast(1'H1),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(1'H0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_buser(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'H0),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(m_axi_aclk),
+    .m_axi_aresetn(m_axi_aresetn),
+    .m_axi_awid(),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'H0),
+    .m_axi_wid(),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'H0),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(2'H0),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(1'H0),
+    .m_axi_bready(),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.cpp
new file mode 100644
index 0000000..c5673dd
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.cpp
@@ -0,0 +1,97 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_cc_0_sc.h"
+
+#include "axi_clock_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_cc_0_sc::pl_eth_10g_auto_cc_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_cc_0", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_AXI_ID_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
+    model_param_props.addLong("C_AXI_DATA_WIDTH", "128");
+    model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
+    model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
+    model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "1");
+    model_param_props.addLong("C_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
+    model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "0");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
+    model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_clock_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  S_TARGET_rd_socket = mp_impl->S_TARGET_rd_socket;
+  S_TARGET_wr_socket = mp_impl->S_TARGET_wr_socket;
+  M_INITIATOR_rd_socket = mp_impl->M_INITIATOR_rd_socket;
+  M_INITIATOR_wr_socket = mp_impl->M_INITIATOR_wr_socket;
+}
+
+pl_eth_10g_auto_cc_0_sc::~pl_eth_10g_auto_cc_0_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.h
new file mode 100644
index 0000000..e688694
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_CC_0_SC_H_
+#define IP_PL_ETH_10G_AUTO_CC_0_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_clock_converter;
+
+class DllExport pl_eth_10g_auto_cc_0_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_cc_0_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_0_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
+  xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_clock_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_cc_0_sc(const pl_eth_10g_auto_cc_0_sc&);
+  const pl_eth_10g_auto_cc_0_sc& operator=(const pl_eth_10g_auto_cc_0_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_CC_0_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_stub.sv
new file mode 100644
index 0000000..1750e89
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sim/pl_eth_10g_auto_cc_0_stub.sv
@@ -0,0 +1,194 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_cc_0_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_cc_0 (
+  input bit_as_bool s_axi_aclk,
+  input bit_as_bool s_axi_aresetn,
+  input bit [31 : 0] s_axi_araddr,
+  input bit [7 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [0 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arregion,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [127 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  input bit_as_bool m_axi_aclk,
+  input bit_as_bool m_axi_aresetn,
+  output bit [31 : 0] m_axi_araddr,
+  output bit [7 : 0] m_axi_arlen,
+  output bit [2 : 0] m_axi_arsize,
+  output bit [1 : 0] m_axi_arburst,
+  output bit [0 : 0] m_axi_arlock,
+  output bit [3 : 0] m_axi_arcache,
+  output bit [2 : 0] m_axi_arprot,
+  output bit [3 : 0] m_axi_arregion,
+  output bit [3 : 0] m_axi_arqos,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [127 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rlast,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_cc_0 (s_axi_aclk,s_axi_aresetn,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [127 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  input bit m_axi_aclk;
+  input bit m_axi_aresetn;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [127 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_cc_0 (s_axi_aclk,s_axi_aresetn,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [127 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  input bit m_axi_aclk;
+  input bit m_axi_aresetn;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [127 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/synth/pl_eth_10g_auto_cc_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/synth/pl_eth_10g_auto_cc_0.v
new file mode 100644
index 0000000..8f8e4c1
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/synth/pl_eth_10g_auto_cc_0.v
@@ -0,0 +1,292 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
+// IP Revision: 21
+
+(* X_CORE_INFO = "axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_cc_0,axi_clock_converter_v2_1_21_axi_clock_converter,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_cc_0,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUS\
+ER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=0,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=3}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_cc_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_aclk,
+  m_axi_aresetn,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
+input wire m_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
+input wire m_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [127 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_clock_converter_v2_1_21_axi_clock_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(128),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(1),
+    .C_AXI_PROTOCOL(0),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_SUPPORTS_WRITE(0),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(32'H00000000),
+    .s_axi_awlen(8'H00),
+    .s_axi_awsize(3'H0),
+    .s_axi_awburst(2'H1),
+    .s_axi_awlock(1'H0),
+    .s_axi_awcache(4'H0),
+    .s_axi_awprot(3'H0),
+    .s_axi_awregion(4'H0),
+    .s_axi_awqos(4'H0),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(1'H0),
+    .s_axi_awready(),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(128'H00000000000000000000000000000000),
+    .s_axi_wstrb(16'HFFFF),
+    .s_axi_wlast(1'H1),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(1'H0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_buser(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'H0),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(m_axi_aclk),
+    .m_axi_aresetn(m_axi_aresetn),
+    .m_axi_awid(),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'H0),
+    .m_axi_wid(),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'H0),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(2'H0),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(1'H0),
+    .m_axi_bready(),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sysc/axi_clock_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sysc/axi_clock_converter.cpp
new file mode 100644
index 0000000..63d46be
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sysc/axi_clock_converter.cpp
@@ -0,0 +1,24 @@
+#include "axi_clock_converter.h"
+#include <sstream>
+
+axi_clock_converter::axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
+	sc_module(module_name) {
+		M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
+		M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
+	 	S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
+		S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
+		P1 = new xtlm::xtlm_aximm_passthru_module("P1");
+		P2 = new xtlm::xtlm_aximm_passthru_module("P2");
+		P1->initiator_socket->bind(*M_INITIATOR_rd_socket);
+		P2->initiator_socket->bind(*M_INITIATOR_wr_socket);
+		S_TARGET_rd_socket->bind(*(P1->target_socket));
+		S_TARGET_wr_socket->bind(*(P2->target_socket));
+		}
+axi_clock_converter::~axi_clock_converter() {
+	delete M_INITIATOR_wr_socket;
+	delete M_INITIATOR_rd_socket;
+	delete S_TARGET_wr_socket;
+	delete S_TARGET_rd_socket;
+	delete P1;
+	delete P2;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sysc/axi_clock_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sysc/axi_clock_converter.h
new file mode 100644
index 0000000..5769de2
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/sysc/axi_clock_converter.h
@@ -0,0 +1,27 @@
+#ifndef _axi_clock_converter_
+#define _axi_clock_converter_
+#include <xtlm.h>
+#include <utils/xtlm_aximm_passthru_module.h>
+#include <systemc>
+
+class axi_clock_converter:public sc_module{
+	public:
+		axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
+		virtual ~axi_clock_converter();
+		SC_HAS_PROCESS(axi_clock_converter);
+	xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
+	xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket*  M_INITIATOR_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
+  sc_in<bool> s_axi_aclk;
+	sc_in<bool> s_axi_aresetn;
+  sc_in<bool> m_axi_aclk;
+	sc_in<bool> m_axi_aresetn;
+  
+	private:
+	xtlm::xtlm_aximm_passthru_module *P1;
+	xtlm::xtlm_aximm_passthru_module *P2;	
+};
+
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml
new file mode 100644
index 0000000..2cfd896
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml
@@ -0,0 +1,4681 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_cc_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
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+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">WRITE_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">WRITE_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_CLK</spirit:name>
+      <spirit:displayName>SI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>s_axi_aclk frequency</spirit:displayName>
+          <spirit:description>s_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">156250000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_CLK</spirit:name>
+      <spirit:displayName>MI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>m_axi_aclk frequency</spirit:displayName>
+          <spirit:description>m_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">124998749</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF">M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET">M_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_RST</spirit:name>
+      <spirit:displayName>SI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_RST</spirit:name>
+      <spirit:displayName>MI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_INITIATOR_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>M_INITIATOR_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_TARGET_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>S_TARGET_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesis</spirit:name>
+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>axi_clock_converter_v2_1_21_axi_clock_converter</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+          </spirit:parameter>
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+        <spirit:name>C_AXI_RUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_BUSER_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_SUPPORTS_WRITE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SUPPORTS_WRITE">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AXI_SUPPORTS_READ</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXI_SUPPORTS_READ">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_SYNCHRONIZER_STAGE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
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+    <spirit:choice>
+      <spirit:name>choice_list_40181835</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+      <spirit:enumeration>64</spirit:enumeration>
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+      <spirit:enumeration>256</spirit:enumeration>
+      <spirit:enumeration>512</spirit:enumeration>
+      <spirit:enumeration>1024</spirit:enumeration>
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+      <spirit:name>choice_list_42702293</spirit:name>
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+      <spirit:enumeration>15:1</spirit:enumeration>
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+      <spirit:enumeration>1:3</spirit:enumeration>
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+      <spirit:enumeration>1:7</spirit:enumeration>
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+      <spirit:enumeration>1:9</spirit:enumeration>
+      <spirit:enumeration>1:10</spirit:enumeration>
+      <spirit:enumeration>1:11</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_list_7235ff92</spirit:name>
+      <spirit:enumeration>AXI4</spirit:enumeration>
+      <spirit:enumeration>AXI3</spirit:enumeration>
+      <spirit:enumeration>AXI4LITE</spirit:enumeration>
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+    <spirit:choice>
+      <spirit:name>choice_pairs_940700f2</spirit:name>
+      <spirit:enumeration spirit:text="READ WRITE">READ_WRITE</spirit:enumeration>
+      <spirit:enumeration spirit:text="READ ONLY">READ_ONLY</spirit:enumeration>
+      <spirit:enumeration spirit:text="WRITE ONLY">WRITE_ONLY</spirit:enumeration>
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+        <spirit:logicalName>axi_clock_converter_v2_1_21</spirit:logicalName>
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+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
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+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
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+      <spirit:file>
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+      <spirit:file>
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+    <spirit:fileSet>
+      <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>pl_eth_10g_auto_cc_1_clocks.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:define>
+          <spirit:name>processing_order</spirit:name>
+          <spirit:value>late</spirit:value>
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+  <spirit:description>The AXI Clock Converter IP provides the facility to add a clock domain crossing between an AXI4/AXI3/AXI4-Lite master and slave.</spirit:description>
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+    <spirit:parameter>
+      <spirit:name>PROTOCOL</spirit:name>
+      <spirit:displayName>PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROTOCOL" spirit:choiceRef="choice_list_7235ff92" spirit:order="2">AXI4</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>READ_WRITE_MODE</spirit:name>
+      <spirit:displayName>READ_WRITE Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.READ_WRITE_MODE" spirit:choiceRef="choice_pairs_940700f2" spirit:order="3">WRITE_ONLY</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH" spirit:order="4" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="5">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ID_WIDTH</spirit:name>
+      <spirit:displayName>ID Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="6" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AWUSER_WIDTH" spirit:order="7" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ARUSER_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RUSER_WIDTH" spirit:order="9" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WUSER_WIDTH" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUSER_WIDTH" spirit:order="11" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_ASYNC</spirit:name>
+      <spirit:displayName>Is ACLK Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_ASYNC" spirit:choiceRef="choice_pairs_6e9436bb" spirit:order="12">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYNCHRONIZATION_STAGES</spirit:name>
+      <spirit:displayName>Synchronization Stages</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYNCHRONIZATION_STAGES" spirit:order="13" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_RATIO</spirit:name>
+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_RATIO" spirit:choiceRef="choice_list_42702293" spirit:order="1635284">1:2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pl_eth_10g_auto_cc_1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI Clock Converter</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:systemCLibraries>
+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
+      </xilinx:systemCLibraries>
+      <xilinx:coreRevision>21</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_ASYNC" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b96317db"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cb3b8462"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="5f9a31f4"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="99129be2"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="9de7b80f"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_clocks.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_clocks.xdc
new file mode 100644
index 0000000..3d402d2
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_clocks.xdc
@@ -0,0 +1,33 @@
+###############################################################################################################
+# Core-Level Timing Constraints for axi_clock_converter Component "pl_eth_10g_auto_cc_1"
+###############################################################################################################
+#
+# This component is configured to perform asynchronous clock-domain-crossing.
+# In order for these core-level constraints to work properly, 
+# the following rules apply to your system-level timing constraints:
+#   1. Each of the nets connected to the s_axi_aclk and m_axi_aclk ports of this component
+#      must have exactly one clock defined on it, using either
+#      a) a create_clock command on a top-level clock pin specified in your system XDC file, or
+#      b) a create_generated_clock command, typically generated automatically by a core 
+#          producing a derived clock signal.
+#   2. The s_axi_aclk and m_axi_aclk ports of this component should not be connected to the
+#      same clock source.
+#
+set s_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
+set m_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance m_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
+set_false_path -from [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == O}] 
+set_false_path -from [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == O}] 
+create_waiver -internal -scope -type CDC -id CDC-10 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
+-description {Waiving CDC-10 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock.  Hence there should not be any issues cause by this logic}
+
+create_waiver -internal -scope -type CDC -id CDC-11 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
+-description {Waiving CDC-11 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock.  Hence there should not be any issues cause by this logic}
+
+create_waiver -internal -scope -type CDC -id CDC-15 -user axi_clock_converter -tags "1024442" -from [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_*/RAM*/CLK]\ 
+-to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg*/D]\
+-description {Waiving CDC-15 Timing constraints are processed during implementation, not synthesis. The xdc is marked only to be used during implementation, as advised by the XDC folks at the time.}
+
+create_waiver -internal -scope -type METHODOLOGY -id {LUTAR-1} -user "axi_clock_converter" -desc {the pathway is completely within fifo-gen, and that path is present dual-clock usage}\
+-tags "1024444"\
+ -objects [get_cells -hierarchical "*gen_clock_conv.gen_async_conv.asyncfifo_axi*"] \
+ -objects [get_pins -hierarchical * -filter "(NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg*/PRE) || (NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg*/PRE)"]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_ooc.xdc
new file mode 100644
index 0000000..5d033a7
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_ooc.xdc
@@ -0,0 +1,49 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp
new file mode 100644
index 0000000..248a50d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp
@@ -0,0 +1,1046 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_cc_1_sc.h"
+
+#include "pl_eth_10g_auto_cc_1.h"
+
+#include "axi_clock_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->S_TARGET_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->S_TARGET_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->CLK(m_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->M_INITIATOR_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->S_TARGET_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->S_TARGET_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->CLK(m_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->M_INITIATOR_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->S_TARGET_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->S_TARGET_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->CLK(m_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->M_INITIATOR_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_1_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->CLK(m_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+    mp_impl->S_TARGET_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->S_TARGET_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+    mp_impl->M_INITIATOR_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_cc_1_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_aclk("m_axi_aclk"), m_axi_aresetn("m_axi_aresetn"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+  mp_impl->m_axi_aclk(m_axi_aclk);
+  mp_impl->m_axi_aresetn(m_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->CLK(m_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+    mp_impl->S_TARGET_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->S_TARGET_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+    mp_impl->M_INITIATOR_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->M_INITIATOR_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_cc_1::~pl_eth_10g_auto_cc_1()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_awlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    delete mp_S_AXI_rd_socket_stub;
+  }
+
+  delete mp_M_AXI_transactor;
+  delete mp_m_axi_awlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_cc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    delete mp_M_AXI_rd_socket_stub;
+  }
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_cc_1);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_cc_1);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_cc_1);
+SC_REGISTER_BV(128);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.h
new file mode 100644
index 0000000..802e58c
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.h
@@ -0,0 +1,490 @@
+#ifndef IP_PL_ETH_10G_AUTO_CC_1_H_
+#define IP_PL_ETH_10G_AUTO_CC_1_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_cc_1_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< bool > m_axi_aclk;
+  sc_core::sc_in< bool > m_axi_aresetn;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_CC_1_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v
new file mode 100644
index 0000000..a330076
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v
@@ -0,0 +1,308 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
+// IP Revision: 21
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_cc_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  m_axi_aclk,
+  m_axi_aresetn,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
+input wire m_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
+input wire m_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [127 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [15 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+
+  axi_clock_converter_v2_1_21_axi_clock_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(128),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(1),
+    .C_AXI_PROTOCOL(0),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(0),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(32'H00000000),
+    .s_axi_arlen(8'H00),
+    .s_axi_arsize(3'H0),
+    .s_axi_arburst(2'H1),
+    .s_axi_arlock(1'H0),
+    .s_axi_arcache(4'H0),
+    .s_axi_arprot(3'H0),
+    .s_axi_arregion(4'H0),
+    .s_axi_arqos(4'H0),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(1'H0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'H0),
+    .m_axi_aclk(m_axi_aclk),
+    .m_axi_aresetn(m_axi_aresetn),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'H0),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(128'H00000000000000000000000000000000),
+    .m_axi_rresp(2'H0),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(1'H0),
+    .m_axi_rready()
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.cpp
new file mode 100644
index 0000000..ed398e0
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.cpp
@@ -0,0 +1,97 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_cc_1_sc.h"
+
+#include "axi_clock_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_cc_1_sc::pl_eth_10g_auto_cc_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_cc_1", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_AXI_ID_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
+    model_param_props.addLong("C_AXI_DATA_WIDTH", "128");
+    model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
+    model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
+    model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "1");
+    model_param_props.addLong("C_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
+    model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "0");
+    model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_clock_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  S_TARGET_rd_socket = mp_impl->S_TARGET_rd_socket;
+  S_TARGET_wr_socket = mp_impl->S_TARGET_wr_socket;
+  M_INITIATOR_rd_socket = mp_impl->M_INITIATOR_rd_socket;
+  M_INITIATOR_wr_socket = mp_impl->M_INITIATOR_wr_socket;
+}
+
+pl_eth_10g_auto_cc_1_sc::~pl_eth_10g_auto_cc_1_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.h
new file mode 100644
index 0000000..9ee8d82
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_CC_1_SC_H_
+#define IP_PL_ETH_10G_AUTO_CC_1_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_clock_converter;
+
+class DllExport pl_eth_10g_auto_cc_1_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_cc_1_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_cc_1_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
+  xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_clock_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_cc_1_sc(const pl_eth_10g_auto_cc_1_sc&);
+  const pl_eth_10g_auto_cc_1_sc& operator=(const pl_eth_10g_auto_cc_1_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_CC_1_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_stub.sv
new file mode 100644
index 0000000..4b26c48
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1_stub.sv
@@ -0,0 +1,212 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_cc_1_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_cc_1 (
+  input bit_as_bool s_axi_aclk,
+  input bit_as_bool s_axi_aresetn,
+  input bit [31 : 0] s_axi_awaddr,
+  input bit [7 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [0 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awregion,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [127 : 0] s_axi_wdata,
+  input bit [15 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  input bit_as_bool m_axi_aclk,
+  input bit_as_bool m_axi_aresetn,
+  output bit [31 : 0] m_axi_awaddr,
+  output bit [7 : 0] m_axi_awlen,
+  output bit [2 : 0] m_axi_awsize,
+  output bit [1 : 0] m_axi_awburst,
+  output bit [0 : 0] m_axi_awlock,
+  output bit [3 : 0] m_axi_awcache,
+  output bit [2 : 0] m_axi_awprot,
+  output bit [3 : 0] m_axi_awregion,
+  output bit [3 : 0] m_axi_awqos,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [127 : 0] m_axi_wdata,
+  output bit [15 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wlast,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_cc_1 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,m_axi_aclk,m_axi_aresetn,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready)
+(* integer foreign = "SystemC";
+*);
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [127 : 0] s_axi_wdata;
+  input bit [15 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit m_axi_aclk;
+  input bit m_axi_aresetn;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [127 : 0] m_axi_wdata;
+  output wire [15 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_cc_1 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,m_axi_aclk,m_axi_aresetn,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready)
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [127 : 0] s_axi_wdata;
+  input bit [15 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit m_axi_aclk;
+  input bit m_axi_aresetn;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [127 : 0] m_axi_wdata;
+  output wire [15 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v
new file mode 100644
index 0000000..37cf1dc
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v
@@ -0,0 +1,310 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
+// IP Revision: 21
+
+(* X_CORE_INFO = "axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_cc_1,axi_clock_converter_v2_1_21_axi_clock_converter,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_cc_1,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUS\
+ER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_SYNCHRONIZER_STAGE=3}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_cc_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  m_axi_aclk,
+  m_axi_aresetn,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
+input wire m_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
+input wire m_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [127 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [15 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+
+  axi_clock_converter_v2_1_21_axi_clock_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(128),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(1),
+    .C_AXI_PROTOCOL(0),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(0),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(32'H00000000),
+    .s_axi_arlen(8'H00),
+    .s_axi_arsize(3'H0),
+    .s_axi_arburst(2'H1),
+    .s_axi_arlock(1'H0),
+    .s_axi_arcache(4'H0),
+    .s_axi_arprot(3'H0),
+    .s_axi_arregion(4'H0),
+    .s_axi_arqos(4'H0),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(1'H0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'H0),
+    .m_axi_aclk(m_axi_aclk),
+    .m_axi_aresetn(m_axi_aresetn),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'H0),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(128'H00000000000000000000000000000000),
+    .m_axi_rresp(2'H0),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(1'H0),
+    .m_axi_rready()
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sysc/axi_clock_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sysc/axi_clock_converter.cpp
new file mode 100644
index 0000000..63d46be
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sysc/axi_clock_converter.cpp
@@ -0,0 +1,24 @@
+#include "axi_clock_converter.h"
+#include <sstream>
+
+axi_clock_converter::axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
+	sc_module(module_name) {
+		M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
+		M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
+	 	S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
+		S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
+		P1 = new xtlm::xtlm_aximm_passthru_module("P1");
+		P2 = new xtlm::xtlm_aximm_passthru_module("P2");
+		P1->initiator_socket->bind(*M_INITIATOR_rd_socket);
+		P2->initiator_socket->bind(*M_INITIATOR_wr_socket);
+		S_TARGET_rd_socket->bind(*(P1->target_socket));
+		S_TARGET_wr_socket->bind(*(P2->target_socket));
+		}
+axi_clock_converter::~axi_clock_converter() {
+	delete M_INITIATOR_wr_socket;
+	delete M_INITIATOR_rd_socket;
+	delete S_TARGET_wr_socket;
+	delete S_TARGET_rd_socket;
+	delete P1;
+	delete P2;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sysc/axi_clock_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sysc/axi_clock_converter.h
new file mode 100644
index 0000000..5769de2
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sysc/axi_clock_converter.h
@@ -0,0 +1,27 @@
+#ifndef _axi_clock_converter_
+#define _axi_clock_converter_
+#include <xtlm.h>
+#include <utils/xtlm_aximm_passthru_module.h>
+#include <systemc>
+
+class axi_clock_converter:public sc_module{
+	public:
+		axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
+		virtual ~axi_clock_converter();
+		SC_HAS_PROCESS(axi_clock_converter);
+	xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
+	xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket*  M_INITIATOR_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
+  sc_in<bool> s_axi_aclk;
+	sc_in<bool> s_axi_aresetn;
+  sc_in<bool> m_axi_aclk;
+	sc_in<bool> m_axi_aresetn;
+  
+	private:
+	xtlm::xtlm_aximm_passthru_module *P1;
+	xtlm::xtlm_aximm_passthru_module *P2;	
+};
+
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml
new file mode 100644
index 0000000..baea326
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml
@@ -0,0 +1,4382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_ds_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">40</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">40</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_CLK</spirit:name>
+      <spirit:displayName>SI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>s_axi_aclk frequency</spirit:displayName>
+          <spirit:description>s_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">124998749</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_CLK</spirit:name>
+      <spirit:displayName>MI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>m_axi_aclk frequency</spirit:displayName>
+          <spirit:description>m_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">10000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MI_CLK" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 2) || (spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 4))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_RST</spirit:name>
+      <spirit:displayName>SI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_RST</spirit:name>
+      <spirit:displayName>MI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MI_RST" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 2) || (spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 4))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>initiator_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>initiator_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesis</spirit:name>
+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>axi_dwidth_converter_v2_1_22_top</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
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+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
+        <spirit:exportedName>blk_mem_gen_v8_4_4</spirit:exportedName>
+      </spirit:file>
+      <spirit:vendorExtensions>
+        <xilinx:subCoreRef>
+          <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="blk_mem_gen" xilinx:version="8.4" xilinx:isGenerated="true" xilinx:checksum="32756be7">
+            <xilinx:mode xilinx:name="copy_mode"/>
+          </xilinx:componentRef>
+        </xilinx:subCoreRef>
+      </spirit:vendorExtensions>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/2394/hdl/axi_dwidth_converter_v2_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>axi_dwidth_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/axi_dwidth_converter.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:logicalName>axi_dwidth_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/axi_dwidth_converter.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>axi_dwidth_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_ds_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_ds_0_sc.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_ds_0_sc.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_ds_0.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_ds_0.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_ds_0_stub.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>pl_eth_10g_auto_ds_0_clocks.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:define>
+          <spirit:name>processing_order</spirit:name>
+          <spirit:value>late</spirit:value>
+        </spirit:define>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>The AXI Data Width Converter IP provides the facility to increase or decrease the data width of WDATA and RDATA between an AXI4/AXI3/AXI4-Lite master and slave.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>PROTOCOL</spirit:name>
+      <spirit:displayName>PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROTOCOL" spirit:choiceRef="choice_list_7235ff92" spirit:order="2">AXI4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_WRITE_MODE</spirit:name>
+      <spirit:displayName>READ_WRITE Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.READ_WRITE_MODE" spirit:choiceRef="choice_pairs_940700f2" spirit:order="3">READ_WRITE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH" spirit:order="4" spirit:minimum="12" spirit:maximum="64" spirit:rangeType="long">40</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PACKING_LEVEL</spirit:name>
+      <spirit:displayName>Packing Level</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PACKING_LEVEL" spirit:choiceRef="choice_pairs_fe99fc86" spirit:order="5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>SI Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="6">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>MI Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MI_DATA_WIDTH" spirit:choiceRef="choice_list_151d8f4e" spirit:order="7">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SI_ID_WIDTH</spirit:name>
+      <spirit:displayName>SI ID Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SI_ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MAX_SPLIT_BEATS</spirit:name>
+      <spirit:displayName>Max Burst Length When Downsizing</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_SPLIT_BEATS" spirit:choiceRef="choice_list_0051c444" spirit:order="9">256</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_MODE</spirit:name>
+      <spirit:displayName>Upsizer FIFO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_MODE" spirit:choiceRef="choice_pairs_a4d18bae" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_ASYNC</spirit:name>
+      <spirit:displayName>Is ACLK Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_ASYNC" spirit:choiceRef="choice_pairs_37189c7b" spirit:order="11">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYNCHRONIZATION_STAGES</spirit:name>
+      <spirit:displayName>Synchronization Stages</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYNCHRONIZATION_STAGES" spirit:order="12" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_RATIO</spirit:name>
+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_RATIO" spirit:choiceRef="choice_list_42702293" spirit:order="1635284">1:2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pl_eth_10g_auto_ds_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI Data Width Converter</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:systemCLibraries>
+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
+      </xilinx:systemCLibraries>
+      <xilinx:coreRevision>22</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_ASYNC" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d6eff22"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3617c7e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="27eb12c9"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ec085b51"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="0a01a2fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_clocks.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_clocks.xdc
new file mode 100644
index 0000000..b7cd856
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_clocks.xdc
@@ -0,0 +1,7 @@
+###############################################################################################################
+# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_ds_0"
+###############################################################################################################
+#
+# This component is not configured to perform asynchronous clock-domain-crossing.
+# No timing core-level constraints are needed.
+# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_ooc.xdc
new file mode 100644
index 0000000..5d033a7
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_ooc.xdc
@@ -0,0 +1,49 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.cpp
new file mode 100644
index 0000000..dc1612c
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.cpp
@@ -0,0 +1,1242 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_ds_0_sc.h"
+
+#include "pl_eth_10g_auto_ds_0.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_ds_0::pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_ds_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWID(s_axi_awid);
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BID(s_axi_bid);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARID(s_axi_arid);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RID(s_axi_rid);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_ds_0::pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_ds_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWID(s_axi_awid);
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BID(s_axi_bid);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARID(s_axi_arid);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RID(s_axi_rid);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_ds_0::pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_ds_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWID(s_axi_awid);
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BID(s_axi_bid);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARID(s_axi_arid);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RID(s_axi_rid);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_ds_0::pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_0_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWID(s_axi_awid);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BID(s_axi_bid);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARID(s_axi_arid);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RID(s_axi_rid);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_ds_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_ds_0::pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_0_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWID(s_axi_awid);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BID(s_axi_bid);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARID(s_axi_arid);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RID(s_axi_rid);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_ds_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_ds_0::~pl_eth_10g_auto_ds_0()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_awlock_converter;
+  delete mp_s_axi_arlock_converter;
+
+  delete mp_M_AXI_transactor;
+  delete mp_m_axi_awlock_converter;
+  delete mp_m_axi_arlock_converter;
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_ds_0);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_ds_0);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_ds_0);
+SC_REGISTER_BV(128);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.h
new file mode 100644
index 0000000..981824d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.h
@@ -0,0 +1,668 @@
+#ifndef IP_PL_ETH_10G_AUTO_DS_0_H_
+#define IP_PL_ETH_10G_AUTO_DS_0_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_ds_0_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_DS_0_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.v
new file mode 100644
index 0000000..037732c
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0.v
@@ -0,0 +1,391 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_ds_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [15 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [39 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [15 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [15 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [39 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [15 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [39 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [39 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(16),
+    .C_SUPPORTS_ID(1),
+    .C_AXI_ADDR_WIDTH(40),
+    .C_S_AXI_DATA_WIDTH(128),
+    .C_M_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(256),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.cpp
new file mode 100644
index 0000000..8418c17
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.cpp
@@ -0,0 +1,96 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_ds_0_sc.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_ds_0_sc::pl_eth_10g_auto_ds_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_ds_0", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_S_AXI_ID_WIDTH", "16");
+    model_param_props.addLong("C_SUPPORTS_ID", "1");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "40");
+    model_param_props.addLong("C_S_AXI_DATA_WIDTH", "128");
+    model_param_props.addLong("C_M_AXI_DATA_WIDTH", "32");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
+    model_param_props.addLong("C_FIFO_MODE", "0");
+    model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
+    model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
+    model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
+    model_param_props.addLong("C_MAX_SPLIT_BEATS", "256");
+    model_param_props.addLong("C_PACKING_LEVEL", "1");
+    model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_dwidth_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  target_rd_socket = mp_impl->target_rd_socket;
+  target_wr_socket = mp_impl->target_wr_socket;
+  initiator_rd_socket = mp_impl->initiator_rd_socket;
+  initiator_wr_socket = mp_impl->initiator_wr_socket;
+}
+
+pl_eth_10g_auto_ds_0_sc::~pl_eth_10g_auto_ds_0_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.h
new file mode 100644
index 0000000..ada51fa
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_DS_0_SC_H_
+#define IP_PL_ETH_10G_AUTO_DS_0_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_dwidth_converter;
+
+class DllExport pl_eth_10g_auto_ds_0_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_ds_0_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_0_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_dwidth_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_ds_0_sc(const pl_eth_10g_auto_ds_0_sc&);
+  const pl_eth_10g_auto_ds_0_sc& operator=(const pl_eth_10g_auto_ds_0_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_DS_0_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_stub.sv
new file mode 100644
index 0000000..f249b0f
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/sim/pl_eth_10g_auto_ds_0_stub.sv
@@ -0,0 +1,314 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_ds_0_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_ds_0 (
+  input bit_as_bool s_axi_aclk,
+  input bit_as_bool s_axi_aresetn,
+  input bit [15 : 0] s_axi_awid,
+  input bit [39 : 0] s_axi_awaddr,
+  input bit [7 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [0 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awregion,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [127 : 0] s_axi_wdata,
+  input bit [15 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [15 : 0] s_axi_bid,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  input bit [15 : 0] s_axi_arid,
+  input bit [39 : 0] s_axi_araddr,
+  input bit [7 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [0 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arregion,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [15 : 0] s_axi_rid,
+  output bit [127 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  output bit [39 : 0] m_axi_awaddr,
+  output bit [7 : 0] m_axi_awlen,
+  output bit [2 : 0] m_axi_awsize,
+  output bit [1 : 0] m_axi_awburst,
+  output bit [0 : 0] m_axi_awlock,
+  output bit [3 : 0] m_axi_awcache,
+  output bit [2 : 0] m_axi_awprot,
+  output bit [3 : 0] m_axi_awregion,
+  output bit [3 : 0] m_axi_awqos,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [31 : 0] m_axi_wdata,
+  output bit [3 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wlast,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready,
+  output bit [39 : 0] m_axi_araddr,
+  output bit [7 : 0] m_axi_arlen,
+  output bit [2 : 0] m_axi_arsize,
+  output bit [1 : 0] m_axi_arburst,
+  output bit [0 : 0] m_axi_arlock,
+  output bit [3 : 0] m_axi_arcache,
+  output bit [2 : 0] m_axi_arprot,
+  output bit [3 : 0] m_axi_arregion,
+  output bit [3 : 0] m_axi_arqos,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [31 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rlast,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_ds_0 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [15 : 0] s_axi_awid;
+  input bit [39 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [127 : 0] s_axi_wdata;
+  input bit [15 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [15 : 0] s_axi_bid;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [15 : 0] s_axi_arid;
+  input bit [39 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [15 : 0] s_axi_rid;
+  output wire [127 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [39 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [39 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_ds_0 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [15 : 0] s_axi_awid;
+  input bit [39 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [127 : 0] s_axi_wdata;
+  input bit [15 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [15 : 0] s_axi_bid;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [15 : 0] s_axi_arid;
+  input bit [39 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [15 : 0] s_axi_rid;
+  output wire [127 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [39 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [39 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.cpp
new file mode 100644
index 0000000..16d5508
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.cpp
@@ -0,0 +1,527 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "axi_dwidth_converter.h"
+#define PAYLOAD_LOG_LEVEL 3
+
+axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
+		xsc::common_cpp::properties& m_properties) :
+		sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
+				nullptr),m_logger((std::string) (p_name)) {
+
+	initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"rd_trace_socket", 32);
+	initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"wr_trace_socket", 32);
+	target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
+			32);
+	target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
+			32);
+	rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
+			"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
+	wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
+			"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
+	target_rd_socket->bind(rd_target_util->rd_socket);
+	target_wr_socket->bind(wr_target_util->wr_socket);
+	rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
+	wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
+
+	mem_manager = new xtlm::xtlm_aximm_mem_manager();
+	SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
+	MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
+  FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
+
+
+	ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
+    if(FIFO_MODE!=2)
+  {
+    	m_axi_aclk(clk);
+			m_axi_aresetn(resetn);
+  }
+
+	SC_METHOD(wr_handler);
+	dont_initialize();
+	sensitive << wr_target_util->transaction_available;
+    sensitive << event_trig_wr_handler;
+
+	SC_METHOD(rd_handler);
+	dont_initialize();
+	sensitive << rd_target_util->addr_available;
+    sensitive << event_trig_rd_handler;
+
+	SC_METHOD(m_downsize_interface_txn_sender);
+	sensitive << event_downsize_trig_txn_sender;
+    sensitive << wr_initiator_util->transaction_sampled;
+    sensitive << rd_initiator_util->transaction_sampled;
+	dont_initialize();
+
+	SC_METHOD(m_upsize_interface_txn_sender);
+	sensitive << event_upsize_trig_txn_sender;
+	dont_initialize();
+
+	SC_METHOD(m_downsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+	SC_METHOD(m_upsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+}
+
+void axi_dwidth_converter::wr_handler() {
+    if(wr_initiator_util->is_slave_ready() && 
+            wr_target_util->is_trans_available() )
+    {
+        m_wr_trans = wr_target_util->get_transaction();
+        m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+        ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
+        if (ratio <= 1)
+            wr_upsizing();
+        else
+            wr_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_handler() {
+    if(rd_initiator_util->is_slave_ready() &&
+            rd_target_util->is_trans_available() )
+    {
+	    m_rd_trans = rd_target_util->get_transaction();
+        
+        m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+	    
+        ratio = m_rd_trans->get_burst_size()  / MI_DATA_WIDTH;
+	    if (ratio <= 1)
+	    	rd_upsizing();
+	    else
+	    	rd_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_downsizing() {
+	auto beat_l = m_rd_trans->get_burst_length();
+	auto data = m_rd_trans->get_data_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto s_addr = m_rd_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    m_response_list = new std::list<xtlm::aximm_payload*>;
+	do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_rd_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_size(MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
+		m_interface_rd_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+        
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+	m_response_mapper_downsize[m_rd_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::wr_downsizing() {
+	auto beat_l = m_wr_trans->get_burst_length();
+	auto data = m_wr_trans->get_data_ptr();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto s_addr = m_wr_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+	m_response_list = new std::list<xtlm::aximm_payload*>;
+    
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_wr_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH );
+		t_trans->set_burst_size(MI_DATA_WIDTH );
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
+		m_interface_wr_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+
+	m_response_mapper_downsize[m_wr_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_downsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_interface_wr_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_interface_wr_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(
+				*m_interface_wr_payload_queue.front(), zero_delay);
+		m_interface_wr_payload_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_interface_rd_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_interface_rd_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(
+				*m_interface_rd_payload_queue.front(), zero_delay);
+		m_interface_rd_payload_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_downsize_interface_response_sender() {
+	if (ratio <= 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Write : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    wr_target_util->send_resp(*(itr->first), zero_delay);
+					delete (itr->second);
+					m_response_mapper_downsize.erase(itr);
+                    event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+					break;
+				}
+				response_payld->release();
+			}
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Read : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    rd_target_util->send_data(*(itr->first), zero_delay);
+					delete (itr->second);
+                    event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+					m_response_mapper_downsize.erase(itr);
+					break;
+				}
+				//Release the transaction to memory manager
+				response_payld->release();
+			}
+		}
+	}
+}
+void axi_dwidth_converter::wr_upsizing() {
+	auto si_addr = m_wr_trans->get_address();
+	auto si_burst_len = m_wr_trans->get_burst_length();
+	auto si_burst_size = m_wr_trans->get_burst_size();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto data = m_wr_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_wr_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH );
+	t_trans->set_burst_length(mi_len);
+	m_upsize_wr_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_wr_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+
+}
+void axi_dwidth_converter::rd_upsizing() {
+	auto si_addr = m_rd_trans->get_address();
+	auto si_burst_len = m_rd_trans->get_burst_length();
+	auto si_burst_size = m_rd_trans->get_burst_size();
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto data = m_rd_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_rd_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH);
+	t_trans->set_burst_length(mi_len);
+	m_upsize_rd_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_rd_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_upsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_upsize_wr_payld_queue.size() != 0)) {
+        
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_upsize_wr_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
+				zero_delay);
+		m_upsize_wr_payld_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_upsize_rd_payld_queue.size() != 0)) {
+
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_upsize_rd_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
+				zero_delay);
+		m_upsize_rd_payld_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_upsize_interface_response_sender() {
+	if (ratio > 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = (m_response_mapper_upsize.find(response_payld));
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Write : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = m_response_mapper_upsize.find(response_payld);
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Read : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+            
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+}
+
+axi_dwidth_converter::~axi_dwidth_converter() {
+	delete mem_manager;
+	delete target_rd_socket;
+	delete target_wr_socket;
+	delete initiator_rd_socket;
+	delete initiator_wr_socket;
+	delete rd_target_util;
+	delete wr_target_util;
+	delete wr_initiator_util;
+	delete rd_initiator_util;
+	delete m_rd_trans;
+	delete m_wr_trans;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.h
new file mode 100644
index 0000000..35ad79d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/src/axi_dwidth_converter.h
@@ -0,0 +1,116 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#ifndef _AXI_DWIDTH_CONVERTER_H_
+#define _AXI_DWIDTH_CONVERTER_H_
+
+#include "xtlm.h"
+#include "report_handler.h"
+
+class axi_dwidth_converter: public sc_core::sc_module {
+public:
+    SC_HAS_PROCESS(axi_dwidth_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+	sc_core::sc_in<bool> s_axi_aclk;
+	sc_core::sc_in<bool> s_axi_aresetn;
+  sc_core::sc_in<bool> m_axi_aclk;
+	sc_core::sc_in<bool> m_axi_aresetn;
+  sc_core::sc_signal<bool> clk;
+	sc_core::sc_signal<bool> resetn;
+	axi_dwidth_converter(sc_core::sc_module_name p_name,
+				xsc::common_cpp::properties& m_properties);
+	xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
+    xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
+    xtlm::xtlm_aximm_mem_manager* mem_manager;
+    ~axi_dwidth_converter();
+    unsigned int SI_DATA_WIDTH;
+    unsigned int MI_DATA_WIDTH;
+    unsigned int FIFO_MODE;
+    unsigned int ratio;
+
+    void wr_handler();
+    void rd_handler();
+    void wr_upsizing();
+    void wr_downsizing();
+    void rd_upsizing();
+    void rd_downsizing();
+
+    /**
+     * @brief Method to send transaction on master interface
+     */
+    void m_downsize_interface_txn_sender();
+    void m_upsize_interface_txn_sender();
+
+    void m_downsize_interface_response_sender();
+    void m_upsize_interface_response_sender();
+
+private:
+    xtlm::aximm_payload* m_rd_trans;
+    xtlm::aximm_payload* m_wr_trans;
+    std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
+    sc_core::sc_event event_downsize_trig_txn_sender;	//!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_trig_rd_handler;
+    sc_core::sc_event event_trig_wr_handler;
+    std::list<xtlm::aximm_payload* > *m_response_list;
+    std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
+    std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
+    xsc::common_cpp::report_handler m_logger;
+    std::string m_log_msg;
+};
+
+#endif /* _AXI_DWIDTH_CONVERTER_H_ */
+
+
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/synth/pl_eth_10g_auto_ds_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/synth/pl_eth_10g_auto_ds_0.v
new file mode 100644
index 0000000..a293de2
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/synth/pl_eth_10g_auto_ds_0.v
@@ -0,0 +1,393 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_ds_0,axi_dwidth_converter_v2_1_22_top,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_ds_0,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=16,C_SUPPORTS_ID=1,C_AXI_ADDR_WIDTH=40,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_B\
+EATS=256,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_ds_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [15 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [39 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [15 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [15 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [39 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [15 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [39 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [39 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(16),
+    .C_SUPPORTS_ID(1),
+    .C_AXI_ADDR_WIDTH(40),
+    .C_S_AXI_DATA_WIDTH(128),
+    .C_M_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(256),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml
new file mode 100644
index 0000000..6092a06
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml
@@ -0,0 +1,4382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_ds_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
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+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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+          <spirit:vendorExtensions>
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+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+          <spirit:vendorExtensions>
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+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
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+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
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+      <spirit:displayName>SI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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+            <spirit:name>s_axi_aclk</spirit:name>
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+          <spirit:displayName>s_axi_aclk frequency</spirit:displayName>
+          <spirit:description>s_axi_aclk frequency</spirit:description>
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+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
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+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
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+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
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+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.INSERT_VIP">0</spirit:value>
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+      <spirit:displayName>MI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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+            <spirit:name>m_axi_aclk</spirit:name>
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+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>m_axi_aclk frequency</spirit:displayName>
+          <spirit:description>m_axi_aclk frequency</spirit:description>
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+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
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+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET"/>
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+          <spirit:name>INSERT_VIP</spirit:name>
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+      <spirit:displayName>SI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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+            <spirit:name>s_axi_aresetn</spirit:name>
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+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.POLARITY">ACTIVE_LOW</spirit:value>
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+          <spirit:name>INSERT_VIP</spirit:name>
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+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:name>MI_RST</spirit:name>
+      <spirit:displayName>MI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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+            <spirit:name>m_axi_aresetn</spirit:name>
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+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_RST.POLARITY">ACTIVE_LOW</spirit:value>
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+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_RST.INSERT_VIP">0</spirit:value>
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+          <spirit:physicalPort>
+            <spirit:name>target_wr_socket</spirit:name>
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+            <spirit:name>initiator_rd_socket</spirit:name>
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+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>initiator_wr_socket</spirit:name>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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+            <spirit:right spirit:format="long">0</spirit:right>
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+              <spirit:typeName>wire</spirit:typeName>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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+        <spirit:name>m_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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+        <spirit:name>target_wr_socket</spirit:name>
+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+                <spirit:typeName>tlm</spirit:typeName>
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+        <spirit:name>target_rd_socket</spirit:name>
+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
+        <spirit:transactional>
+          <spirit:transTypeDef>
+            <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
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+            <spirit:typeName>xtlm::xtlm_aximm_initiator_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+        <spirit:name>initiator_rd_socket</spirit:name>
+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
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+            <spirit:typeName>xtlm::xtlm_aximm_initiator_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+      <spirit:displayName>PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROTOCOL" spirit:choiceRef="choice_list_7235ff92" spirit:order="2">AXI4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_WRITE_MODE</spirit:name>
+      <spirit:displayName>READ_WRITE Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.READ_WRITE_MODE" spirit:choiceRef="choice_pairs_940700f2" spirit:order="3">READ_WRITE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH" spirit:order="4" spirit:minimum="12" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PACKING_LEVEL</spirit:name>
+      <spirit:displayName>Packing Level</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PACKING_LEVEL" spirit:choiceRef="choice_pairs_fe99fc86" spirit:order="5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>SI Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="6">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>MI Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MI_DATA_WIDTH" spirit:choiceRef="choice_list_151d8f4e" spirit:order="7">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SI_ID_WIDTH</spirit:name>
+      <spirit:displayName>SI ID Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SI_ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MAX_SPLIT_BEATS</spirit:name>
+      <spirit:displayName>Max Burst Length When Downsizing</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_SPLIT_BEATS" spirit:choiceRef="choice_list_0051c444" spirit:order="9">256</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_MODE</spirit:name>
+      <spirit:displayName>Upsizer FIFO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_MODE" spirit:choiceRef="choice_pairs_a4d18bae" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_ASYNC</spirit:name>
+      <spirit:displayName>Is ACLK Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_ASYNC" spirit:choiceRef="choice_pairs_37189c7b" spirit:order="11">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYNCHRONIZATION_STAGES</spirit:name>
+      <spirit:displayName>Synchronization Stages</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYNCHRONIZATION_STAGES" spirit:order="12" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_RATIO</spirit:name>
+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_RATIO" spirit:choiceRef="choice_list_42702293" spirit:order="1635284">1:2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pl_eth_10g_auto_ds_1</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI Data Width Converter</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:systemCLibraries>
+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
+      </xilinx:systemCLibraries>
+      <xilinx:coreRevision>22</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_ASYNC" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d6eff22"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3617c7e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="27eb12c9"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ec085b51"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="0a01a2fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_clocks.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_clocks.xdc
new file mode 100644
index 0000000..7cd225a
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_clocks.xdc
@@ -0,0 +1,7 @@
+###############################################################################################################
+# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_ds_1"
+###############################################################################################################
+#
+# This component is not configured to perform asynchronous clock-domain-crossing.
+# No timing core-level constraints are needed.
+# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_ooc.xdc
new file mode 100644
index 0000000..5d033a7
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_ooc.xdc
@@ -0,0 +1,49 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.cpp
new file mode 100644
index 0000000..a62ce97
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.cpp
@@ -0,0 +1,1242 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_ds_1_sc.h"
+
+#include "pl_eth_10g_auto_ds_1.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_ds_1::pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_ds_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWID(s_axi_awid);
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BID(s_axi_bid);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARID(s_axi_arid);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RID(s_axi_rid);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_ds_1::pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_ds_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWID(s_axi_awid);
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BID(s_axi_bid);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARID(s_axi_arid);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RID(s_axi_rid);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_ds_1::pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_ds_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWID(s_axi_awid);
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BID(s_axi_bid);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARID(s_axi_arid);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RID(s_axi_rid);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_ds_1::pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_1_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWID(s_axi_awid);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BID(s_axi_bid);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARID(s_axi_arid);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RID(s_axi_rid);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_ds_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_ds_1::pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_ds_1_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "16");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWID(s_axi_awid);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BID(s_axi_bid);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARID(s_axi_arid);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RID(s_axi_rid);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_ds_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_ds_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_ds_1::~pl_eth_10g_auto_ds_1()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_awlock_converter;
+  delete mp_s_axi_arlock_converter;
+
+  delete mp_M_AXI_transactor;
+  delete mp_m_axi_awlock_converter;
+  delete mp_m_axi_arlock_converter;
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_ds_1);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_ds_1);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_ds_1);
+SC_REGISTER_BV(128);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.h
new file mode 100644
index 0000000..5369cf5
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.h
@@ -0,0 +1,668 @@
+#ifndef IP_PL_ETH_10G_AUTO_DS_1_H_
+#define IP_PL_ETH_10G_AUTO_DS_1_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_ds_1_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
+{
+public:
+
+  pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
+  sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_DS_1_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.v
new file mode 100644
index 0000000..59faf92
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1.v
@@ -0,0 +1,391 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_ds_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [15 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [15 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [15 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [15 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(16),
+    .C_SUPPORTS_ID(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(128),
+    .C_M_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(256),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_sc.cpp
new file mode 100644
index 0000000..872aba8
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_sc.cpp
@@ -0,0 +1,96 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_ds_1_sc.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_ds_1_sc::pl_eth_10g_auto_ds_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_ds_1", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_S_AXI_ID_WIDTH", "16");
+    model_param_props.addLong("C_SUPPORTS_ID", "1");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
+    model_param_props.addLong("C_S_AXI_DATA_WIDTH", "128");
+    model_param_props.addLong("C_M_AXI_DATA_WIDTH", "32");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
+    model_param_props.addLong("C_FIFO_MODE", "0");
+    model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
+    model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
+    model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
+    model_param_props.addLong("C_MAX_SPLIT_BEATS", "256");
+    model_param_props.addLong("C_PACKING_LEVEL", "1");
+    model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_dwidth_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  target_rd_socket = mp_impl->target_rd_socket;
+  target_wr_socket = mp_impl->target_wr_socket;
+  initiator_rd_socket = mp_impl->initiator_rd_socket;
+  initiator_wr_socket = mp_impl->initiator_wr_socket;
+}
+
+pl_eth_10g_auto_ds_1_sc::~pl_eth_10g_auto_ds_1_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_sc.h
new file mode 100644
index 0000000..a290a38
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_DS_1_SC_H_
+#define IP_PL_ETH_10G_AUTO_DS_1_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_dwidth_converter;
+
+class DllExport pl_eth_10g_auto_ds_1_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_ds_1_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_ds_1_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_dwidth_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_ds_1_sc(const pl_eth_10g_auto_ds_1_sc&);
+  const pl_eth_10g_auto_ds_1_sc& operator=(const pl_eth_10g_auto_ds_1_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_DS_1_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_stub.sv
new file mode 100644
index 0000000..59506aa
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/sim/pl_eth_10g_auto_ds_1_stub.sv
@@ -0,0 +1,314 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_ds_1_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_ds_1 (
+  input bit_as_bool s_axi_aclk,
+  input bit_as_bool s_axi_aresetn,
+  input bit [15 : 0] s_axi_awid,
+  input bit [31 : 0] s_axi_awaddr,
+  input bit [7 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [0 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awregion,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [127 : 0] s_axi_wdata,
+  input bit [15 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [15 : 0] s_axi_bid,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  input bit [15 : 0] s_axi_arid,
+  input bit [31 : 0] s_axi_araddr,
+  input bit [7 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [0 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arregion,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [15 : 0] s_axi_rid,
+  output bit [127 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  output bit [31 : 0] m_axi_awaddr,
+  output bit [7 : 0] m_axi_awlen,
+  output bit [2 : 0] m_axi_awsize,
+  output bit [1 : 0] m_axi_awburst,
+  output bit [0 : 0] m_axi_awlock,
+  output bit [3 : 0] m_axi_awcache,
+  output bit [2 : 0] m_axi_awprot,
+  output bit [3 : 0] m_axi_awregion,
+  output bit [3 : 0] m_axi_awqos,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [31 : 0] m_axi_wdata,
+  output bit [3 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wlast,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready,
+  output bit [31 : 0] m_axi_araddr,
+  output bit [7 : 0] m_axi_arlen,
+  output bit [2 : 0] m_axi_arsize,
+  output bit [1 : 0] m_axi_arburst,
+  output bit [0 : 0] m_axi_arlock,
+  output bit [3 : 0] m_axi_arcache,
+  output bit [2 : 0] m_axi_arprot,
+  output bit [3 : 0] m_axi_arregion,
+  output bit [3 : 0] m_axi_arqos,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [31 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rlast,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_ds_1 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [15 : 0] s_axi_awid;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [127 : 0] s_axi_wdata;
+  input bit [15 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [15 : 0] s_axi_bid;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [15 : 0] s_axi_arid;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [15 : 0] s_axi_rid;
+  output wire [127 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_ds_1 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [15 : 0] s_axi_awid;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [127 : 0] s_axi_wdata;
+  input bit [15 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [15 : 0] s_axi_bid;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [15 : 0] s_axi_arid;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [15 : 0] s_axi_rid;
+  output wire [127 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.cpp
new file mode 100644
index 0000000..16d5508
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.cpp
@@ -0,0 +1,527 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "axi_dwidth_converter.h"
+#define PAYLOAD_LOG_LEVEL 3
+
+axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
+		xsc::common_cpp::properties& m_properties) :
+		sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
+				nullptr),m_logger((std::string) (p_name)) {
+
+	initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"rd_trace_socket", 32);
+	initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"wr_trace_socket", 32);
+	target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
+			32);
+	target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
+			32);
+	rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
+			"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
+	wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
+			"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
+	target_rd_socket->bind(rd_target_util->rd_socket);
+	target_wr_socket->bind(wr_target_util->wr_socket);
+	rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
+	wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
+
+	mem_manager = new xtlm::xtlm_aximm_mem_manager();
+	SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
+	MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
+  FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
+
+
+	ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
+    if(FIFO_MODE!=2)
+  {
+    	m_axi_aclk(clk);
+			m_axi_aresetn(resetn);
+  }
+
+	SC_METHOD(wr_handler);
+	dont_initialize();
+	sensitive << wr_target_util->transaction_available;
+    sensitive << event_trig_wr_handler;
+
+	SC_METHOD(rd_handler);
+	dont_initialize();
+	sensitive << rd_target_util->addr_available;
+    sensitive << event_trig_rd_handler;
+
+	SC_METHOD(m_downsize_interface_txn_sender);
+	sensitive << event_downsize_trig_txn_sender;
+    sensitive << wr_initiator_util->transaction_sampled;
+    sensitive << rd_initiator_util->transaction_sampled;
+	dont_initialize();
+
+	SC_METHOD(m_upsize_interface_txn_sender);
+	sensitive << event_upsize_trig_txn_sender;
+	dont_initialize();
+
+	SC_METHOD(m_downsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+	SC_METHOD(m_upsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+}
+
+void axi_dwidth_converter::wr_handler() {
+    if(wr_initiator_util->is_slave_ready() && 
+            wr_target_util->is_trans_available() )
+    {
+        m_wr_trans = wr_target_util->get_transaction();
+        m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+        ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
+        if (ratio <= 1)
+            wr_upsizing();
+        else
+            wr_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_handler() {
+    if(rd_initiator_util->is_slave_ready() &&
+            rd_target_util->is_trans_available() )
+    {
+	    m_rd_trans = rd_target_util->get_transaction();
+        
+        m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+	    
+        ratio = m_rd_trans->get_burst_size()  / MI_DATA_WIDTH;
+	    if (ratio <= 1)
+	    	rd_upsizing();
+	    else
+	    	rd_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_downsizing() {
+	auto beat_l = m_rd_trans->get_burst_length();
+	auto data = m_rd_trans->get_data_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto s_addr = m_rd_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    m_response_list = new std::list<xtlm::aximm_payload*>;
+	do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_rd_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_size(MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
+		m_interface_rd_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+        
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+	m_response_mapper_downsize[m_rd_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::wr_downsizing() {
+	auto beat_l = m_wr_trans->get_burst_length();
+	auto data = m_wr_trans->get_data_ptr();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto s_addr = m_wr_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+	m_response_list = new std::list<xtlm::aximm_payload*>;
+    
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_wr_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH );
+		t_trans->set_burst_size(MI_DATA_WIDTH );
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
+		m_interface_wr_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+
+	m_response_mapper_downsize[m_wr_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_downsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_interface_wr_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_interface_wr_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(
+				*m_interface_wr_payload_queue.front(), zero_delay);
+		m_interface_wr_payload_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_interface_rd_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_interface_rd_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(
+				*m_interface_rd_payload_queue.front(), zero_delay);
+		m_interface_rd_payload_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_downsize_interface_response_sender() {
+	if (ratio <= 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Write : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    wr_target_util->send_resp(*(itr->first), zero_delay);
+					delete (itr->second);
+					m_response_mapper_downsize.erase(itr);
+                    event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+					break;
+				}
+				response_payld->release();
+			}
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Read : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    rd_target_util->send_data(*(itr->first), zero_delay);
+					delete (itr->second);
+                    event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+					m_response_mapper_downsize.erase(itr);
+					break;
+				}
+				//Release the transaction to memory manager
+				response_payld->release();
+			}
+		}
+	}
+}
+void axi_dwidth_converter::wr_upsizing() {
+	auto si_addr = m_wr_trans->get_address();
+	auto si_burst_len = m_wr_trans->get_burst_length();
+	auto si_burst_size = m_wr_trans->get_burst_size();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto data = m_wr_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_wr_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH );
+	t_trans->set_burst_length(mi_len);
+	m_upsize_wr_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_wr_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+
+}
+void axi_dwidth_converter::rd_upsizing() {
+	auto si_addr = m_rd_trans->get_address();
+	auto si_burst_len = m_rd_trans->get_burst_length();
+	auto si_burst_size = m_rd_trans->get_burst_size();
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto data = m_rd_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_rd_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH);
+	t_trans->set_burst_length(mi_len);
+	m_upsize_rd_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_rd_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_upsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_upsize_wr_payld_queue.size() != 0)) {
+        
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_upsize_wr_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
+				zero_delay);
+		m_upsize_wr_payld_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_upsize_rd_payld_queue.size() != 0)) {
+
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_upsize_rd_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
+				zero_delay);
+		m_upsize_rd_payld_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_upsize_interface_response_sender() {
+	if (ratio > 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = (m_response_mapper_upsize.find(response_payld));
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Write : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = m_response_mapper_upsize.find(response_payld);
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Read : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+            
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+}
+
+axi_dwidth_converter::~axi_dwidth_converter() {
+	delete mem_manager;
+	delete target_rd_socket;
+	delete target_wr_socket;
+	delete initiator_rd_socket;
+	delete initiator_wr_socket;
+	delete rd_target_util;
+	delete wr_target_util;
+	delete wr_initiator_util;
+	delete rd_initiator_util;
+	delete m_rd_trans;
+	delete m_wr_trans;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.h
new file mode 100644
index 0000000..35ad79d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/src/axi_dwidth_converter.h
@@ -0,0 +1,116 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#ifndef _AXI_DWIDTH_CONVERTER_H_
+#define _AXI_DWIDTH_CONVERTER_H_
+
+#include "xtlm.h"
+#include "report_handler.h"
+
+class axi_dwidth_converter: public sc_core::sc_module {
+public:
+    SC_HAS_PROCESS(axi_dwidth_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+	sc_core::sc_in<bool> s_axi_aclk;
+	sc_core::sc_in<bool> s_axi_aresetn;
+  sc_core::sc_in<bool> m_axi_aclk;
+	sc_core::sc_in<bool> m_axi_aresetn;
+  sc_core::sc_signal<bool> clk;
+	sc_core::sc_signal<bool> resetn;
+	axi_dwidth_converter(sc_core::sc_module_name p_name,
+				xsc::common_cpp::properties& m_properties);
+	xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
+    xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
+    xtlm::xtlm_aximm_mem_manager* mem_manager;
+    ~axi_dwidth_converter();
+    unsigned int SI_DATA_WIDTH;
+    unsigned int MI_DATA_WIDTH;
+    unsigned int FIFO_MODE;
+    unsigned int ratio;
+
+    void wr_handler();
+    void rd_handler();
+    void wr_upsizing();
+    void wr_downsizing();
+    void rd_upsizing();
+    void rd_downsizing();
+
+    /**
+     * @brief Method to send transaction on master interface
+     */
+    void m_downsize_interface_txn_sender();
+    void m_upsize_interface_txn_sender();
+
+    void m_downsize_interface_response_sender();
+    void m_upsize_interface_response_sender();
+
+private:
+    xtlm::aximm_payload* m_rd_trans;
+    xtlm::aximm_payload* m_wr_trans;
+    std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
+    sc_core::sc_event event_downsize_trig_txn_sender;	//!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_trig_rd_handler;
+    sc_core::sc_event event_trig_wr_handler;
+    std::list<xtlm::aximm_payload* > *m_response_list;
+    std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
+    std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
+    xsc::common_cpp::report_handler m_logger;
+    std::string m_log_msg;
+};
+
+#endif /* _AXI_DWIDTH_CONVERTER_H_ */
+
+
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/synth/pl_eth_10g_auto_ds_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/synth/pl_eth_10g_auto_ds_1.v
new file mode 100644
index 0000000..9eea21c
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/synth/pl_eth_10g_auto_ds_1.v
@@ -0,0 +1,393 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_ds_1,axi_dwidth_converter_v2_1_22_top,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_ds_1,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=16,C_SUPPORTS_ID=1,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_B\
+EATS=256,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_ds_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
+input wire [15 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [127 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [15 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
+output wire [15 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
+input wire [15 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
+output wire [15 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [127 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(16),
+    .C_SUPPORTS_ID(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(128),
+    .C_M_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(256),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml
new file mode 100644
index 0000000..f6f3174
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml
@@ -0,0 +1,4557 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_pc_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">40</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">40</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
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+          <spirit:vendorExtensions>
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+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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+          <spirit:physicalPort>
+            <spirit:name>aclk</spirit:name>
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+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>aclk frequency</spirit:displayName>
+          <spirit:description>aclk frequency</spirit:description>
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+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
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+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
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+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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+      <spirit:displayName>RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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+            <spirit:name>RST</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>aresetn</spirit:name>
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+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_rd_socket</spirit:name>
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+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_wr_socket</spirit:name>
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+        </spirit:portMap>
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+      <spirit:name>M_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
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+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>initiator_rd_socket</spirit:name>
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+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
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+          <spirit:physicalPort>
+            <spirit:name>initiator_wr_socket</spirit:name>
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+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>axi_protocol_converter_v2_1_22_axi_protocol_converter</spirit:modelName>
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+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
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+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
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+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
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+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
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+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
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+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:34f28976</spirit:value>
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+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
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+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:34f28976</spirit:value>
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+        <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
+        <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>pl_eth_10g_auto_pc_0</spirit:modelName>
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+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
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+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:34f28976</spirit:value>
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+      <spirit:view>
+        <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+        <spirit:displayName>Verilog Simulation</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>axi_protocol_converter_v2_1_22_axi_protocol_converter</spirit:modelName>
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+            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
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+            <spirit:name>outputProductCRC</spirit:name>
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+        <spirit:language>systemc</spirit:language>
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+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
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+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:226447ff</spirit:value>
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+            <spirit:value>tlm</spirit:value>
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+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
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+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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+        <spirit:name>s_axi_awid</spirit:name>
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+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>axi_register_slice_v2_1_22</spirit:logicalName>
+      </spirit:file>
+      <spirit:vendorExtensions>
+        <xilinx:subCoreRef>
+          <xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_register_slice" xilinx:version="2.1" xilinx:isGenerated="true" xilinx:checksum="1500423a">
+            <xilinx:mode xilinx:name="copy_mode"/>
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+        </xilinx:subCoreRef>
+      </spirit:vendorExtensions>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../../ipshared/5cee/hdl/axi_protocol_converter_v2_1_vl_rfs.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:logicalName>axi_protocol_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/axi_protocol_converter.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:logicalName>axi_protocol_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/axi_protocol_converter.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>axi_protocol_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_pc_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_pc_0_sc.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_pc_0_sc.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_pc_0.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_pc_0.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_pc_0_stub.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>The AXI Protocol Converter IP provides the facility to change the protocol of the connection between an AXI4/AXI3/AXI4-Lite master and slave. It will convert between AXI4->AXI3/AXI4-Lite, AXI3->AXI4/AXI4-Lite, AXI4-Lite->AXI4/AXI3.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>SI_PROTOCOL</spirit:name>
+      <spirit:displayName>SI PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SI_PROTOCOL" spirit:choiceRef="choice_list_7235ff92" spirit:order="2">AXI4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MI_PROTOCOL</spirit:name>
+      <spirit:displayName>MI PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MI_PROTOCOL" spirit:choiceRef="choice_list_a4e480ed" spirit:order="3">AXI4LITE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_WRITE_MODE</spirit:name>
+      <spirit:displayName>READ_WRITE Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.READ_WRITE_MODE" spirit:choiceRef="choice_pairs_940700f2" spirit:order="4">READ_WRITE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TRANSLATION_MODE</spirit:name>
+      <spirit:displayName>Translation Mode</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TRANSLATION_MODE" spirit:choiceRef="choice_pairs_fc76701f" spirit:order="5">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH" spirit:order="6" spirit:minimum="12" spirit:maximum="64" spirit:rangeType="long">40</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:choiceRef="choice_list_99ba8646" spirit:order="7">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ID_WIDTH</spirit:name>
+      <spirit:displayName>ID Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AWUSER_WIDTH" spirit:order="9" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ARUSER_WIDTH" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RUSER_WIDTH" spirit:order="11" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WUSER_WIDTH" spirit:order="12" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUSER_WIDTH" spirit:order="13" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pl_eth_10g_auto_pc_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI Protocol Converter</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:systemCLibraries>
+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
+      </xilinx:systemCLibraries>
+      <xilinx:coreRevision>22</xilinx:coreRevision>
+      <xilinx:configElementInfos>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8bf55e5d"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="16899ba7"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="407fc740"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c4684b29"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="9c81bfcc"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0_ooc.xdc
new file mode 100644
index 0000000..e76084b
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0_ooc.xdc
@@ -0,0 +1,50 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports aclk]
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.cpp
new file mode 100644
index 0000000..0a04622
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.cpp
@@ -0,0 +1,1090 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_pc_0_sc.h"
+
+#include "pl_eth_10g_auto_pc_0.h"
+
+#include "axi_protocol_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_pc_0::pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_pc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(aclk);
+    mp_S_AXI_transactor->RST(aresetn);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(aclk);
+    mp_M_AXI_transactor->RST(aresetn);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_pc_0::pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_pc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(aclk);
+    mp_S_AXI_transactor->RST(aresetn);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(aclk);
+    mp_M_AXI_transactor->RST(aresetn);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_pc_0::pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_pc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(aclk);
+    mp_S_AXI_transactor->RST(aresetn);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(aclk);
+    mp_M_AXI_transactor->RST(aresetn);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_pc_0::pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_0_sc(nm),  aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(aclk);
+  mp_S_AXI_transactor->RST(aresetn);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(aclk);
+  mp_M_AXI_transactor->RST(aresetn);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_pc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_pc_0::pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_0_sc(nm),  aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(aclk);
+  mp_S_AXI_transactor->RST(aresetn);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "40");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(aclk);
+  mp_M_AXI_transactor->RST(aresetn);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_pc_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_pc_0::~pl_eth_10g_auto_pc_0()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_awlock_converter;
+  delete mp_s_axi_arlock_converter;
+
+  delete mp_M_AXI_transactor;
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_pc_0);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_pc_0);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_pc_0);
+SC_REGISTER_BV(40);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.h
new file mode 100644
index 0000000..b2eb269
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.h
@@ -0,0 +1,538 @@
+#ifndef IP_PL_ETH_10G_AUTO_PC_0_H_
+#define IP_PL_ETH_10G_AUTO_PC_0_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_pc_0_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_PC_0_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.v
new file mode 100644
index 0000000..2dfcc39
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0.v
@@ -0,0 +1,345 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_pc_0 (
+  aclk,
+  aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [39 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [39 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [39 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [39 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_22_axi_protocol_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(0),
+    .C_IGNORE_ID(1),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(40),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_sc.cpp
new file mode 100644
index 0000000..065ecfb
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_sc.cpp
@@ -0,0 +1,96 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_pc_0_sc.h"
+
+#include "axi_protocol_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_pc_0_sc::pl_eth_10g_auto_pc_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_pc_0", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_M_AXI_PROTOCOL", "2");
+    model_param_props.addLong("C_S_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_IGNORE_ID", "1");
+    model_param_props.addLong("C_AXI_ID_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "40");
+    model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
+    model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
+    model_param_props.addLong("C_TRANSLATION_MODE", "2");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_protocol_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  target_rd_socket = mp_impl->target_rd_socket;
+  target_wr_socket = mp_impl->target_wr_socket;
+  initiator_rd_socket = mp_impl->initiator_rd_socket;
+  initiator_wr_socket = mp_impl->initiator_wr_socket;
+}
+
+pl_eth_10g_auto_pc_0_sc::~pl_eth_10g_auto_pc_0_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_sc.h
new file mode 100644
index 0000000..20c3811
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_PC_0_SC_H_
+#define IP_PL_ETH_10G_AUTO_PC_0_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_protocol_converter;
+
+class DllExport pl_eth_10g_auto_pc_0_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_pc_0_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_0_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_protocol_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_pc_0_sc(const pl_eth_10g_auto_pc_0_sc&);
+  const pl_eth_10g_auto_pc_0_sc& operator=(const pl_eth_10g_auto_pc_0_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_PC_0_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_stub.sv
new file mode 100644
index 0000000..b5e1d7e
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/sim/pl_eth_10g_auto_pc_0_stub.sv
@@ -0,0 +1,254 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_pc_0_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_pc_0 (
+  input bit_as_bool aclk,
+  input bit_as_bool aresetn,
+  input bit [39 : 0] s_axi_awaddr,
+  input bit [7 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [0 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awregion,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [31 : 0] s_axi_wdata,
+  input bit [3 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  input bit [39 : 0] s_axi_araddr,
+  input bit [7 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [0 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arregion,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [31 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  output bit [39 : 0] m_axi_awaddr,
+  output bit [2 : 0] m_axi_awprot,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [31 : 0] m_axi_wdata,
+  output bit [3 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready,
+  output bit [39 : 0] m_axi_araddr,
+  output bit [2 : 0] m_axi_arprot,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [31 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_pc_0 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit aclk;
+  input bit aresetn;
+  input bit [39 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [31 : 0] s_axi_wdata;
+  input bit [3 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [39 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [31 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [39 : 0] m_axi_awaddr;
+  output wire [2 : 0] m_axi_awprot;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [39 : 0] m_axi_araddr;
+  output wire [2 : 0] m_axi_arprot;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_pc_0 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
+  input bit aclk;
+  input bit aresetn;
+  input bit [39 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [31 : 0] s_axi_wdata;
+  input bit [3 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [39 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [31 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [39 : 0] m_axi_awaddr;
+  output wire [2 : 0] m_axi_awprot;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [39 : 0] m_axi_araddr;
+  output wire [2 : 0] m_axi_arprot;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/src/axi_protocol_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/src/axi_protocol_converter.cpp
new file mode 100644
index 0000000..8fdcd9f
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/src/axi_protocol_converter.cpp
@@ -0,0 +1,25 @@
+#include "axi_protocol_converter.h"
+#include <sstream>
+
+axi_protocol_converter::axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
+	sc_module(module_name) {
+		initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
+		initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
+	 	target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
+		target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
+		P1 = new xtlm::xtlm_aximm_passthru_module("P1");
+		P2 = new xtlm::xtlm_aximm_passthru_module("P2");
+		P1->initiator_socket->bind(*initiator_rd_socket);
+		P2->initiator_socket->bind(*initiator_wr_socket);
+		target_rd_socket->bind(*(P1->target_socket));
+		target_wr_socket->bind(*(P2->target_socket));
+		}
+
+axi_protocol_converter::~axi_protocol_converter() {
+	delete initiator_wr_socket;
+	delete initiator_rd_socket;
+	delete target_wr_socket;
+	delete target_rd_socket;
+	delete P1;
+	delete P2;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/src/axi_protocol_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/src/axi_protocol_converter.h
new file mode 100644
index 0000000..3275533
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/src/axi_protocol_converter.h
@@ -0,0 +1,24 @@
+#ifndef _axi_protocol_converter_
+#define _axi_protocol_converter_
+#include <xtlm.h>
+#include <utils/xtlm_aximm_passthru_module.h>
+#include <systemc>
+
+class axi_protocol_converter:public sc_module{
+	public:
+		axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
+		virtual ~axi_protocol_converter();
+		SC_HAS_PROCESS(axi_protocol_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket*  initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+  	sc_in<bool> aclk;
+	sc_in<bool> aresetn;
+	private:
+	xtlm::xtlm_aximm_passthru_module *P1;
+	xtlm::xtlm_aximm_passthru_module *P2;	
+};
+
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/synth/pl_eth_10g_auto_pc_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/synth/pl_eth_10g_auto_pc_0.v
new file mode 100644
index 0000000..a9e5b97
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/synth/pl_eth_10g_auto_pc_0.v
@@ -0,0 +1,347 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 22
+
+(* X_CORE_INFO = "axi_protocol_converter_v2_1_22_axi_protocol_converter,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_pc_0,axi_protocol_converter_v2_1_22_axi_protocol_converter,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_pc_0,axi_protocol_converter_v2_1_22_axi_protocol_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=40,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI\
+_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_pc_0 (
+  aclk,
+  aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [39 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [39 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [39 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [39 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_22_axi_protocol_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(0),
+    .C_IGNORE_ID(1),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(40),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml
new file mode 100644
index 0000000..f678364
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml
@@ -0,0 +1,4557 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_pc_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_buser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_ruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK</spirit:name>
+      <spirit:displayName>CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>aclk frequency</spirit:displayName>
+          <spirit:description>aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">124998749</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>RST</spirit:name>
+      <spirit:displayName>RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>initiator_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>initiator_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesis</spirit:name>
+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>axi_protocol_converter_v2_1_22_axi_protocol_converter</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f1bf5693</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f1bf5693</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
+        <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>pl_eth_10g_auto_pc_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:f1bf5693</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+        <spirit:displayName>Verilog Simulation</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>axi_protocol_converter_v2_1_22_axi_protocol_converter</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:acf4a4fd</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_systemcsimulation</spirit:name>
+        <spirit:displayName>SystemC Simulation</spirit:displayName>
+        <spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>systemc</spirit:language>
+        <spirit:modelName>axi_protocol_converter</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:7af77f67</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>sim_type</spirit:name>
+            <spirit:value>tlm</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>use_subcore_outputs</spirit:name>
+            <spirit:value>false</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
+        <spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>pl_eth_10g_auto_pc_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:acf4a4fd</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_systemcsimulationwrapper</spirit:name>
+        <spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>systemc</spirit:language>
+        <spirit:modelName>pl_eth_10g_auto_pc_1</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_systemcsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:7af77f67</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>sim_type</spirit:name>
+            <spirit:value>tlm</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>aclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
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+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
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+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
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+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
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+        <spirit:name>sim/pl_eth_10g_auto_pc_1_sc.cpp</spirit:name>
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+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_pc_1.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
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+        <spirit:name>sim/pl_eth_10g_auto_pc_1.cpp</spirit:name>
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+        <spirit:fileType>systemVerilogSource</spirit:fileType>
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+  </spirit:fileSets>
+  <spirit:description>The AXI Protocol Converter IP provides the facility to change the protocol of the connection between an AXI4/AXI3/AXI4-Lite master and slave. It will convert between AXI4->AXI3/AXI4-Lite, AXI3->AXI4/AXI4-Lite, AXI4-Lite->AXI4/AXI3.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>SI_PROTOCOL</spirit:name>
+      <spirit:displayName>SI PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SI_PROTOCOL" spirit:choiceRef="choice_list_7235ff92" spirit:order="2">AXI4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MI_PROTOCOL</spirit:name>
+      <spirit:displayName>MI PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MI_PROTOCOL" spirit:choiceRef="choice_list_a4e480ed" spirit:order="3">AXI4LITE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_WRITE_MODE</spirit:name>
+      <spirit:displayName>READ_WRITE Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.READ_WRITE_MODE" spirit:choiceRef="choice_pairs_940700f2" spirit:order="4">READ_WRITE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TRANSLATION_MODE</spirit:name>
+      <spirit:displayName>Translation Mode</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TRANSLATION_MODE" spirit:choiceRef="choice_pairs_fc76701f" spirit:order="5">2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH" spirit:order="6" spirit:minimum="12" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:choiceRef="choice_list_99ba8646" spirit:order="7">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ID_WIDTH</spirit:name>
+      <spirit:displayName>ID Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER_WIDTH</spirit:displayName>
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+      <spirit:name>ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ARUSER_WIDTH" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER_WIDTH</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER_WIDTH</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER_WIDTH</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUSER_WIDTH" spirit:order="13" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pl_eth_10g_auto_pc_1</spirit:value>
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+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI Protocol Converter</xilinx:displayName>
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+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
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+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
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+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8bf55e5d"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="16899ba7"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="407fc740"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c4684b29"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="9c81bfcc"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1_ooc.xdc
new file mode 100644
index 0000000..e76084b
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1_ooc.xdc
@@ -0,0 +1,50 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports aclk]
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.cpp
new file mode 100644
index 0000000..f6a3b03
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.cpp
@@ -0,0 +1,1089 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_pc_1_sc.h"
+
+#include "pl_eth_10g_auto_pc_1.h"
+
+#include "axi_protocol_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_pc_1::pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_pc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(aclk);
+    mp_S_AXI_transactor->RST(aresetn);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(aclk);
+    mp_M_AXI_transactor->RST(aresetn);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_pc_1::pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_pc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(aclk);
+    mp_S_AXI_transactor->RST(aresetn);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(aclk);
+    mp_M_AXI_transactor->RST(aresetn);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_pc_1::pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_pc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(aclk);
+    mp_S_AXI_transactor->RST(aresetn);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(aclk);
+    mp_M_AXI_transactor->RST(aresetn);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_pc_1::pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_1_sc(nm),  aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(aclk);
+  mp_S_AXI_transactor->RST(aresetn);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(aclk);
+  mp_M_AXI_transactor->RST(aresetn);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_pc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_pc_1::pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_pc_1_sc(nm),  aclk("aclk"), aresetn("aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->aclk(aclk);
+  mp_impl->aresetn(aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(aclk);
+  mp_S_AXI_transactor->RST(aresetn);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(aclk);
+  mp_M_AXI_transactor->RST(aresetn);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_pc_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_pc_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_pc_1::~pl_eth_10g_auto_pc_1()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_awlock_converter;
+  delete mp_s_axi_arlock_converter;
+
+  delete mp_M_AXI_transactor;
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_pc_1);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_pc_1);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_pc_1);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.h
new file mode 100644
index 0000000..e745e69
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.h
@@ -0,0 +1,538 @@
+#ifndef IP_PL_ETH_10G_AUTO_PC_1_H_
+#define IP_PL_ETH_10G_AUTO_PC_1_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_pc_1_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
+{
+public:
+
+  pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > aclk;
+  sc_core::sc_in< bool > aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_PC_1_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.v
new file mode 100644
index 0000000..a54adef
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1.v
@@ -0,0 +1,345 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_pc_1 (
+  aclk,
+  aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_22_axi_protocol_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(0),
+    .C_IGNORE_ID(1),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_sc.cpp
new file mode 100644
index 0000000..d8ffaa4
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_sc.cpp
@@ -0,0 +1,96 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_pc_1_sc.h"
+
+#include "axi_protocol_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_pc_1_sc::pl_eth_10g_auto_pc_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_pc_1", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_M_AXI_PROTOCOL", "2");
+    model_param_props.addLong("C_S_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_IGNORE_ID", "1");
+    model_param_props.addLong("C_AXI_ID_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
+    model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
+    model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
+    model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
+    model_param_props.addLong("C_TRANSLATION_MODE", "2");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_protocol_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  target_rd_socket = mp_impl->target_rd_socket;
+  target_wr_socket = mp_impl->target_wr_socket;
+  initiator_rd_socket = mp_impl->initiator_rd_socket;
+  initiator_wr_socket = mp_impl->initiator_wr_socket;
+}
+
+pl_eth_10g_auto_pc_1_sc::~pl_eth_10g_auto_pc_1_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_sc.h
new file mode 100644
index 0000000..7466090
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_PC_1_SC_H_
+#define IP_PL_ETH_10G_AUTO_PC_1_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_protocol_converter;
+
+class DllExport pl_eth_10g_auto_pc_1_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_pc_1_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_pc_1_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_protocol_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_pc_1_sc(const pl_eth_10g_auto_pc_1_sc&);
+  const pl_eth_10g_auto_pc_1_sc& operator=(const pl_eth_10g_auto_pc_1_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_PC_1_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_stub.sv
new file mode 100644
index 0000000..00f833f
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/sim/pl_eth_10g_auto_pc_1_stub.sv
@@ -0,0 +1,254 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_pc_1_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_pc_1 (
+  input bit_as_bool aclk,
+  input bit_as_bool aresetn,
+  input bit [31 : 0] s_axi_awaddr,
+  input bit [7 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [0 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awregion,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [31 : 0] s_axi_wdata,
+  input bit [3 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  input bit [31 : 0] s_axi_araddr,
+  input bit [7 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [0 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arregion,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [31 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  output bit [31 : 0] m_axi_awaddr,
+  output bit [2 : 0] m_axi_awprot,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [31 : 0] m_axi_wdata,
+  output bit [3 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready,
+  output bit [31 : 0] m_axi_araddr,
+  output bit [2 : 0] m_axi_arprot,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [31 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_pc_1 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit aclk;
+  input bit aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [31 : 0] s_axi_wdata;
+  input bit [3 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [31 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [2 : 0] m_axi_awprot;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [2 : 0] m_axi_arprot;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_pc_1 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
+  input bit aclk;
+  input bit aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [31 : 0] s_axi_wdata;
+  input bit [3 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [31 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [2 : 0] m_axi_awprot;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [31 : 0] m_axi_wdata;
+  output wire [3 : 0] m_axi_wstrb;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [2 : 0] m_axi_arprot;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [31 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/src/axi_protocol_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/src/axi_protocol_converter.cpp
new file mode 100644
index 0000000..8fdcd9f
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/src/axi_protocol_converter.cpp
@@ -0,0 +1,25 @@
+#include "axi_protocol_converter.h"
+#include <sstream>
+
+axi_protocol_converter::axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
+	sc_module(module_name) {
+		initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
+		initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
+	 	target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
+		target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
+		P1 = new xtlm::xtlm_aximm_passthru_module("P1");
+		P2 = new xtlm::xtlm_aximm_passthru_module("P2");
+		P1->initiator_socket->bind(*initiator_rd_socket);
+		P2->initiator_socket->bind(*initiator_wr_socket);
+		target_rd_socket->bind(*(P1->target_socket));
+		target_wr_socket->bind(*(P2->target_socket));
+		}
+
+axi_protocol_converter::~axi_protocol_converter() {
+	delete initiator_wr_socket;
+	delete initiator_rd_socket;
+	delete target_wr_socket;
+	delete target_rd_socket;
+	delete P1;
+	delete P2;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/src/axi_protocol_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/src/axi_protocol_converter.h
new file mode 100644
index 0000000..3275533
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/src/axi_protocol_converter.h
@@ -0,0 +1,24 @@
+#ifndef _axi_protocol_converter_
+#define _axi_protocol_converter_
+#include <xtlm.h>
+#include <utils/xtlm_aximm_passthru_module.h>
+#include <systemc>
+
+class axi_protocol_converter:public sc_module{
+	public:
+		axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
+		virtual ~axi_protocol_converter();
+		SC_HAS_PROCESS(axi_protocol_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket*  initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+  	sc_in<bool> aclk;
+	sc_in<bool> aresetn;
+	private:
+	xtlm::xtlm_aximm_passthru_module *P1;
+	xtlm::xtlm_aximm_passthru_module *P2;	
+};
+
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/synth/pl_eth_10g_auto_pc_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/synth/pl_eth_10g_auto_pc_1.v
new file mode 100644
index 0000000..c964074
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/synth/pl_eth_10g_auto_pc_1.v
@@ -0,0 +1,347 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 22
+
+(* X_CORE_INFO = "axi_protocol_converter_v2_1_22_axi_protocol_converter,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_pc_1,axi_protocol_converter_v2_1_22_axi_protocol_converter,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_pc_1,axi_protocol_converter_v2_1_22_axi_protocol_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI\
+_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_pc_1 (
+  aclk,
+  aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
+, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_22_axi_protocol_converter #(
+    .C_FAMILY("zynquplus"),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(0),
+    .C_IGNORE_ID(1),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(1'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(1'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1'H1),
+    .m_axi_ruser(1'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml
new file mode 100644
index 0000000..0977807
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml
@@ -0,0 +1,4382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_us_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_CLK</spirit:name>
+      <spirit:displayName>SI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>s_axi_aclk frequency</spirit:displayName>
+          <spirit:description>s_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">124998749</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_CLK</spirit:name>
+      <spirit:displayName>MI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>m_axi_aclk frequency</spirit:displayName>
+          <spirit:description>m_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">10000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MI_CLK" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 2) || (spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 4))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_RST</spirit:name>
+      <spirit:displayName>SI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_RST</spirit:name>
+      <spirit:displayName>MI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MI_RST" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 2) || (spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 4))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>target_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_TLM</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_tlm" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_READ_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>initiator_rd_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AXIMM_WRITE_SOCKET</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>initiator_wr_socket</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_verilogsynthesis</spirit:name>
+        <spirit:displayName>Verilog Synthesis</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>axi_dwidth_converter_v2_1_22_top</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_protocol_converter_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_clock_converter_2_1__ref_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:5327931b</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:5327931b</spirit:value>
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+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
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+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
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+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+        <spirit:displayName>AXIMM Write Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Write</spirit:description>
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+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+        <spirit:displayName>AXIMM Read Socket</spirit:displayName>
+        <spirit:description>AXIMM Socket for Read</spirit:description>
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+            <spirit:typeName>xtlm::xtlm_aximm_initiator_socket</spirit:typeName>
+            <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
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+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MAX_SPLIT_BEATS">16</spirit:value>
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+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PACKING_LEVEL">1</spirit:value>
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+      <spirit:file>
+        <spirit:name>src/axi_dwidth_converter.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:logicalName>axi_dwidth_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/axi_dwidth_converter.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>axi_dwidth_converter_v2_1_22</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_us_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_us_0_sc.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_us_0_sc.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_us_0.h</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_us_0.cpp</spirit:name>
+        <spirit:fileType>systemCSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>sim/pl_eth_10g_auto_us_0_stub.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>pl_eth_10g_auto_us_0_clocks.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:define>
+          <spirit:name>processing_order</spirit:name>
+          <spirit:value>late</spirit:value>
+        </spirit:define>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>The AXI Data Width Converter IP provides the facility to increase or decrease the data width of WDATA and RDATA between an AXI4/AXI3/AXI4-Lite master and slave.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>PROTOCOL</spirit:name>
+      <spirit:displayName>PROTOCOL</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROTOCOL" spirit:choiceRef="choice_list_7235ff92" spirit:order="2">AXI4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>READ_WRITE_MODE</spirit:name>
+      <spirit:displayName>READ_WRITE Mode</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.READ_WRITE_MODE" spirit:choiceRef="choice_pairs_940700f2" spirit:order="3">READ_WRITE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADDR_WIDTH</spirit:name>
+      <spirit:displayName>Address Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH" spirit:order="4" spirit:minimum="12" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PACKING_LEVEL</spirit:name>
+      <spirit:displayName>Packing Level</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PACKING_LEVEL" spirit:choiceRef="choice_pairs_fe99fc86" spirit:order="5">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>SI Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SI_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="6">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>MI Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MI_DATA_WIDTH" spirit:choiceRef="choice_list_22f447d7" spirit:order="7">128</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SI_ID_WIDTH</spirit:name>
+      <spirit:displayName>SI ID Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SI_ID_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MAX_SPLIT_BEATS</spirit:name>
+      <spirit:displayName>Max Burst Length When Downsizing</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_SPLIT_BEATS" spirit:choiceRef="choice_list_0051c444" spirit:order="9">256</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FIFO_MODE</spirit:name>
+      <spirit:displayName>Upsizer FIFO</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_MODE" spirit:choiceRef="choice_pairs_a4d18bae" spirit:order="10">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_ASYNC</spirit:name>
+      <spirit:displayName>Is ACLK Asynchronous</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_ASYNC" spirit:choiceRef="choice_pairs_37189c7b" spirit:order="11">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SYNCHRONIZATION_STAGES</spirit:name>
+      <spirit:displayName>Synchronization Stages</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYNCHRONIZATION_STAGES" spirit:order="12" spirit:minimum="2" spirit:maximum="8" spirit:rangeType="long">3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ACLK_RATIO</spirit:name>
+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ACLK_RATIO" spirit:choiceRef="choice_list_42702293" spirit:order="1635284">1:2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">pl_eth_10g_auto_us_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>AXI Data Width Converter</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:systemCLibraries>
+        <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
+      </xilinx:systemCLibraries>
+      <xilinx:coreRevision>22</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_ASYNC" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d6eff22"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3617c7e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="27eb12c9"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ec085b51"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="0a01a2fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_clocks.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_clocks.xdc
new file mode 100644
index 0000000..f34adfb
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_clocks.xdc
@@ -0,0 +1,7 @@
+###############################################################################################################
+# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_us_0"
+###############################################################################################################
+#
+# This component is not configured to perform asynchronous clock-domain-crossing.
+# No timing core-level constraints are needed.
+# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_ooc.xdc
new file mode 100644
index 0000000..5d033a7
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_ooc.xdc
@@ -0,0 +1,49 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.cpp
new file mode 100644
index 0000000..1aa0486
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.cpp
@@ -0,0 +1,1222 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_us_0_sc.h"
+
+#include "pl_eth_10g_auto_us_0.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_us_0::pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_us_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_us_0::pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_us_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_us_0::pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+
+}
+
+void pl_eth_10g_auto_us_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_us_0::pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_0_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_us_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_us_0::pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_0_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "124998749");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_us_0::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_0", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_us_0::~pl_eth_10g_auto_us_0()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_awlock_converter;
+  delete mp_s_axi_arlock_converter;
+
+  delete mp_M_AXI_transactor;
+  delete mp_m_axi_awlock_converter;
+  delete mp_m_axi_arlock_converter;
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_us_0);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_us_0);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_us_0);
+SC_REGISTER_BV(128);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.h
new file mode 100644
index 0000000..49e6154
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.h
@@ -0,0 +1,648 @@
+#ifndef IP_PL_ETH_10G_AUTO_US_0_H_
+#define IP_PL_ETH_10G_AUTO_US_0_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_us_0_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
+{
+public:
+
+  pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
+{
+public:
+
+  pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
+{
+public:
+
+  pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
+{
+public:
+
+  pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
+{
+public:
+
+  pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_0();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_US_0_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.v
new file mode 100644
index 0000000..ef47138
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0.v
@@ -0,0 +1,379 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_us_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
+UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [127 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [15 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [127 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
+UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(1),
+    .C_SUPPORTS_ID(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(32),
+    .C_M_AXI_DATA_WIDTH(128),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_sc.cpp
new file mode 100644
index 0000000..40c738b
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_sc.cpp
@@ -0,0 +1,96 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_us_0_sc.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_us_0_sc::pl_eth_10g_auto_us_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_us_0", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
+    model_param_props.addLong("C_SUPPORTS_ID", "0");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
+    model_param_props.addLong("C_S_AXI_DATA_WIDTH", "32");
+    model_param_props.addLong("C_M_AXI_DATA_WIDTH", "128");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
+    model_param_props.addLong("C_FIFO_MODE", "0");
+    model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
+    model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
+    model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
+    model_param_props.addLong("C_MAX_SPLIT_BEATS", "16");
+    model_param_props.addLong("C_PACKING_LEVEL", "1");
+    model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_dwidth_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  target_rd_socket = mp_impl->target_rd_socket;
+  target_wr_socket = mp_impl->target_wr_socket;
+  initiator_rd_socket = mp_impl->initiator_rd_socket;
+  initiator_wr_socket = mp_impl->initiator_wr_socket;
+}
+
+pl_eth_10g_auto_us_0_sc::~pl_eth_10g_auto_us_0_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_sc.h
new file mode 100644
index 0000000..0e13675
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_US_0_SC_H_
+#define IP_PL_ETH_10G_AUTO_US_0_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_dwidth_converter;
+
+class DllExport pl_eth_10g_auto_us_0_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_us_0_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_0_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_dwidth_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_us_0_sc(const pl_eth_10g_auto_us_0_sc&);
+  const pl_eth_10g_auto_us_0_sc& operator=(const pl_eth_10g_auto_us_0_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_US_0_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_stub.sv
new file mode 100644
index 0000000..ab2aef3
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/sim/pl_eth_10g_auto_us_0_stub.sv
@@ -0,0 +1,302 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_us_0_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_0 (
+  input bit_as_bool s_axi_aclk,
+  input bit_as_bool s_axi_aresetn,
+  input bit [31 : 0] s_axi_awaddr,
+  input bit [7 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [0 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awregion,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [31 : 0] s_axi_wdata,
+  input bit [3 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  input bit [31 : 0] s_axi_araddr,
+  input bit [7 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [0 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arregion,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [31 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  output bit [31 : 0] m_axi_awaddr,
+  output bit [7 : 0] m_axi_awlen,
+  output bit [2 : 0] m_axi_awsize,
+  output bit [1 : 0] m_axi_awburst,
+  output bit [0 : 0] m_axi_awlock,
+  output bit [3 : 0] m_axi_awcache,
+  output bit [2 : 0] m_axi_awprot,
+  output bit [3 : 0] m_axi_awregion,
+  output bit [3 : 0] m_axi_awqos,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [127 : 0] m_axi_wdata,
+  output bit [15 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wlast,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready,
+  output bit [31 : 0] m_axi_araddr,
+  output bit [7 : 0] m_axi_arlen,
+  output bit [2 : 0] m_axi_arsize,
+  output bit [1 : 0] m_axi_arburst,
+  output bit [0 : 0] m_axi_arlock,
+  output bit [3 : 0] m_axi_arcache,
+  output bit [2 : 0] m_axi_arprot,
+  output bit [3 : 0] m_axi_arregion,
+  output bit [3 : 0] m_axi_arqos,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [127 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rlast,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_0 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [31 : 0] s_axi_wdata;
+  input bit [3 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [31 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [127 : 0] m_axi_wdata;
+  output wire [15 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [127 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_0 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [31 : 0] s_axi_wdata;
+  input bit [3 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [31 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [127 : 0] m_axi_wdata;
+  output wire [15 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [127 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/src/axi_dwidth_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/src/axi_dwidth_converter.cpp
new file mode 100644
index 0000000..16d5508
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/src/axi_dwidth_converter.cpp
@@ -0,0 +1,527 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "axi_dwidth_converter.h"
+#define PAYLOAD_LOG_LEVEL 3
+
+axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
+		xsc::common_cpp::properties& m_properties) :
+		sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
+				nullptr),m_logger((std::string) (p_name)) {
+
+	initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"rd_trace_socket", 32);
+	initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"wr_trace_socket", 32);
+	target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
+			32);
+	target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
+			32);
+	rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
+			"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
+	wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
+			"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
+	target_rd_socket->bind(rd_target_util->rd_socket);
+	target_wr_socket->bind(wr_target_util->wr_socket);
+	rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
+	wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
+
+	mem_manager = new xtlm::xtlm_aximm_mem_manager();
+	SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
+	MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
+  FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
+
+
+	ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
+    if(FIFO_MODE!=2)
+  {
+    	m_axi_aclk(clk);
+			m_axi_aresetn(resetn);
+  }
+
+	SC_METHOD(wr_handler);
+	dont_initialize();
+	sensitive << wr_target_util->transaction_available;
+    sensitive << event_trig_wr_handler;
+
+	SC_METHOD(rd_handler);
+	dont_initialize();
+	sensitive << rd_target_util->addr_available;
+    sensitive << event_trig_rd_handler;
+
+	SC_METHOD(m_downsize_interface_txn_sender);
+	sensitive << event_downsize_trig_txn_sender;
+    sensitive << wr_initiator_util->transaction_sampled;
+    sensitive << rd_initiator_util->transaction_sampled;
+	dont_initialize();
+
+	SC_METHOD(m_upsize_interface_txn_sender);
+	sensitive << event_upsize_trig_txn_sender;
+	dont_initialize();
+
+	SC_METHOD(m_downsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+	SC_METHOD(m_upsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+}
+
+void axi_dwidth_converter::wr_handler() {
+    if(wr_initiator_util->is_slave_ready() && 
+            wr_target_util->is_trans_available() )
+    {
+        m_wr_trans = wr_target_util->get_transaction();
+        m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+        ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
+        if (ratio <= 1)
+            wr_upsizing();
+        else
+            wr_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_handler() {
+    if(rd_initiator_util->is_slave_ready() &&
+            rd_target_util->is_trans_available() )
+    {
+	    m_rd_trans = rd_target_util->get_transaction();
+        
+        m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+	    
+        ratio = m_rd_trans->get_burst_size()  / MI_DATA_WIDTH;
+	    if (ratio <= 1)
+	    	rd_upsizing();
+	    else
+	    	rd_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_downsizing() {
+	auto beat_l = m_rd_trans->get_burst_length();
+	auto data = m_rd_trans->get_data_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto s_addr = m_rd_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    m_response_list = new std::list<xtlm::aximm_payload*>;
+	do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_rd_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_size(MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
+		m_interface_rd_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+        
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+	m_response_mapper_downsize[m_rd_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::wr_downsizing() {
+	auto beat_l = m_wr_trans->get_burst_length();
+	auto data = m_wr_trans->get_data_ptr();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto s_addr = m_wr_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+	m_response_list = new std::list<xtlm::aximm_payload*>;
+    
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_wr_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH );
+		t_trans->set_burst_size(MI_DATA_WIDTH );
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
+		m_interface_wr_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+
+	m_response_mapper_downsize[m_wr_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_downsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_interface_wr_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_interface_wr_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(
+				*m_interface_wr_payload_queue.front(), zero_delay);
+		m_interface_wr_payload_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_interface_rd_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_interface_rd_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(
+				*m_interface_rd_payload_queue.front(), zero_delay);
+		m_interface_rd_payload_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_downsize_interface_response_sender() {
+	if (ratio <= 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Write : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    wr_target_util->send_resp(*(itr->first), zero_delay);
+					delete (itr->second);
+					m_response_mapper_downsize.erase(itr);
+                    event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+					break;
+				}
+				response_payld->release();
+			}
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Read : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    rd_target_util->send_data(*(itr->first), zero_delay);
+					delete (itr->second);
+                    event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+					m_response_mapper_downsize.erase(itr);
+					break;
+				}
+				//Release the transaction to memory manager
+				response_payld->release();
+			}
+		}
+	}
+}
+void axi_dwidth_converter::wr_upsizing() {
+	auto si_addr = m_wr_trans->get_address();
+	auto si_burst_len = m_wr_trans->get_burst_length();
+	auto si_burst_size = m_wr_trans->get_burst_size();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto data = m_wr_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_wr_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH );
+	t_trans->set_burst_length(mi_len);
+	m_upsize_wr_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_wr_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+
+}
+void axi_dwidth_converter::rd_upsizing() {
+	auto si_addr = m_rd_trans->get_address();
+	auto si_burst_len = m_rd_trans->get_burst_length();
+	auto si_burst_size = m_rd_trans->get_burst_size();
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto data = m_rd_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_rd_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH);
+	t_trans->set_burst_length(mi_len);
+	m_upsize_rd_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_rd_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_upsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_upsize_wr_payld_queue.size() != 0)) {
+        
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_upsize_wr_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
+				zero_delay);
+		m_upsize_wr_payld_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_upsize_rd_payld_queue.size() != 0)) {
+
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_upsize_rd_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
+				zero_delay);
+		m_upsize_rd_payld_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_upsize_interface_response_sender() {
+	if (ratio > 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = (m_response_mapper_upsize.find(response_payld));
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Write : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = m_response_mapper_upsize.find(response_payld);
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Read : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+            
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+}
+
+axi_dwidth_converter::~axi_dwidth_converter() {
+	delete mem_manager;
+	delete target_rd_socket;
+	delete target_wr_socket;
+	delete initiator_rd_socket;
+	delete initiator_wr_socket;
+	delete rd_target_util;
+	delete wr_target_util;
+	delete wr_initiator_util;
+	delete rd_initiator_util;
+	delete m_rd_trans;
+	delete m_wr_trans;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/src/axi_dwidth_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/src/axi_dwidth_converter.h
new file mode 100644
index 0000000..35ad79d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/src/axi_dwidth_converter.h
@@ -0,0 +1,116 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#ifndef _AXI_DWIDTH_CONVERTER_H_
+#define _AXI_DWIDTH_CONVERTER_H_
+
+#include "xtlm.h"
+#include "report_handler.h"
+
+class axi_dwidth_converter: public sc_core::sc_module {
+public:
+    SC_HAS_PROCESS(axi_dwidth_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+	sc_core::sc_in<bool> s_axi_aclk;
+	sc_core::sc_in<bool> s_axi_aresetn;
+  sc_core::sc_in<bool> m_axi_aclk;
+	sc_core::sc_in<bool> m_axi_aresetn;
+  sc_core::sc_signal<bool> clk;
+	sc_core::sc_signal<bool> resetn;
+	axi_dwidth_converter(sc_core::sc_module_name p_name,
+				xsc::common_cpp::properties& m_properties);
+	xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
+    xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
+    xtlm::xtlm_aximm_mem_manager* mem_manager;
+    ~axi_dwidth_converter();
+    unsigned int SI_DATA_WIDTH;
+    unsigned int MI_DATA_WIDTH;
+    unsigned int FIFO_MODE;
+    unsigned int ratio;
+
+    void wr_handler();
+    void rd_handler();
+    void wr_upsizing();
+    void wr_downsizing();
+    void rd_upsizing();
+    void rd_downsizing();
+
+    /**
+     * @brief Method to send transaction on master interface
+     */
+    void m_downsize_interface_txn_sender();
+    void m_upsize_interface_txn_sender();
+
+    void m_downsize_interface_response_sender();
+    void m_upsize_interface_response_sender();
+
+private:
+    xtlm::aximm_payload* m_rd_trans;
+    xtlm::aximm_payload* m_wr_trans;
+    std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
+    sc_core::sc_event event_downsize_trig_txn_sender;	//!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_trig_rd_handler;
+    sc_core::sc_event event_trig_wr_handler;
+    std::list<xtlm::aximm_payload* > *m_response_list;
+    std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
+    std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
+    xsc::common_cpp::report_handler m_logger;
+    std::string m_log_msg;
+};
+
+#endif /* _AXI_DWIDTH_CONVERTER_H_ */
+
+
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/synth/pl_eth_10g_auto_us_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/synth/pl_eth_10g_auto_us_0.v
new file mode 100644
index 0000000..047d398
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/synth/pl_eth_10g_auto_us_0.v
@@ -0,0 +1,381 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_us_0,axi_dwidth_converter_v2_1_22_top,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_us_0,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=128,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BE\
+ATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_us_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
+UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [127 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [15 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [127 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
+UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(1),
+    .C_SUPPORTS_ID(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(32),
+    .C_M_AXI_DATA_WIDTH(128),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml
new file mode 100644
index 0000000..15b9c24
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml
@@ -0,0 +1,4382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_us_1</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">64</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">64</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_CLK</spirit:name>
+      <spirit:displayName>SI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>s_axi_aclk frequency</spirit:displayName>
+          <spirit:description>s_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">156250000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_CLK</spirit:name>
+      <spirit:displayName>MI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_ASYNC" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d6eff22"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3617c7e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="27eb12c9"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ec085b51"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="0a01a2fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_clocks.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_clocks.xdc
new file mode 100644
index 0000000..989ac56
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_clocks.xdc
@@ -0,0 +1,7 @@
+###############################################################################################################
+# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_us_1"
+###############################################################################################################
+#
+# This component is not configured to perform asynchronous clock-domain-crossing.
+# No timing core-level constraints are needed.
+# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_ooc.xdc
new file mode 100644
index 0000000..5d033a7
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_ooc.xdc
@@ -0,0 +1,49 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.cpp
new file mode 100644
index 0000000..fb69c86
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.cpp
@@ -0,0 +1,1006 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_us_1_sc.h"
+
+#include "pl_eth_10g_auto_us_1.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_us_1::pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_us_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "64");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_us_1::pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_us_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "64");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_us_1::pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_1_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_us_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "64");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+    mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+    mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+    mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+    mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+    mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+    mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+    mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+    mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+    mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+    mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+    mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+    mp_S_AXI_transactor->ARREADY(s_axi_arready);
+    mp_S_AXI_transactor->RDATA(s_axi_rdata);
+    mp_S_AXI_transactor->RRESP(s_axi_rresp);
+    mp_S_AXI_transactor->RLAST(s_axi_rlast);
+    mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+    mp_S_AXI_transactor->RREADY(s_axi_rready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+    mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+    mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+    mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+    mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+    mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+    mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+    mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+    mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+    mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+    mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+    mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+    mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+    mp_M_AXI_transactor->ARREADY(m_axi_arready);
+    mp_M_AXI_transactor->RDATA(m_axi_rdata);
+    mp_M_AXI_transactor->RRESP(m_axi_rresp);
+    mp_M_AXI_transactor->RLAST(m_axi_rlast);
+    mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+    mp_M_AXI_transactor->RREADY(m_axi_rready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_us_1::pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_1_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "64");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_us_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+    mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+    mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_us_1::pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_1_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arregion("m_axi_arregion"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_arlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_arlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_wr_socket_stub = NULL;
+  mp_M_AXI_wr_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "64");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
+  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
+  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
+  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
+  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
+  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
+  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
+  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
+  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
+  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
+  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
+  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
+  mp_S_AXI_transactor->ARREADY(s_axi_arready);
+  mp_S_AXI_transactor->RDATA(s_axi_rdata);
+  mp_S_AXI_transactor->RRESP(s_axi_rresp);
+  mp_S_AXI_transactor->RLAST(s_axi_rlast);
+  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
+  mp_S_AXI_transactor->RREADY(s_axi_rready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "32");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
+  mp_M_AXI_transactor->ARLEN(m_axi_arlen);
+  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
+  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
+  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_arlock_converter");
+  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
+  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
+  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
+  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
+  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
+  mp_M_AXI_transactor->ARREGION(m_axi_arregion);
+  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
+  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
+  mp_M_AXI_transactor->ARREADY(m_axi_arready);
+  mp_M_AXI_transactor->RDATA(m_axi_rdata);
+  mp_M_AXI_transactor->RRESP(m_axi_rresp);
+  mp_M_AXI_transactor->RLAST(m_axi_rlast);
+  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
+  mp_M_AXI_transactor->RREADY(m_axi_rready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_rd_socket_stub = nullptr;
+  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_us_1::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
+    mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
+    S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
+    mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+    M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_us_1::~pl_eth_10g_auto_us_1()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_arlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "S_AXI_TLM_MODE") != 1)
+  {
+    delete mp_S_AXI_wr_socket_stub;
+  }
+
+  delete mp_M_AXI_transactor;
+  delete mp_m_axi_arlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_1", "M_AXI_TLM_MODE") != 1)
+  {
+    delete mp_M_AXI_wr_socket_stub;
+  }
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_us_1);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_us_1);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_us_1);
+SC_REGISTER_BV(128);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.h
new file mode 100644
index 0000000..323a07a
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.h
@@ -0,0 +1,450 @@
+#ifndef IP_PL_ETH_10G_AUTO_US_1_H_
+#define IP_PL_ETH_10G_AUTO_US_1_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_us_1_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
+{
+public:
+
+  pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
+{
+public:
+
+  pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
+{
+public:
+
+  pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
+{
+public:
+
+  pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
+{
+public:
+
+  pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_1();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
+  sc_core::sc_in< bool > s_axi_arvalid;
+  sc_core::sc_out< bool > s_axi_arready;
+  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
+  sc_core::sc_out< bool > s_axi_rlast;
+  sc_core::sc_out< bool > s_axi_rvalid;
+  sc_core::sc_in< bool > s_axi_rready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
+  sc_core::sc_out< bool > m_axi_arvalid;
+  sc_core::sc_in< bool > m_axi_arready;
+  sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
+  sc_core::sc_in< bool > m_axi_rlast;
+  sc_core::sc_in< bool > m_axi_rvalid;
+  sc_core::sc_out< bool > m_axi_rready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
+  sc_signal< bool > m_s_axi_arlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
+  sc_signal< bool > m_m_axi_arlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_US_1_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.v
new file mode 100644
index 0000000..53bd492
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1.v
@@ -0,0 +1,265 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_us_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [63 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NUM\
+_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [127 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(1),
+    .C_SUPPORTS_ID(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(64),
+    .C_M_AXI_DATA_WIDTH(128),
+    .C_AXI_SUPPORTS_WRITE(0),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(32'H00000000),
+    .s_axi_awlen(8'H00),
+    .s_axi_awsize(3'H0),
+    .s_axi_awburst(2'H1),
+    .s_axi_awlock(1'H0),
+    .s_axi_awcache(4'H0),
+    .s_axi_awprot(3'H0),
+    .s_axi_awregion(4'H0),
+    .s_axi_awqos(4'H0),
+    .s_axi_awvalid(1'H0),
+    .s_axi_awready(),
+    .s_axi_wdata(64'H0000000000000000),
+    .s_axi_wstrb(8'HFF),
+    .s_axi_wlast(1'H1),
+    .s_axi_wvalid(1'H0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'H0),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'H0),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'H0),
+    .m_axi_bresp(2'H0),
+    .m_axi_bvalid(1'H0),
+    .m_axi_bready(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_sc.cpp
new file mode 100644
index 0000000..4e9e1da
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_sc.cpp
@@ -0,0 +1,96 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_us_1_sc.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_us_1_sc::pl_eth_10g_auto_us_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_us_1", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
+    model_param_props.addLong("C_SUPPORTS_ID", "0");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
+    model_param_props.addLong("C_S_AXI_DATA_WIDTH", "64");
+    model_param_props.addLong("C_M_AXI_DATA_WIDTH", "128");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "0");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
+    model_param_props.addLong("C_FIFO_MODE", "0");
+    model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
+    model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
+    model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
+    model_param_props.addLong("C_MAX_SPLIT_BEATS", "16");
+    model_param_props.addLong("C_PACKING_LEVEL", "1");
+    model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_dwidth_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  target_rd_socket = mp_impl->target_rd_socket;
+  target_wr_socket = mp_impl->target_wr_socket;
+  initiator_rd_socket = mp_impl->initiator_rd_socket;
+  initiator_wr_socket = mp_impl->initiator_wr_socket;
+}
+
+pl_eth_10g_auto_us_1_sc::~pl_eth_10g_auto_us_1_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_sc.h
new file mode 100644
index 0000000..0cd330d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_US_1_SC_H_
+#define IP_PL_ETH_10G_AUTO_US_1_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_dwidth_converter;
+
+class DllExport pl_eth_10g_auto_us_1_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_us_1_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_1_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_dwidth_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_us_1_sc(const pl_eth_10g_auto_us_1_sc&);
+  const pl_eth_10g_auto_us_1_sc& operator=(const pl_eth_10g_auto_us_1_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_US_1_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_stub.sv
new file mode 100644
index 0000000..3338a4b
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/sim/pl_eth_10g_auto_us_1_stub.sv
@@ -0,0 +1,188 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_us_1_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_1 (
+  input bit_as_bool s_axi_aclk,
+  input bit_as_bool s_axi_aresetn,
+  input bit [31 : 0] s_axi_araddr,
+  input bit [7 : 0] s_axi_arlen,
+  input bit [2 : 0] s_axi_arsize,
+  input bit [1 : 0] s_axi_arburst,
+  input bit [0 : 0] s_axi_arlock,
+  input bit [3 : 0] s_axi_arcache,
+  input bit [2 : 0] s_axi_arprot,
+  input bit [3 : 0] s_axi_arregion,
+  input bit [3 : 0] s_axi_arqos,
+  input bit_as_bool s_axi_arvalid,
+  output bit_as_bool s_axi_arready,
+  output bit [63 : 0] s_axi_rdata,
+  output bit [1 : 0] s_axi_rresp,
+  output bit_as_bool s_axi_rlast,
+  output bit_as_bool s_axi_rvalid,
+  input bit_as_bool s_axi_rready,
+  output bit [31 : 0] m_axi_araddr,
+  output bit [7 : 0] m_axi_arlen,
+  output bit [2 : 0] m_axi_arsize,
+  output bit [1 : 0] m_axi_arburst,
+  output bit [0 : 0] m_axi_arlock,
+  output bit [3 : 0] m_axi_arcache,
+  output bit [2 : 0] m_axi_arprot,
+  output bit [3 : 0] m_axi_arregion,
+  output bit [3 : 0] m_axi_arqos,
+  output bit_as_bool m_axi_arvalid,
+  input bit_as_bool m_axi_arready,
+  input bit [127 : 0] m_axi_rdata,
+  input bit [1 : 0] m_axi_rresp,
+  input bit_as_bool m_axi_rlast,
+  input bit_as_bool m_axi_rvalid,
+  output bit_as_bool m_axi_rready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_1 (s_axi_aclk,s_axi_aresetn,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+(* integer foreign = "SystemC";
+*);
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [63 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [127 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_1 (s_axi_aclk,s_axi_aresetn,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_araddr;
+  input bit [7 : 0] s_axi_arlen;
+  input bit [2 : 0] s_axi_arsize;
+  input bit [1 : 0] s_axi_arburst;
+  input bit [0 : 0] s_axi_arlock;
+  input bit [3 : 0] s_axi_arcache;
+  input bit [2 : 0] s_axi_arprot;
+  input bit [3 : 0] s_axi_arregion;
+  input bit [3 : 0] s_axi_arqos;
+  input bit s_axi_arvalid;
+  output wire s_axi_arready;
+  output wire [63 : 0] s_axi_rdata;
+  output wire [1 : 0] s_axi_rresp;
+  output wire s_axi_rlast;
+  output wire s_axi_rvalid;
+  input bit s_axi_rready;
+  output wire [31 : 0] m_axi_araddr;
+  output wire [7 : 0] m_axi_arlen;
+  output wire [2 : 0] m_axi_arsize;
+  output wire [1 : 0] m_axi_arburst;
+  output wire [0 : 0] m_axi_arlock;
+  output wire [3 : 0] m_axi_arcache;
+  output wire [2 : 0] m_axi_arprot;
+  output wire [3 : 0] m_axi_arregion;
+  output wire [3 : 0] m_axi_arqos;
+  output wire m_axi_arvalid;
+  input bit m_axi_arready;
+  input bit [127 : 0] m_axi_rdata;
+  input bit [1 : 0] m_axi_rresp;
+  input bit m_axi_rlast;
+  input bit m_axi_rvalid;
+  output wire m_axi_rready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/src/axi_dwidth_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/src/axi_dwidth_converter.cpp
new file mode 100644
index 0000000..16d5508
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/src/axi_dwidth_converter.cpp
@@ -0,0 +1,527 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "axi_dwidth_converter.h"
+#define PAYLOAD_LOG_LEVEL 3
+
+axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
+		xsc::common_cpp::properties& m_properties) :
+		sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
+				nullptr),m_logger((std::string) (p_name)) {
+
+	initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"rd_trace_socket", 32);
+	initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"wr_trace_socket", 32);
+	target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
+			32);
+	target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
+			32);
+	rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
+			"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
+	wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
+			"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
+	target_rd_socket->bind(rd_target_util->rd_socket);
+	target_wr_socket->bind(wr_target_util->wr_socket);
+	rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
+	wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
+
+	mem_manager = new xtlm::xtlm_aximm_mem_manager();
+	SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
+	MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
+  FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
+
+
+	ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
+    if(FIFO_MODE!=2)
+  {
+    	m_axi_aclk(clk);
+			m_axi_aresetn(resetn);
+  }
+
+	SC_METHOD(wr_handler);
+	dont_initialize();
+	sensitive << wr_target_util->transaction_available;
+    sensitive << event_trig_wr_handler;
+
+	SC_METHOD(rd_handler);
+	dont_initialize();
+	sensitive << rd_target_util->addr_available;
+    sensitive << event_trig_rd_handler;
+
+	SC_METHOD(m_downsize_interface_txn_sender);
+	sensitive << event_downsize_trig_txn_sender;
+    sensitive << wr_initiator_util->transaction_sampled;
+    sensitive << rd_initiator_util->transaction_sampled;
+	dont_initialize();
+
+	SC_METHOD(m_upsize_interface_txn_sender);
+	sensitive << event_upsize_trig_txn_sender;
+	dont_initialize();
+
+	SC_METHOD(m_downsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+	SC_METHOD(m_upsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+}
+
+void axi_dwidth_converter::wr_handler() {
+    if(wr_initiator_util->is_slave_ready() && 
+            wr_target_util->is_trans_available() )
+    {
+        m_wr_trans = wr_target_util->get_transaction();
+        m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+        ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
+        if (ratio <= 1)
+            wr_upsizing();
+        else
+            wr_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_handler() {
+    if(rd_initiator_util->is_slave_ready() &&
+            rd_target_util->is_trans_available() )
+    {
+	    m_rd_trans = rd_target_util->get_transaction();
+        
+        m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+	    
+        ratio = m_rd_trans->get_burst_size()  / MI_DATA_WIDTH;
+	    if (ratio <= 1)
+	    	rd_upsizing();
+	    else
+	    	rd_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_downsizing() {
+	auto beat_l = m_rd_trans->get_burst_length();
+	auto data = m_rd_trans->get_data_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto s_addr = m_rd_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    m_response_list = new std::list<xtlm::aximm_payload*>;
+	do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_rd_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_size(MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
+		m_interface_rd_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+        
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+	m_response_mapper_downsize[m_rd_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::wr_downsizing() {
+	auto beat_l = m_wr_trans->get_burst_length();
+	auto data = m_wr_trans->get_data_ptr();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto s_addr = m_wr_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+	m_response_list = new std::list<xtlm::aximm_payload*>;
+    
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_wr_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH );
+		t_trans->set_burst_size(MI_DATA_WIDTH );
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
+		m_interface_wr_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+
+	m_response_mapper_downsize[m_wr_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_downsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_interface_wr_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_interface_wr_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(
+				*m_interface_wr_payload_queue.front(), zero_delay);
+		m_interface_wr_payload_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_interface_rd_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_interface_rd_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(
+				*m_interface_rd_payload_queue.front(), zero_delay);
+		m_interface_rd_payload_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_downsize_interface_response_sender() {
+	if (ratio <= 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Write : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    wr_target_util->send_resp(*(itr->first), zero_delay);
+					delete (itr->second);
+					m_response_mapper_downsize.erase(itr);
+                    event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+					break;
+				}
+				response_payld->release();
+			}
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Read : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    rd_target_util->send_data(*(itr->first), zero_delay);
+					delete (itr->second);
+                    event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+					m_response_mapper_downsize.erase(itr);
+					break;
+				}
+				//Release the transaction to memory manager
+				response_payld->release();
+			}
+		}
+	}
+}
+void axi_dwidth_converter::wr_upsizing() {
+	auto si_addr = m_wr_trans->get_address();
+	auto si_burst_len = m_wr_trans->get_burst_length();
+	auto si_burst_size = m_wr_trans->get_burst_size();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto data = m_wr_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_wr_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH );
+	t_trans->set_burst_length(mi_len);
+	m_upsize_wr_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_wr_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+
+}
+void axi_dwidth_converter::rd_upsizing() {
+	auto si_addr = m_rd_trans->get_address();
+	auto si_burst_len = m_rd_trans->get_burst_length();
+	auto si_burst_size = m_rd_trans->get_burst_size();
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto data = m_rd_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_rd_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH);
+	t_trans->set_burst_length(mi_len);
+	m_upsize_rd_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_rd_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_upsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_upsize_wr_payld_queue.size() != 0)) {
+        
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_upsize_wr_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
+				zero_delay);
+		m_upsize_wr_payld_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_upsize_rd_payld_queue.size() != 0)) {
+
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_upsize_rd_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
+				zero_delay);
+		m_upsize_rd_payld_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_upsize_interface_response_sender() {
+	if (ratio > 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = (m_response_mapper_upsize.find(response_payld));
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Write : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = m_response_mapper_upsize.find(response_payld);
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Read : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+            
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+}
+
+axi_dwidth_converter::~axi_dwidth_converter() {
+	delete mem_manager;
+	delete target_rd_socket;
+	delete target_wr_socket;
+	delete initiator_rd_socket;
+	delete initiator_wr_socket;
+	delete rd_target_util;
+	delete wr_target_util;
+	delete wr_initiator_util;
+	delete rd_initiator_util;
+	delete m_rd_trans;
+	delete m_wr_trans;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/src/axi_dwidth_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/src/axi_dwidth_converter.h
new file mode 100644
index 0000000..35ad79d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/src/axi_dwidth_converter.h
@@ -0,0 +1,116 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#ifndef _AXI_DWIDTH_CONVERTER_H_
+#define _AXI_DWIDTH_CONVERTER_H_
+
+#include "xtlm.h"
+#include "report_handler.h"
+
+class axi_dwidth_converter: public sc_core::sc_module {
+public:
+    SC_HAS_PROCESS(axi_dwidth_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+	sc_core::sc_in<bool> s_axi_aclk;
+	sc_core::sc_in<bool> s_axi_aresetn;
+  sc_core::sc_in<bool> m_axi_aclk;
+	sc_core::sc_in<bool> m_axi_aresetn;
+  sc_core::sc_signal<bool> clk;
+	sc_core::sc_signal<bool> resetn;
+	axi_dwidth_converter(sc_core::sc_module_name p_name,
+				xsc::common_cpp::properties& m_properties);
+	xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
+    xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
+    xtlm::xtlm_aximm_mem_manager* mem_manager;
+    ~axi_dwidth_converter();
+    unsigned int SI_DATA_WIDTH;
+    unsigned int MI_DATA_WIDTH;
+    unsigned int FIFO_MODE;
+    unsigned int ratio;
+
+    void wr_handler();
+    void rd_handler();
+    void wr_upsizing();
+    void wr_downsizing();
+    void rd_upsizing();
+    void rd_downsizing();
+
+    /**
+     * @brief Method to send transaction on master interface
+     */
+    void m_downsize_interface_txn_sender();
+    void m_upsize_interface_txn_sender();
+
+    void m_downsize_interface_response_sender();
+    void m_upsize_interface_response_sender();
+
+private:
+    xtlm::aximm_payload* m_rd_trans;
+    xtlm::aximm_payload* m_wr_trans;
+    std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
+    sc_core::sc_event event_downsize_trig_txn_sender;	//!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_trig_rd_handler;
+    sc_core::sc_event event_trig_wr_handler;
+    std::list<xtlm::aximm_payload* > *m_response_list;
+    std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
+    std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
+    xsc::common_cpp::report_handler m_logger;
+    std::string m_log_msg;
+};
+
+#endif /* _AXI_DWIDTH_CONVERTER_H_ */
+
+
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/synth/pl_eth_10g_auto_us_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/synth/pl_eth_10g_auto_us_1.v
new file mode 100644
index 0000000..9262a2c
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/synth/pl_eth_10g_auto_us_1.v
@@ -0,0 +1,267 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_us_1,axi_dwidth_converter_v2_1_22_top,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_us_1,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=64,C_M_AXI_DATA_WIDTH=128,C_AXI_SUPPORTS_WRITE=0,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BE\
+ATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_us_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arregion,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_araddr,
+  m_axi_arlen,
+  m_axi_arsize,
+  m_axi_arburst,
+  m_axi_arlock,
+  m_axi_arcache,
+  m_axi_arprot,
+  m_axi_arregion,
+  m_axi_arqos,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rlast,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
+input wire [7 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
+input wire [0 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
+input wire [3 : 0] s_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
+output wire [63 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NUM\
+_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
+output wire [7 : 0] m_axi_arlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
+output wire [2 : 0] m_axi_arsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
+output wire [1 : 0] m_axi_arburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
+output wire [0 : 0] m_axi_arlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
+output wire [3 : 0] m_axi_arcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
+output wire [3 : 0] m_axi_arregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
+output wire [3 : 0] m_axi_arqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
+input wire [127 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
+input wire m_axi_rlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
+output wire m_axi_rready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(1),
+    .C_SUPPORTS_ID(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(64),
+    .C_M_AXI_DATA_WIDTH(128),
+    .C_AXI_SUPPORTS_WRITE(0),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(32'H00000000),
+    .s_axi_awlen(8'H00),
+    .s_axi_awsize(3'H0),
+    .s_axi_awburst(2'H1),
+    .s_axi_awlock(1'H0),
+    .s_axi_awcache(4'H0),
+    .s_axi_awprot(3'H0),
+    .s_axi_awregion(4'H0),
+    .s_axi_awqos(4'H0),
+    .s_axi_awvalid(1'H0),
+    .s_axi_awready(),
+    .s_axi_wdata(64'H0000000000000000),
+    .s_axi_wstrb(8'HFF),
+    .s_axi_wlast(1'H1),
+    .s_axi_wvalid(1'H0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'H0),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(s_axi_arregion),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'H0),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'H0),
+    .m_axi_bresp(2'H0),
+    .m_axi_bvalid(1'H0),
+    .m_axi_bready(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml
new file mode 100644
index 0000000..ac2fb02
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml
@@ -0,0 +1,4382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_auto_us_2</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI</spirit:name>
+      <spirit:displayName>S_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">64</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">WRITE_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arlock</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arregion</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arqos</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">128</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">WRITE_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">16</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_CLK</spirit:name>
+      <spirit:displayName>SI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>s_axi_aclk frequency</spirit:displayName>
+          <spirit:description>s_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">156250000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_CLK</spirit:name>
+      <spirit:displayName>MI_CLK</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>m_axi_aclk frequency</spirit:displayName>
+          <spirit:description>m_axi_aclk frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">10000000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MI_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MI_CLK" xilinx:dependency="((spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 2) || (spirit:decode(id(&apos;PARAM_VALUE.FIFO_MODE&apos;)) = 4))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>SI_RST</spirit:name>
+      <spirit:displayName>SI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_RST.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_RST.TYPE">INTERCONNECT</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MI_RST</spirit:name>
+      <spirit:displayName>MI_RST</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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+      <spirit:name>PROTOCOL</spirit:name>
+      <spirit:displayName>PROTOCOL</spirit:displayName>
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+      <spirit:displayName>READ_WRITE Mode</spirit:displayName>
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+      <spirit:displayName>Address Width</spirit:displayName>
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+    <spirit:parameter>
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+      <spirit:name>SI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>SI Data Width</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>MI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>MI Data Width</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>SI_ID_WIDTH</spirit:name>
+      <spirit:displayName>SI ID Width</spirit:displayName>
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+    <spirit:parameter>
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+    <spirit:parameter>
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+    <spirit:parameter>
+      <spirit:name>SYNCHRONIZATION_STAGES</spirit:name>
+      <spirit:displayName>Synchronization Stages</spirit:displayName>
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+    <spirit:parameter>
+      <spirit:name>ACLK_RATIO</spirit:name>
+      <spirit:displayName>SI to MI Clock Ratio</spirit:displayName>
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+  <spirit:vendorExtensions>
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+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_ASYNC" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d6eff22"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3617c7e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="27eb12c9"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ec085b51"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="0a01a2fe"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc
new file mode 100644
index 0000000..4f4655a
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc
@@ -0,0 +1,7 @@
+###############################################################################################################
+# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_us_2"
+###############################################################################################################
+#
+# This component is not configured to perform asynchronous clock-domain-crossing.
+# No timing core-level constraints are needed.
+# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_ooc.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_ooc.xdc
new file mode 100644
index 0000000..5d033a7
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_ooc.xdc
@@ -0,0 +1,49 @@
+################################################################################
+# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp
new file mode 100644
index 0000000..34144e0
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp
@@ -0,0 +1,1036 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_us_2_sc.h"
+
+#include "pl_eth_10g_auto_us_2.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+
+
+
+
+#ifdef XILINX_SIMULATOR
+pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_2_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_us_2::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_2_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_us_2::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_2_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // initialize socket stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+}
+
+void pl_eth_10g_auto_us_2::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "S_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+
+  // 'S_AXI' transactor parameters
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+
+    // S_AXI' transactor ports
+
+    mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+    mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+    mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+    mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+    mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+    mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+    mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+    mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+    mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+    mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+    mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+    mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+    mp_S_AXI_transactor->AWREADY(s_axi_awready);
+    mp_S_AXI_transactor->WDATA(s_axi_wdata);
+    mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+    mp_S_AXI_transactor->WLAST(s_axi_wlast);
+    mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+    mp_S_AXI_transactor->WREADY(s_axi_wready);
+    mp_S_AXI_transactor->BRESP(s_axi_bresp);
+    mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+    mp_S_AXI_transactor->BREADY(s_axi_bready);
+    mp_S_AXI_transactor->CLK(s_axi_aclk);
+    m_S_AXI_transactor_rst_signal.write(1);
+    mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+
+    // S_AXI' transactor sockets
+
+    mp_impl->target_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+  // configure 'M_AXI' transactor
+
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "M_AXI_TLM_MODE") != 1)
+  {
+    // Instantiate Socket Stubs
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+
+  // 'M_AXI' transactor parameters
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+
+    // M_AXI' transactor ports
+
+    mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+    mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+    mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+    mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+    mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+    mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+    mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+    mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+    mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+    mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+    mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+    mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+    mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+    mp_M_AXI_transactor->AWREADY(m_axi_awready);
+    mp_M_AXI_transactor->WDATA(m_axi_wdata);
+    mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+    mp_M_AXI_transactor->WLAST(m_axi_wlast);
+    mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+    mp_M_AXI_transactor->WREADY(m_axi_wready);
+    mp_M_AXI_transactor->BRESP(m_axi_bresp);
+    mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+    mp_M_AXI_transactor->BREADY(m_axi_bready);
+    mp_M_AXI_transactor->CLK(s_axi_aclk);
+    m_M_AXI_transactor_rst_signal.write(1);
+    mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+    // M_AXI' transactor sockets
+
+    mp_impl->initiator_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  }
+  else
+  {
+  }
+
+}
+
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_2_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_us_2::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+    mp_impl->target_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+    mp_impl->initiator_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : pl_eth_10g_auto_us_2_sc(nm),  s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awregion("s_axi_awregion"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awlen("m_axi_awlen"), m_axi_awsize("m_axi_awsize"), m_axi_awburst("m_axi_awburst"), m_axi_awlock("m_axi_awlock"), m_axi_awcache("m_axi_awcache"), m_axi_awprot("m_axi_awprot"), m_axi_awregion("m_axi_awregion"), m_axi_awqos("m_axi_awqos"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wlast("m_axi_wlast"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"),mp_S_AXI_rd_socket_stub(nullptr),mp_M_AXI_rd_socket_stub(nullptr)
+{
+  // initialize pins
+  mp_impl->s_axi_aclk(s_axi_aclk);
+  mp_impl->s_axi_aresetn(s_axi_aresetn);
+
+  // initialize transactors
+  mp_S_AXI_transactor = NULL;
+  mp_s_axi_awlock_converter = NULL;
+  mp_M_AXI_transactor = NULL;
+  mp_m_axi_awlock_converter = NULL;
+
+  // Instantiate Socket Stubs
+  mp_S_AXI_rd_socket_stub = NULL;
+  mp_M_AXI_rd_socket_stub = NULL;
+
+  // configure S_AXI_transactor
+    xsc::common_cpp::properties S_AXI_transactor_param_props;
+    S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
+    S_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    S_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    S_AXI_transactor_param_props.addFloat("PHASE", "0");
+    S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    S_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
+  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
+  mp_S_AXI_transactor->AWLEN(s_axi_awlen);
+  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
+  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
+  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_awlock_converter");
+  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
+  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
+  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
+  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
+  mp_S_AXI_transactor->AWREGION(s_axi_awregion);
+  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
+  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
+  mp_S_AXI_transactor->AWREADY(s_axi_awready);
+  mp_S_AXI_transactor->WDATA(s_axi_wdata);
+  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
+  mp_S_AXI_transactor->WLAST(s_axi_wlast);
+  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
+  mp_S_AXI_transactor->WREADY(s_axi_wready);
+  mp_S_AXI_transactor->BRESP(s_axi_bresp);
+  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
+  mp_S_AXI_transactor->BREADY(s_axi_bready);
+  mp_S_AXI_transactor->CLK(s_axi_aclk);
+  m_S_AXI_transactor_rst_signal.write(1);
+  mp_S_AXI_transactor->RST(m_S_AXI_transactor_rst_signal);
+  // configure M_AXI_transactor
+    xsc::common_cpp::properties M_AXI_transactor_param_props;
+    M_AXI_transactor_param_props.addLong("DATA_WIDTH", "128");
+    M_AXI_transactor_param_props.addLong("FREQ_HZ", "156250000");
+    M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+    M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+    M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
+    M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
+    M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+    M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
+    M_AXI_transactor_param_props.addLong("HAS_REGION", "1");
+    M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+    M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RRESP", "0");
+    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+    M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
+    M_AXI_transactor_param_props.addLong("HAS_RESET", "0");
+    M_AXI_transactor_param_props.addFloat("PHASE", "0");
+    M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
+    M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "WRITE_ONLY");
+    M_AXI_transactor_param_props.addString("CLK_DOMAIN", "pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0");
+
+    mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
+  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
+  mp_M_AXI_transactor->AWLEN(m_axi_awlen);
+  mp_M_AXI_transactor->AWSIZE(m_axi_awsize);
+  mp_M_AXI_transactor->AWBURST(m_axi_awburst);
+  mp_m_axi_awlock_converter = new xsc::common::scalar2vectorN_converter<1>("m_axi_awlock_converter");
+  mp_m_axi_awlock_converter->scalar_in(m_m_axi_awlock_converter_signal);
+  mp_m_axi_awlock_converter->vector_out(m_axi_awlock);
+  mp_M_AXI_transactor->AWLOCK(m_m_axi_awlock_converter_signal);
+  mp_M_AXI_transactor->AWCACHE(m_axi_awcache);
+  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
+  mp_M_AXI_transactor->AWREGION(m_axi_awregion);
+  mp_M_AXI_transactor->AWQOS(m_axi_awqos);
+  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
+  mp_M_AXI_transactor->AWREADY(m_axi_awready);
+  mp_M_AXI_transactor->WDATA(m_axi_wdata);
+  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
+  mp_M_AXI_transactor->WLAST(m_axi_wlast);
+  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
+  mp_M_AXI_transactor->WREADY(m_axi_wready);
+  mp_M_AXI_transactor->BRESP(m_axi_bresp);
+  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
+  mp_M_AXI_transactor->BREADY(m_axi_bready);
+  mp_M_AXI_transactor->CLK(s_axi_aclk);
+  m_M_AXI_transactor_rst_signal.write(1);
+  mp_M_AXI_transactor->RST(m_M_AXI_transactor_rst_signal);
+
+  // initialize transactors stubs
+  S_AXI_transactor_target_wr_socket_stub = nullptr;
+  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
+
+}
+
+void pl_eth_10g_auto_us_2::before_end_of_elaboration()
+{
+  // configure 'S_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "S_AXI_TLM_MODE") != 1)
+  {
+    mp_S_AXI_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket", 0);
+    mp_impl->target_rd_socket->bind(mp_S_AXI_rd_socket_stub->initiator_socket);
+    mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
+    S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
+    mp_S_AXI_transactor->disable_transactor();
+  }
+
+  // configure 'M_AXI' transactor
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "M_AXI_TLM_MODE") != 1)
+  {
+    mp_M_AXI_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket", 0);
+    mp_impl->initiator_rd_socket->bind(mp_M_AXI_rd_socket_stub->target_socket);
+    mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
+  
+  }
+  else
+  {
+    M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+    M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
+    mp_M_AXI_transactor->disable_transactor();
+  }
+
+}
+
+#endif // MTI_SYSTEMC
+
+
+
+
+pl_eth_10g_auto_us_2::~pl_eth_10g_auto_us_2()
+{
+  delete mp_S_AXI_transactor;
+  delete mp_s_axi_awlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "S_AXI_TLM_MODE") != 1)
+  {
+    delete mp_S_AXI_rd_socket_stub;
+  }
+
+  delete mp_M_AXI_transactor;
+  delete mp_m_axi_awlock_converter;
+  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("pl_eth_10g_auto_us_2", "M_AXI_TLM_MODE") != 1)
+  {
+    delete mp_M_AXI_rd_socket_stub;
+  }
+
+}
+
+#ifdef MTI_SYSTEMC
+SC_MODULE_EXPORT(pl_eth_10g_auto_us_2);
+#endif
+
+#ifdef XM_SYSTEMC
+XMSC_MODULE_EXPORT(pl_eth_10g_auto_us_2);
+#endif
+
+#ifdef RIVIERA
+SC_MODULE_EXPORT(pl_eth_10g_auto_us_2);
+SC_REGISTER_BV(128);
+#endif
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.h
new file mode 100644
index 0000000..e21c82e
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.h
@@ -0,0 +1,480 @@
+#ifndef IP_PL_ETH_10G_AUTO_US_2_H_
+#define IP_PL_ETH_10G_AUTO_US_2_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+#include "pl_eth_10g_auto_us_2_sc.h"
+
+
+
+
+#ifdef XILINX_SIMULATOR
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_us_2 : public pl_eth_10g_auto_us_2_sc
+{
+public:
+
+  pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_2();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // XILINX_SIMULATOR
+
+
+
+
+#ifdef XM_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_us_2 : public pl_eth_10g_auto_us_2_sc
+{
+public:
+
+  pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_2();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // XM_SYSTEMC
+
+
+
+
+#ifdef RIVIERA
+#include "utils/xtlm_aximm_initiator_stub.h"
+#include "utils/xtlm_aximm_target_stub.h"
+class DllExport pl_eth_10g_auto_us_2 : public pl_eth_10g_auto_us_2_sc
+{
+public:
+
+  pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_2();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // RIVIERA
+
+
+
+
+#ifdef VCSSYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_us_2 : public pl_eth_10g_auto_us_2_sc
+{
+public:
+
+  pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_2();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // VCSSYSTEMC
+
+
+
+
+#ifdef MTI_SYSTEMC
+#include "utils/xtlm_aximm_initiator_stub.h"
+
+#include "utils/xtlm_aximm_target_stub.h"
+
+class DllExport pl_eth_10g_auto_us_2 : public pl_eth_10g_auto_us_2_sc
+{
+public:
+
+  pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_2();
+
+  // module pin-to-pin RTL interface
+
+  sc_core::sc_in< bool > s_axi_aclk;
+  sc_core::sc_in< bool > s_axi_aresetn;
+  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
+  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
+  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
+  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
+  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
+  sc_core::sc_in< bool > s_axi_awvalid;
+  sc_core::sc_out< bool > s_axi_awready;
+  sc_core::sc_in< sc_dt::sc_bv<64> > s_axi_wdata;
+  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_wstrb;
+  sc_core::sc_in< bool > s_axi_wlast;
+  sc_core::sc_in< bool > s_axi_wvalid;
+  sc_core::sc_out< bool > s_axi_wready;
+  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
+  sc_core::sc_out< bool > s_axi_bvalid;
+  sc_core::sc_in< bool > s_axi_bready;
+  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
+  sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
+  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
+  sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
+  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
+  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
+  sc_core::sc_out< bool > m_axi_awvalid;
+  sc_core::sc_in< bool > m_axi_awready;
+  sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
+  sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
+  sc_core::sc_out< bool > m_axi_wlast;
+  sc_core::sc_out< bool > m_axi_wvalid;
+  sc_core::sc_in< bool > m_axi_wready;
+  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
+  sc_core::sc_in< bool > m_axi_bvalid;
+  sc_core::sc_out< bool > m_axi_bready;
+
+  // Dummy Signals for IP Ports
+
+
+protected:
+
+  virtual void before_end_of_elaboration();
+
+private:
+
+  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
+  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
+  sc_signal< bool > m_s_axi_awlock_converter_signal;
+  sc_signal< bool > m_S_AXI_transactor_rst_signal;
+  xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
+  xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
+  sc_signal< bool > m_m_axi_awlock_converter_signal;
+  sc_signal< bool > m_M_AXI_transactor_rst_signal;
+
+  // Transactor stubs
+  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
+  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
+
+  // Socket stubs
+  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
+  xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
+
+};
+#endif // MTI_SYSTEMC
+#endif // IP_PL_ETH_10G_AUTO_US_2_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v
new file mode 100644
index 0000000..1c1df42
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v
@@ -0,0 +1,283 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_us_2 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [63 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [7 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
+_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [127 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [15 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(1),
+    .C_SUPPORTS_ID(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(64),
+    .C_M_AXI_DATA_WIDTH(128),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(0),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(32'H00000000),
+    .s_axi_arlen(8'H00),
+    .s_axi_arsize(3'H0),
+    .s_axi_arburst(2'H1),
+    .s_axi_arlock(1'H0),
+    .s_axi_arcache(4'H0),
+    .s_axi_arprot(3'H0),
+    .s_axi_arregion(4'H0),
+    .s_axi_arqos(4'H0),
+    .s_axi_arvalid(1'H0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'H0),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'H0),
+    .m_axi_rdata(128'H00000000000000000000000000000000),
+    .m_axi_rresp(2'H0),
+    .m_axi_rlast(1'H1),
+    .m_axi_rvalid(1'H0),
+    .m_axi_rready()
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_sc.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_sc.cpp
new file mode 100644
index 0000000..1356950
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_sc.cpp
@@ -0,0 +1,96 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#include "pl_eth_10g_auto_us_2_sc.h"
+
+#include "axi_dwidth_converter.h"
+
+#include <map>
+#include <string>
+
+pl_eth_10g_auto_us_2_sc::pl_eth_10g_auto_us_2_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
+{
+  // configure connectivity manager
+  xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_us_2", this);
+
+  // initialize module
+    xsc::common_cpp::properties model_param_props;
+    model_param_props.addLong("C_AXI_PROTOCOL", "0");
+    model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
+    model_param_props.addLong("C_SUPPORTS_ID", "0");
+    model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
+    model_param_props.addLong("C_S_AXI_DATA_WIDTH", "64");
+    model_param_props.addLong("C_M_AXI_DATA_WIDTH", "128");
+    model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
+    model_param_props.addLong("C_AXI_SUPPORTS_READ", "0");
+    model_param_props.addLong("C_FIFO_MODE", "0");
+    model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
+    model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
+    model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
+    model_param_props.addLong("C_MAX_SPLIT_BEATS", "16");
+    model_param_props.addLong("C_PACKING_LEVEL", "1");
+    model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
+    model_param_props.addString("C_FAMILY", "zynquplus");
+
+  mp_impl = new axi_dwidth_converter("inst", model_param_props);
+
+  // initialize AXI sockets
+  target_rd_socket = mp_impl->target_rd_socket;
+  target_wr_socket = mp_impl->target_wr_socket;
+  initiator_rd_socket = mp_impl->initiator_rd_socket;
+  initiator_wr_socket = mp_impl->initiator_wr_socket;
+}
+
+pl_eth_10g_auto_us_2_sc::~pl_eth_10g_auto_us_2_sc()
+{
+  xsc::utils::xsc_sim_manager::clean();
+
+  delete mp_impl;
+}
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_sc.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_sc.h
new file mode 100644
index 0000000..d775293
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_sc.h
@@ -0,0 +1,98 @@
+#ifndef IP_PL_ETH_10G_AUTO_US_2_SC_H_
+#define IP_PL_ETH_10G_AUTO_US_2_SC_H_
+
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+#ifndef XTLM
+#include "xtlm.h"
+#endif
+#ifndef SYSTEMC_INCLUDED
+#include <systemc>
+#endif
+
+#if defined(_MSC_VER)
+#define DllExport __declspec(dllexport)
+#elif defined(__GNUC__)
+#define DllExport __attribute__ ((visibility("default")))
+#else
+#define DllExport
+#endif
+
+class axi_dwidth_converter;
+
+class DllExport pl_eth_10g_auto_us_2_sc : public sc_core::sc_module
+{
+public:
+
+  pl_eth_10g_auto_us_2_sc(const sc_core::sc_module_name& nm);
+  virtual ~pl_eth_10g_auto_us_2_sc();
+
+  // module socket-to-socket AXI TLM interfaces
+
+  xtlm::xtlm_aximm_target_socket* target_rd_socket;
+  xtlm::xtlm_aximm_target_socket* target_wr_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+  xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+
+  // module socket-to-socket TLM interfaces
+
+
+protected:
+
+  axi_dwidth_converter* mp_impl;
+
+private:
+
+  pl_eth_10g_auto_us_2_sc(const pl_eth_10g_auto_us_2_sc&);
+  const pl_eth_10g_auto_us_2_sc& operator=(const pl_eth_10g_auto_us_2_sc&);
+
+};
+
+#endif // IP_PL_ETH_10G_AUTO_US_2_SC_H_
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_stub.sv b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_stub.sv
new file mode 100644
index 0000000..64658b0
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2_stub.sv
@@ -0,0 +1,206 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+//------------------------------------------------------------------------------------
+// Filename:    pl_eth_10g_auto_us_2_stub.sv
+// Description: This HDL file is intended to be used with following simulators only:
+//
+//   Vivado Simulator (XSim)
+//   Cadence Xcelium Simulator
+//   Aldec Riviera-PRO Simulator
+//
+//------------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+`ifdef XILINX_SIMULATOR
+
+`ifndef XILINX_SIMULATOR_BITASBOOL
+`define XILINX_SIMULATOR_BITASBOOL
+typedef bit bit_as_bool;
+`endif
+
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_2 (
+  input bit_as_bool s_axi_aclk,
+  input bit_as_bool s_axi_aresetn,
+  input bit [31 : 0] s_axi_awaddr,
+  input bit [7 : 0] s_axi_awlen,
+  input bit [2 : 0] s_axi_awsize,
+  input bit [1 : 0] s_axi_awburst,
+  input bit [0 : 0] s_axi_awlock,
+  input bit [3 : 0] s_axi_awcache,
+  input bit [2 : 0] s_axi_awprot,
+  input bit [3 : 0] s_axi_awregion,
+  input bit [3 : 0] s_axi_awqos,
+  input bit_as_bool s_axi_awvalid,
+  output bit_as_bool s_axi_awready,
+  input bit [63 : 0] s_axi_wdata,
+  input bit [7 : 0] s_axi_wstrb,
+  input bit_as_bool s_axi_wlast,
+  input bit_as_bool s_axi_wvalid,
+  output bit_as_bool s_axi_wready,
+  output bit [1 : 0] s_axi_bresp,
+  output bit_as_bool s_axi_bvalid,
+  input bit_as_bool s_axi_bready,
+  output bit [31 : 0] m_axi_awaddr,
+  output bit [7 : 0] m_axi_awlen,
+  output bit [2 : 0] m_axi_awsize,
+  output bit [1 : 0] m_axi_awburst,
+  output bit [0 : 0] m_axi_awlock,
+  output bit [3 : 0] m_axi_awcache,
+  output bit [2 : 0] m_axi_awprot,
+  output bit [3 : 0] m_axi_awregion,
+  output bit [3 : 0] m_axi_awqos,
+  output bit_as_bool m_axi_awvalid,
+  input bit_as_bool m_axi_awready,
+  output bit [127 : 0] m_axi_wdata,
+  output bit [15 : 0] m_axi_wstrb,
+  output bit_as_bool m_axi_wlast,
+  output bit_as_bool m_axi_wvalid,
+  input bit_as_bool m_axi_wready,
+  input bit [1 : 0] m_axi_bresp,
+  input bit_as_bool m_axi_bvalid,
+  output bit_as_bool m_axi_bready
+);
+endmodule
+`endif
+
+`ifdef XCELIUM
+(* XMSC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_2 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready)
+(* integer foreign = "SystemC";
+*);
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [63 : 0] s_axi_wdata;
+  input bit [7 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [127 : 0] m_axi_wdata;
+  output wire [15 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+endmodule
+`endif
+
+`ifdef RIVIERA
+(* SC_MODULE_EXPORT *)
+module pl_eth_10g_auto_us_2 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready)
+  input bit s_axi_aclk;
+  input bit s_axi_aresetn;
+  input bit [31 : 0] s_axi_awaddr;
+  input bit [7 : 0] s_axi_awlen;
+  input bit [2 : 0] s_axi_awsize;
+  input bit [1 : 0] s_axi_awburst;
+  input bit [0 : 0] s_axi_awlock;
+  input bit [3 : 0] s_axi_awcache;
+  input bit [2 : 0] s_axi_awprot;
+  input bit [3 : 0] s_axi_awregion;
+  input bit [3 : 0] s_axi_awqos;
+  input bit s_axi_awvalid;
+  output wire s_axi_awready;
+  input bit [63 : 0] s_axi_wdata;
+  input bit [7 : 0] s_axi_wstrb;
+  input bit s_axi_wlast;
+  input bit s_axi_wvalid;
+  output wire s_axi_wready;
+  output wire [1 : 0] s_axi_bresp;
+  output wire s_axi_bvalid;
+  input bit s_axi_bready;
+  output wire [31 : 0] m_axi_awaddr;
+  output wire [7 : 0] m_axi_awlen;
+  output wire [2 : 0] m_axi_awsize;
+  output wire [1 : 0] m_axi_awburst;
+  output wire [0 : 0] m_axi_awlock;
+  output wire [3 : 0] m_axi_awcache;
+  output wire [2 : 0] m_axi_awprot;
+  output wire [3 : 0] m_axi_awregion;
+  output wire [3 : 0] m_axi_awqos;
+  output wire m_axi_awvalid;
+  input bit m_axi_awready;
+  output wire [127 : 0] m_axi_wdata;
+  output wire [15 : 0] m_axi_wstrb;
+  output wire m_axi_wlast;
+  output wire m_axi_wvalid;
+  input bit m_axi_wready;
+  input bit [1 : 0] m_axi_bresp;
+  input bit m_axi_bvalid;
+  output wire m_axi_bready;
+endmodule
+`endif
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/src/axi_dwidth_converter.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/src/axi_dwidth_converter.cpp
new file mode 100644
index 0000000..16d5508
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/src/axi_dwidth_converter.cpp
@@ -0,0 +1,527 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#include "axi_dwidth_converter.h"
+#define PAYLOAD_LOG_LEVEL 3
+
+axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
+		xsc::common_cpp::properties& m_properties) :
+		sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
+				nullptr),m_logger((std::string) (p_name)) {
+
+	initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"rd_trace_socket", 32);
+	initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
+			"wr_trace_socket", 32);
+	target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
+			32);
+	target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
+			32);
+	rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
+			xtlm::aximm::TRANSACTION, 32);
+	rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
+			"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
+	wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
+			"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
+	target_rd_socket->bind(rd_target_util->rd_socket);
+	target_wr_socket->bind(wr_target_util->wr_socket);
+	rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
+	wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
+
+	mem_manager = new xtlm::xtlm_aximm_mem_manager();
+	SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
+	MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
+  FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
+
+
+	ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
+    if(FIFO_MODE!=2)
+  {
+    	m_axi_aclk(clk);
+			m_axi_aresetn(resetn);
+  }
+
+	SC_METHOD(wr_handler);
+	dont_initialize();
+	sensitive << wr_target_util->transaction_available;
+    sensitive << event_trig_wr_handler;
+
+	SC_METHOD(rd_handler);
+	dont_initialize();
+	sensitive << rd_target_util->addr_available;
+    sensitive << event_trig_rd_handler;
+
+	SC_METHOD(m_downsize_interface_txn_sender);
+	sensitive << event_downsize_trig_txn_sender;
+    sensitive << wr_initiator_util->transaction_sampled;
+    sensitive << rd_initiator_util->transaction_sampled;
+	dont_initialize();
+
+	SC_METHOD(m_upsize_interface_txn_sender);
+	sensitive << event_upsize_trig_txn_sender;
+	dont_initialize();
+
+	SC_METHOD(m_downsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+	SC_METHOD(m_upsize_interface_response_sender);
+	dont_initialize();
+	sensitive << wr_initiator_util->resp_available;
+	sensitive << rd_initiator_util->data_available;
+  sensitive << rd_target_util->data_sampled;
+  sensitive << wr_target_util->resp_sampled;
+
+}
+
+void axi_dwidth_converter::wr_handler() {
+    if(wr_initiator_util->is_slave_ready() && 
+            wr_target_util->is_trans_available() )
+    {
+        m_wr_trans = wr_target_util->get_transaction();
+        m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+        ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
+        if (ratio <= 1)
+            wr_upsizing();
+        else
+            wr_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_handler() {
+    if(rd_initiator_util->is_slave_ready() &&
+            rd_target_util->is_trans_available() )
+    {
+	    m_rd_trans = rd_target_util->get_transaction();
+        
+        m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG); 
+	    
+        ratio = m_rd_trans->get_burst_size()  / MI_DATA_WIDTH;
+	    if (ratio <= 1)
+	    	rd_upsizing();
+	    else
+	    	rd_downsizing();
+    }
+}
+
+void axi_dwidth_converter::rd_downsizing() {
+	auto beat_l = m_rd_trans->get_burst_length();
+	auto data = m_rd_trans->get_data_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto s_addr = m_rd_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    m_response_list = new std::list<xtlm::aximm_payload*>;
+	do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_rd_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_size(MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH);
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
+		m_interface_rd_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+        
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+	m_response_mapper_downsize[m_rd_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::wr_downsizing() {
+	auto beat_l = m_wr_trans->get_burst_length();
+	auto data = m_wr_trans->get_data_ptr();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto new_beat_l = beat_l * (ratio);
+	auto s_addr = m_wr_trans->get_address();
+	auto num_byte_counter = 0;
+	auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
+	auto cur_beat_l = 0;
+	auto t_total_txns = 0;
+	m_response_list = new std::list<xtlm::aximm_payload*>;
+    
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg = "Down Sizing input transaction : " + payload_log;
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+	
+    do {
+		if (new_beat_l > 256)
+			cur_beat_l = 256;
+		else
+			cur_beat_l = new_beat_l;
+
+		xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+		t_trans->acquire();
+		t_trans->deep_copy_from(*m_wr_trans);
+		t_trans->set_address(s_addr + num_byte_counter);
+		t_trans->set_data_ptr(data + num_byte_counter,
+				cur_beat_l * MI_DATA_WIDTH);
+		if (strb != nullptr)
+			t_trans->set_byte_enable_ptr(strb + num_byte_counter,
+					cur_beat_l * MI_DATA_WIDTH );
+		t_trans->set_burst_size(MI_DATA_WIDTH );
+		t_trans->set_burst_length(cur_beat_l);
+		num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
+		m_interface_wr_payload_queue.push(t_trans);
+		m_response_list->push_back(t_trans);
+		t_total_txns++;
+
+        std::string payload_log; 
+        t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+        m_log_msg = "Down sized output transaction  : " + payload_log;
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG); 
+
+	} while (num_byte_counter < total_num_bytes);
+
+	m_response_mapper_downsize[m_wr_trans] = m_response_list;
+	event_downsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_downsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_interface_wr_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_interface_wr_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(
+				*m_interface_wr_payload_queue.front(), zero_delay);
+		m_interface_wr_payload_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_interface_rd_payload_queue.size() != 0)) {
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_interface_rd_payload_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(
+				*m_interface_rd_payload_queue.front(), zero_delay);
+		m_interface_rd_payload_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_downsize_interface_response_sender() {
+	if (ratio <= 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Write : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    wr_target_util->send_resp(*(itr->first), zero_delay);
+					delete (itr->second);
+					m_response_mapper_downsize.erase(itr);
+                    event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+					break;
+				}
+				response_payld->release();
+			}
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_downsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+
+		std::list<xtlm::aximm_payload*>::iterator itrlist;
+		std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
+		for (itr = m_response_mapper_downsize.begin();
+				itr != m_response_mapper_downsize.end(); itr++) {
+			itrlist = (std::find(itr->second->begin(), itr->second->end(),
+					response_payld));
+			if (itrlist != itr->second->end()) {
+				itr->second->remove(response_payld);
+				if (itr->second->size() == 0) {
+					sc_core::sc_time zero_delay = SC_ZERO_TIME;
+                    itr->first->set_axi_response_status(
+                            response_payld->get_axi_response_status());
+                    m_log_msg = "Sending Response for Read : " + 
+                        std::to_string(itr->first->get_address());
+                    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG); 
+					
+                    rd_target_util->send_data(*(itr->first), zero_delay);
+					delete (itr->second);
+                    event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+					m_response_mapper_downsize.erase(itr);
+					break;
+				}
+				//Release the transaction to memory manager
+				response_payld->release();
+			}
+		}
+	}
+}
+void axi_dwidth_converter::wr_upsizing() {
+	auto si_addr = m_wr_trans->get_address();
+	auto si_burst_len = m_wr_trans->get_burst_length();
+	auto si_burst_size = m_wr_trans->get_burst_size();
+	auto strb = m_wr_trans->get_byte_enable_ptr();
+	auto data = m_wr_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_wr_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH );
+	t_trans->set_burst_length(mi_len);
+	m_upsize_wr_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_wr_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+
+}
+void axi_dwidth_converter::rd_upsizing() {
+	auto si_addr = m_rd_trans->get_address();
+	auto si_burst_len = m_rd_trans->get_burst_length();
+	auto si_burst_size = m_rd_trans->get_burst_size();
+	auto strb = m_rd_trans->get_byte_enable_ptr();
+	auto data = m_rd_trans->get_data_ptr();
+	auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
+	auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
+			+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
+			* MI_DATA_WIDTH;
+	auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
+
+	xtlm::aximm_payload* t_trans = mem_manager->get_payload();
+	t_trans->acquire();
+	t_trans->deep_copy_from(*m_rd_trans);
+	t_trans->set_address(si_addr);
+	t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
+	if (strb != nullptr)
+		t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
+	t_trans->set_burst_size(MI_DATA_WIDTH);
+	t_trans->set_burst_length(mi_len);
+	m_upsize_rd_payld_queue.push(t_trans);
+	m_response_mapper_upsize[t_trans] = m_rd_trans;
+    
+    m_log_msg = "Upsizing input Txn ";
+    std::string payload_log; 
+    m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+
+    m_log_msg = "Upsized output Txn ";
+    t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
+    m_log_msg += payload_log;                
+    XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG); 
+	
+    event_upsize_trig_txn_sender.notify();
+}
+
+void axi_dwidth_converter::m_upsize_interface_txn_sender() {
+	sc_core::sc_time zero_delay = SC_ZERO_TIME;
+	if (wr_initiator_util->is_slave_ready()
+			&& (m_upsize_wr_payld_queue.size() != 0)) {
+        
+        m_log_msg = "Sending Write transaction " + 
+            std::to_string(m_upsize_wr_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
+				zero_delay);
+		m_upsize_wr_payld_queue.pop();
+	}
+
+	//For Read transaction
+	zero_delay = SC_ZERO_TIME;
+	if (rd_initiator_util->is_slave_ready()
+			&& (m_upsize_rd_payld_queue.size() != 0)) {
+
+        m_log_msg = "Sending Read transaction " + 
+            std::to_string(m_upsize_rd_payld_queue.front()->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG); 
+		
+        rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
+				zero_delay);
+		m_upsize_rd_payld_queue.pop();
+	}
+
+}
+void axi_dwidth_converter::m_upsize_interface_response_sender() {
+	if (ratio > 1)
+		return;
+	if (wr_initiator_util->is_resp_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (wr_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
+        m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = (m_response_mapper_upsize.find(response_payld));
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Write : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+
+	if (rd_initiator_util->is_data_available()
+			&& (m_response_mapper_upsize.size() != 0)
+			&& (rd_target_util->is_master_ready())) {
+		xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
+        m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
+        XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG); 
+
+		std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
+		itr = m_response_mapper_upsize.find(response_payld);
+		if (itr != m_response_mapper_upsize.end()) {
+			sc_core::sc_time zero_delay = SC_ZERO_TIME;
+            m_response_mapper_upsize[response_payld]->set_axi_response_status(
+                    response_payld->get_axi_response_status());
+            m_log_msg = "Sending Response for Read : " + 
+                std::to_string(m_response_mapper_upsize[response_payld]->get_address());
+            XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
+
+			rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
+					zero_delay);
+            
+			response_payld->release();
+			m_response_mapper_upsize.erase(response_payld);
+            event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
+		}
+	}
+}
+
+axi_dwidth_converter::~axi_dwidth_converter() {
+	delete mem_manager;
+	delete target_rd_socket;
+	delete target_wr_socket;
+	delete initiator_rd_socket;
+	delete initiator_wr_socket;
+	delete rd_target_util;
+	delete wr_target_util;
+	delete wr_initiator_util;
+	delete rd_initiator_util;
+	delete m_rd_trans;
+	delete m_wr_trans;
+}
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/src/axi_dwidth_converter.h b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/src/axi_dwidth_converter.h
new file mode 100644
index 0000000..35ad79d
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/src/axi_dwidth_converter.h
@@ -0,0 +1,116 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+#ifndef _AXI_DWIDTH_CONVERTER_H_
+#define _AXI_DWIDTH_CONVERTER_H_
+
+#include "xtlm.h"
+#include "report_handler.h"
+
+class axi_dwidth_converter: public sc_core::sc_module {
+public:
+    SC_HAS_PROCESS(axi_dwidth_converter);
+	xtlm::xtlm_aximm_target_socket* target_rd_socket;
+	xtlm::xtlm_aximm_target_socket* target_wr_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
+	xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
+	sc_core::sc_in<bool> s_axi_aclk;
+	sc_core::sc_in<bool> s_axi_aresetn;
+  sc_core::sc_in<bool> m_axi_aclk;
+	sc_core::sc_in<bool> m_axi_aresetn;
+  sc_core::sc_signal<bool> clk;
+	sc_core::sc_signal<bool> resetn;
+	axi_dwidth_converter(sc_core::sc_module_name p_name,
+				xsc::common_cpp::properties& m_properties);
+	xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
+    xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
+    xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
+    xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
+    xtlm::xtlm_aximm_mem_manager* mem_manager;
+    ~axi_dwidth_converter();
+    unsigned int SI_DATA_WIDTH;
+    unsigned int MI_DATA_WIDTH;
+    unsigned int FIFO_MODE;
+    unsigned int ratio;
+
+    void wr_handler();
+    void rd_handler();
+    void wr_upsizing();
+    void wr_downsizing();
+    void rd_upsizing();
+    void rd_downsizing();
+
+    /**
+     * @brief Method to send transaction on master interface
+     */
+    void m_downsize_interface_txn_sender();
+    void m_upsize_interface_txn_sender();
+
+    void m_downsize_interface_response_sender();
+    void m_upsize_interface_response_sender();
+
+private:
+    xtlm::aximm_payload* m_rd_trans;
+    xtlm::aximm_payload* m_wr_trans;
+    std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
+    std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
+    sc_core::sc_event event_downsize_trig_txn_sender;	//!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
+    sc_core::sc_event event_trig_rd_handler;
+    sc_core::sc_event event_trig_wr_handler;
+    std::list<xtlm::aximm_payload* > *m_response_list;
+    std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
+    std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
+    xsc::common_cpp::report_handler m_logger;
+    std::string m_log_msg;
+};
+
+#endif /* _AXI_DWIDTH_CONVERTER_H_ */
+
+
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v
new file mode 100644
index 0000000..f2375ca
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v
@@ -0,0 +1,285 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
+// IP Revision: 22
+
+(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
+(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_us_2,axi_dwidth_converter_v2_1_22_top,{}" *)
+(* CORE_GENERATION_INFO = "pl_eth_10g_auto_us_2,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=64,C_M_AXI_DATA_WIDTH=128,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BE\
+ATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pl_eth_10g_auto_us_2 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awregion,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  m_axi_awaddr,
+  m_axi_awlen,
+  m_axi_awsize,
+  m_axi_awburst,
+  m_axi_awlock,
+  m_axi_awcache,
+  m_axi_awprot,
+  m_axi_awregion,
+  m_axi_awqos,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wlast,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
+input wire [7 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
+input wire [0 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
+input wire [3 : 0] s_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
+input wire [63 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
+input wire [7 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
+_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
+output wire [7 : 0] m_axi_awlen;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
+output wire [2 : 0] m_axi_awsize;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
+output wire [1 : 0] m_axi_awburst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
+output wire [0 : 0] m_axi_awlock;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
+output wire [3 : 0] m_axi_awcache;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
+output wire [3 : 0] m_axi_awregion;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
+output wire [3 : 0] m_axi_awqos;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
+output wire [127 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
+output wire [15 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
+output wire m_axi_wlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
+output wire m_axi_bready;
+
+  axi_dwidth_converter_v2_1_22_top #(
+    .C_FAMILY("zynquplus"),
+    .C_AXI_PROTOCOL(0),
+    .C_S_AXI_ID_WIDTH(1),
+    .C_SUPPORTS_ID(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(64),
+    .C_M_AXI_DATA_WIDTH(128),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(0),
+    .C_FIFO_MODE(0),
+    .C_S_AXI_ACLK_RATIO(1),
+    .C_M_AXI_ACLK_RATIO(2),
+    .C_AXI_IS_ACLK_ASYNC(0),
+    .C_MAX_SPLIT_BEATS(16),
+    .C_PACKING_LEVEL(1),
+    .C_SYNCHRONIZER_STAGE(3)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awid(1'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(s_axi_awregion),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1'H0),
+    .s_axi_araddr(32'H00000000),
+    .s_axi_arlen(8'H00),
+    .s_axi_arsize(3'H0),
+    .s_axi_arburst(2'H1),
+    .s_axi_arlock(1'H0),
+    .s_axi_arcache(4'H0),
+    .s_axi_arprot(3'H0),
+    .s_axi_arregion(4'H0),
+    .s_axi_arqos(4'H0),
+    .s_axi_arvalid(1'H0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'H0),
+    .m_axi_aclk(1'H0),
+    .m_axi_aresetn(1'H0),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'H0),
+    .m_axi_rdata(128'H00000000000000000000000000000000),
+    .m_axi_rresp(2'H0),
+    .m_axi_rlast(1'H1),
+    .m_axi_rvalid(1'H0),
+    .m_axi_rready()
+  );
+endmodule
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xdc b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xdc
new file mode 100644
index 0000000..ac4fe53
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xdc
@@ -0,0 +1,65 @@
+# file: pl_eth_10g_axi_dma_0_0.xdc
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+## INFO: Level CDC Crossing in AXI DMA
+
+set_false_path -to [get_pins -hier *cdc_to*/D]
+
+create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
+-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
+-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
+
+create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
+-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
+-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
+
+# Specific to MultiChannel mode
+create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
+-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. In multi channel mode, it is safe to ignore this." \
+-from [get_pins -hier -quiet -filter {NAME =~*MM2S_SPLIT.I_COMMAND_MM2S_SPLITTER/vsize_data_int_reg[*]/C}]
+
+
diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml
new file mode 100644
index 0000000..f6bc6cd
--- /dev/null
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml
@@ -0,0 +1,8893 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>pl_eth_10g_axi_dma_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_LITE</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">10</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_SG</spirit:name>
+      <spirit:displayName>M_AXI_SG</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_SG"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.NUM_READ_OUTSTANDING">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.NUM_WRITE_OUTSTANDING">2</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.MAX_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.FREQ_HZ">124998749</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_SG" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;)) = 1)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI</spirit:name>
+      <spirit:displayName>M_AXI</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_SINGLE_INTERFACE&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_MM2S</spirit:name>
+      <spirit:displayName>M_AXI_MM2S</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_MM2S"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_aruser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.DATA_WIDTH">64</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.READ_WRITE_MODE">READ_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_RRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.MAX_BURST_LENGTH">64</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_MM2S" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_MM2S&apos;)) = 1 and (spirit:decode(id(&apos;PARAM_VALUE.C_SINGLE_INTERFACE&apos;)) = 0))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_S2MM</spirit:name>
+      <spirit:displayName>M_AXI_S2MM</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_S2MM"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awburst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awcache</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awlen</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awsize</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.DATA_WIDTH">64</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.PROTOCOL">AXI4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.ADDR_WIDTH">32</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.READ_WRITE_MODE">WRITE_ONLY</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_PROT">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_CACHE">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_WSTRB">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BRESP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_OUTSTANDING">2</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.MAX_BURST_LENGTH">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_S2MM" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_S2MM&apos;)) = 1 and (spirit:decode(id(&apos;PARAM_VALUE.C_SINGLE_INTERFACE&apos;)) = 0))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_MM2S</spirit:name>
+      <spirit:displayName>M_AXIS_MM2S</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.TDATA_NUM_BYTES">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_MM2S" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_MM2S&apos;)) = 1)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_S2MM</spirit:name>
+      <spirit:displayName>S_AXIS_S2MM</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDEST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tdest</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tuser</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDATA_NUM_BYTES">8</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.FREQ_HZ">156250000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_S2MM.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_S2MM" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_S2MM&apos;)) = 1)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXIS_CNTRL</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_cntrl_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_cntrl_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_cntrl_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_cntrl_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axis_mm2s_cntrl_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDATA_NUM_BYTES">4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CNTRL.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_CNTRL" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_MM2S&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_SG_INCLUDE_STSCNTRL_STRM&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXIS_STS</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_sts_tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_sts_tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_sts_tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_sts_tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axis_s2mm_sts_tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>TDATA_NUM_BYTES</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.TDATA_NUM_BYTES">4</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TDEST_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.TDEST_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.TID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>TUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.TUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TREADY</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TREADY">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TKEEP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TKEEP">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_TLAST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TLAST">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>LAYERED_METADATA</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.LAYERED_METADATA">undef</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_STS.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_STS" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_S2MM&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_SG_INCLUDE_STSCNTRL_STRM&apos;)) = 1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>AXI_RESETN</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>axi_resetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AXI_RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_RESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MM2S_INTROUT</spirit:name>
+      <spirit:displayName>mm2s_introut</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mm2s_introut</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MM2S_INTROUT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MM2S_INTROUT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S2MM_INTROUT</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s2mm_introut</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S2MM_INTROUT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S2MM_INTROUT.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_SG_CLK</spirit:name>
+      <spirit:displayName>M_AXI_SG_CLK</spirit:displayName>
+      <spirit:description>SG AXI4 Clock</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_sg_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_SG_CLK.ASSOCIATED_BUSIF">M_AXI_SG</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>MAXI SG clock frequency</spirit:displayName>
+          <spirit:description>MAXI SG clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG_CLK.FREQ_HZ">124998749</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG_CLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG_CLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_SG_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_MM2S_CLK</spirit:name>
+      <spirit:displayName>m_axi_mm2s_clk</spirit:displayName>
+      <spirit:description>MM2S AXI4 Clock</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_mm2s_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.ASSOCIATED_BUSIF">M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.ASSOCIATED_RESET">mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>M_AXI_MM2S_CLK clock frequency</spirit:displayName>
+          <spirit:description>M_AXI_MM2S_CLK clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.FREQ_HZ">156250000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>M_AXI_S2MM_CLK</spirit:name>
+      <spirit:displayName>m_axi_s2mm_clk</spirit:displayName>
+      <spirit:description>S2MM AXI4 Clock</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_s2mm_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.ASSOCIATED_BUSIF">M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.ASSOCIATED_RESET">s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>M_AXI_S2MM_CLK clock frequency</spirit:displayName>
+          <spirit:description>M_AXI_S2MM_CLK clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_HZ">156250000</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.PHASE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.CLK_DOMAIN">pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S_AXI_LITE_ACLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_lite_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.ASSOCIATED_BUSIF">S_AXI_LITE:M_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.ASSOCIATED_RESET">axi_resetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>S_AXI_LITE_ACLK clock frequency</spirit:displayName>
+          <spirit:description>S_AXI_LITE_ACLK clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_HZ">124998749</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.PHASE">0.000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.CLK_DOMAIN">pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MM2S_PRMRY_RESET_OUT_N</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mm2s_prmry_reset_out_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MM2S_PRMRY_RESET_OUT_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MM2S_PRMRY_RESET_OUT_N.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S2MM_PRMRY_RESET_OUT_N</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s2mm_prmry_reset_out_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S2MM_PRMRY_RESET_OUT_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S2MM_PRMRY_RESET_OUT_N.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>MM2S_CNTRL_RESET_OUT_N</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>mm2s_cntrl_reset_out_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.MM2S_CNTRL_RESET_OUT_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MM2S_CNTRL_RESET_OUT_N.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S2MM_STS_RESET_OUT_N</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s2mm_sts_reset_out_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S2MM_STS_RESET_OUT_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S2MM_STS_RESET_OUT_N.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_SG</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_SG_ADDR_WIDTH&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_SG_ADDR_WIDTH&apos;))">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_SG.DEPENDENT_ON">S_AXI_LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_SG.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:addressSpaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRSPACE_ENABLEMENT.Data_SG" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;)) = 1">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:addressSpaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_MM2S_ADDR_WIDTH&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_MM2S_ADDR_WIDTH&apos;))">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA.DEPENDENT_ON">S_AXI_LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:addressSpaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRSPACE_ENABLEMENT.Data" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.C_SINGLE_INTERFACE&apos;)) = 1">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:addressSpaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_MM2S</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_MM2S_ADDR_WIDTH&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_MM2S_ADDR_WIDTH&apos;))">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_MM2S.DEPENDENT_ON">S_AXI_LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_MM2S.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:addressSpaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRSPACE_ENABLEMENT.Data_MM2S" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_MM2S&apos;)) = 1 and spirit:decode(id(&apos;PARAM_VALUE.C_SINGLE_INTERFACE&apos;)) = 0)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:addressSpaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_S2MM</spirit:name>
+      <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(pow(2,spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_S2MM_ADDR_WIDTH&apos;)))))">4294967296</spirit:range>
+      <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_M_AXI_S2MM_ADDR_WIDTH&apos;))">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_S2MM.DEPENDENT_ON">S_AXI_LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_S2MM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:addressSpaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRSPACE_ENABLEMENT.Data_S2MM" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_S2MM&apos;)) = 1 and spirit:decode(id(&apos;PARAM_VALUE.C_SINGLE_INTERFACE&apos;)) = 0)">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:addressSpaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>S_AXI_LITE</spirit:name>
+      <spirit:displayName>S_AXI_MEM</spirit:displayName>
+      <spirit:description>Memory Map for S_AXI_LITE</spirit:description>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:displayName>Reg</spirit:displayName>
+        <spirit:description>Register Block</spirit:description>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">4096</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:register>
+          <spirit:name>MM2S_DMACR</spirit:name>
+          <spirit:displayName>MM2S DMA Control Register</spirit:displayName>
+          <spirit:description>MM2S DMA Control Register</spirit:description>
+          <spirit:addressOffset>0x0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x10002</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>RS</spirit:name>
+            <spirit:displayName>Run/Stop Control</spirit:displayName>
+            <spirit:description>Run / Stop control for controlling running and stopping of the DMA channel.
+  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. 
+  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
+  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
+  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
+  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Reset</spirit:name>
+            <spirit:displayName>Soft Reset</spirit:displayName>
+            <spirit:description>Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
+AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.
+</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Keyhole</spirit:name>
+            <spirit:displayName>Keyhole Read</spirit:displayName>
+            <spirit:description>Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
+This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
+</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Cyclic_BD_Enable</spirit:name>
+            <spirit:displayName>Cyclic BD Enable</spirit:displayName>
+            <spirit:description>When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
+This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
+This bit is non functional when DMA operates in multichannel mode.
+</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IOC_IrqEn</spirit:name>
+            <spirit:displayName>Interrupt on Complete (IOC) Interrupt Enable</spirit:displayName>
+            <spirit:description>Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled
+</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Dly_IrqEn</spirit:name>
+            <spirit:displayName>Interrupt on Delay Timer Interrupt Enable</spirit:displayName>
+            <spirit:description>Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
+</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Err_IrqEn</spirit:name>
+            <spirit:displayName>Interrupt on Error Interrupt Enable</spirit:displayName>
+            <spirit:description>Interrupt on Error Interrupt Enable.
+  0 - Error Interrupt disabled
+  1 - Error Interrupt enabled
+</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQThreshold</spirit:name>
+            <spirit:displayName>Interrupt Threshold</spirit:displayName>
+            <spirit:description>Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQDelay</spirit:name>
+            <spirit:displayName>Interrupt Delay Time Out</spirit:displayName>
+            <spirit:description>Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
+Note: Setting this value to zero disables the delay timer interrupt.
+Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
+</spirit:description>
+            <spirit:bitOffset>24</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_DMASR</spirit:name>
+          <spirit:displayName>MM2S DMA Status Register</spirit:displayName>
+          <spirit:description>MM2S DMA Status Register</spirit:description>
+          <spirit:addressOffset>0x04</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x10000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Halted</spirit:name>
+            <spirit:displayName>DMA Channel Halted</spirit:displayName>
+            <spirit:description>DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Idle</spirit:name>
+            <spirit:displayName>DMA Channel Idle</spirit:displayName>
+            <spirit:description>DMA Channel Idle. Indicates the state of AXI DMA operations.
+For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
+For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGIncld</spirit:name>
+            <spirit:displayName>SGIncld</spirit:displayName>
+            <spirit:description>1 - Scatter Gather Enabled
+0 - Scatter Gather not enabled
+</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>DMAIntErr</spirit:name>
+            <spirit:displayName>DMA Internal Error</spirit:displayName>
+            <spirit:description>DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts
+</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>DMASlvErr</spirit:name>
+            <spirit:displayName>DMA Slave Error</spirit:displayName>
+            <spirit:description>DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts
+</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>DMADecErr</spirit:name>
+            <spirit:displayName>DMA Decode Error</spirit:displayName>
+            <spirit:description>DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGIntErr</spirit:name>
+            <spirit:displayName>Scatter Gather Internal Error</spirit:displayName>
+            <spirit:description>Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit� already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
+</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGSlvErr</spirit:name>
+            <spirit:displayName>Scatter Gather Slave Error</spirit:displayName>
+            <spirit:description>Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. 
+</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGDecErr</spirit:name>
+            <spirit:displayName>Scatter Gather Decode Error</spirit:displayName>
+            <spirit:description>Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. 
+</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IOC_Irq</spirit:name>
+            <spirit:displayName>Interrupt on Complete</spirit:displayName>
+            <spirit:description>Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.
+</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Dly_Irq</spirit:name>
+            <spirit:displayName>Interrupt on Delay</spirit:displayName>
+            <spirit:description>Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. 
+</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Err_Irq</spirit:name>
+            <spirit:displayName>Interrupt on Error</spirit:displayName>
+            <spirit:description>Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
+Writing a 1 to this bit will clear it.   
+0 - No error Interrupt.   
+1 - Error interrupt detected.
+</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQThresholdSts</spirit:name>
+            <spirit:displayName>Interrupt Threshold Status</spirit:displayName>
+            <spirit:description>Interrupt Threshold Status. Indicates current interrupt threshold value.
+Note: Applicable only when Scatter Gather is enabled.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQDelaySts</spirit:name>
+            <spirit:displayName>Interrupt Delay Time Status</spirit:displayName>
+            <spirit:description>Interrupt Delay Time Status. Indicates current interrupt delay time value.
+Note: Applicable only when Scatter Gather is enabled.
+</spirit:description>
+            <spirit:bitOffset>24</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_CURDESC</spirit:name>
+          <spirit:displayName>MM2S DMA Current Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>MM2S DMA Current Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x08</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Current_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Current Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
+When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
+On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
+Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">26</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.MM2S_CURDESC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_CURDESC_MSB</spirit:name>
+          <spirit:displayName>MM2S DMA Current Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>MM2S DMA Current Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x0C</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Current_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Current Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
+When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
+On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
+Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.MM2S_CURDESC_MSB" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_TAILDESC</spirit:name>
+          <spirit:displayName>MM2S DMA Tail Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>MM2S DMA Tail Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x10</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Tail_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Tail Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
+When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
+If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
+Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">26</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.MM2S_TAILDESC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_TAILDESC_MSB</spirit:name>
+          <spirit:displayName>MM2S DMA Tail Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>MM2S DMA Tail Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x14</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Tail_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Tail Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
+When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
+If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
+Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.MM2S_TAILDESC_MSB" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_SA</spirit:name>
+          <spirit:displayName>MM2S Source Address Register</spirit:displayName>
+          <spirit:description>MM2S Source Address Register</spirit:description>
+          <spirit:addressOffset>0x18</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Source_Address</spirit:name>
+            <spirit:displayName>Source Address</spirit:displayName>
+            <spirit:description>Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
+Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.MM2S_SA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_SA_MSB</spirit:name>
+          <spirit:displayName>MM2S Source Address Register</spirit:displayName>
+          <spirit:description>MM2S Source Address Register</spirit:description>
+          <spirit:addressOffset>0x1C</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Source_Address</spirit:name>
+            <spirit:displayName>Source Address</spirit:displayName>
+            <spirit:description>Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
+Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.MM2S_SA_MSB" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>MM2S_LENGTH</spirit:name>
+          <spirit:displayName>MM2S DMA Transfer Length Register</spirit:displayName>
+          <spirit:description>MM2S DMA Transfer Length Register</spirit:description>
+          <spirit:addressOffset>0x28</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Length</spirit:name>
+            <spirit:displayName>Length</spirit:displayName>
+            <spirit:description>Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">26</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.MM2S_LENGTH" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>SG_CTL</spirit:name>
+          <spirit:displayName>Scatter/Gather User and Cache Control Register</spirit:displayName>
+          <spirit:description>Scatter/Gather User and Cache Control Register</spirit:description>
+          <spirit:addressOffset>0x2C</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x03</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>SG_CACHE</spirit:name>
+            <spirit:displayName>Scatter/Gather Cache Control</spirit:displayName>
+            <spirit:description>Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">4</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SG_USER</spirit:name>
+            <spirit:displayName>Scatter/Gather User Control</spirit:displayName>
+            <spirit:description>Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.
+</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">4</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.SG_CTL" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_DMACR</spirit:name>
+          <spirit:displayName>S2MM DMA Control Register</spirit:displayName>
+          <spirit:description>S2MM DMA Control Register</spirit:description>
+          <spirit:addressOffset>0x30</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x10002</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>RS</spirit:name>
+            <spirit:displayName>Run/Stop Control</spirit:displayName>
+            <spirit:description>Run / Stop control for controlling running and stopping of the DMA channel.
+  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. 
+  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
+  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
+  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
+  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Reset</spirit:name>
+            <spirit:displayName>Soft Reset</spirit:displayName>
+            <spirit:description>Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
+AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress
+</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Keyhole</spirit:name>
+            <spirit:displayName>Keyhole Write</spirit:displayName>
+            <spirit:description>Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
+This bit is non functional when DMA is used in multichannel mode.
+</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Cyclic_BD_Enable</spirit:name>
+            <spirit:displayName>Cyclic BD Enable</spirit:displayName>
+            <spirit:description>When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
+This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
+</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IOC_IrqEn</spirit:name>
+            <spirit:displayName>Interrupt on Complete (IOC) Interrupt Enable</spirit:displayName>
+            <spirit:description>Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled
+</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Dly_IrqEn</spirit:name>
+            <spirit:displayName>Interrupt on Delay Timer Interrupt Enable</spirit:displayName>
+            <spirit:description>Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.
+</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Err_IrqEn</spirit:name>
+            <spirit:displayName>Interrupt on Error Interrupt Enable</spirit:displayName>
+            <spirit:description>Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled
+</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQThreshold</spirit:name>
+            <spirit:displayName>Interrupt Threshold</spirit:displayName>
+            <spirit:description>Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
+Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
+Note: Applicable only when Scatter Gather is enabled.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQDelay</spirit:name>
+            <spirit:displayName>Interrupt Delay Time Out</spirit:displayName>
+            <spirit:description>Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
+Note: Setting this value to zero disables the delay timer interrupt.
+Note: Applicable only when Scatter Gather is enabled.
+</spirit:description>
+            <spirit:bitOffset>24</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_DMASR</spirit:name>
+          <spirit:displayName>S2MM DMA Status Register</spirit:displayName>
+          <spirit:description>S2MM DMA Status Register</spirit:description>
+          <spirit:addressOffset>0x34</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x10000</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Halted</spirit:name>
+            <spirit:displayName>DMA Channel Halted</spirit:displayName>
+            <spirit:description>DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 
+Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Idle</spirit:name>
+            <spirit:displayName>DMA Channel Idle</spirit:displayName>
+            <spirit:description>DMA Channel Idle. Indicates the state of AXI DMA operations.
+For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
+For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
+</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGIncld</spirit:name>
+            <spirit:displayName>SGIncld</spirit:displayName>
+            <spirit:description>Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
+</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>DMAIntErr</spirit:name>
+            <spirit:displayName>DMA Internal Error</spirit:displayName>
+            <spirit:description>DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
+This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.
+</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>DMASlvErr</spirit:name>
+            <spirit:displayName>DMA Slave Error</spirit:displayName>
+            <spirit:description>DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.
+</spirit:description>
+            <spirit:bitOffset>5</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>DMADecErr</spirit:name>
+            <spirit:displayName>DMA Decode Error</spirit:displayName>
+            <spirit:description>DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGIntErr</spirit:name>
+            <spirit:displayName>Scatter Gather Internal Error</spirit:displayName>
+            <spirit:description>Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit� already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. 
+</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGSlvErr</spirit:name>
+            <spirit:displayName>Scatter Gather Slave Error</spirit:displayName>
+            <spirit:description>Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. 
+</spirit:description>
+            <spirit:bitOffset>9</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>SGDecErr</spirit:name>
+            <spirit:displayName>Scatter Gather Decode Error</spirit:displayName>
+            <spirit:description>Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. 
+</spirit:description>
+            <spirit:bitOffset>10</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IOC_Irq</spirit:name>
+            <spirit:displayName>Interrupt on Complete</spirit:displayName>
+            <spirit:description>Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
+</spirit:description>
+            <spirit:bitOffset>12</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Dly_Irq</spirit:name>
+            <spirit:displayName>Interrupt on Delay</spirit:displayName>
+            <spirit:description>Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. 
+</spirit:description>
+            <spirit:bitOffset>13</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>Err_Irq</spirit:name>
+            <spirit:displayName>Interrupt on Error</spirit:displayName>
+            <spirit:description>Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
+Writing a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.
+</spirit:description>
+            <spirit:bitOffset>14</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>oneToClear</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQThresholdSts</spirit:name>
+            <spirit:displayName>Interrupt Threshold Status</spirit:displayName>
+            <spirit:description>Interrupt Threshold Status. Indicates current interrupt threshold value.
+Note: Applicable only when Scatter Gather is enabled.
+</spirit:description>
+            <spirit:bitOffset>16</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>IRQDelaySts</spirit:name>
+            <spirit:displayName>Interrupt Delay Time Status</spirit:displayName>
+            <spirit:description>Interrupt Delay Time Status. Indicates current interrupt delay time value.
+Note: Applicable only when Scatter Gather is enabled.
+</spirit:description>
+            <spirit:bitOffset>24</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">8</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_CURDESC</spirit:name>
+          <spirit:displayName>S2MM DMA Current Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>S2MM DMA Current Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x38</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Current_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Current Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
+When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
+On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
+Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). 
+Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">26</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.S2MM_CURDESC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_CURDESC_MSB</spirit:name>
+          <spirit:displayName>S2MM DMA Current Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>S2MM DMA Current Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x3C</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Current_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Current Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
+When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
+On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
+Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.S2MM_CURDESC_MSB" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_TAILDESC</spirit:name>
+          <spirit:displayName>S2MM DMA Tail Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>S2MM DMA Tail Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x40</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Tail_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Tail Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
+When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
+If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
+Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. 
+Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
+</spirit:description>
+            <spirit:bitOffset>6</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">26</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.S2MM_TAILDESC" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_TAILDESC_MSB</spirit:name>
+          <spirit:displayName>S2MM DMA Tail Descriptor Pointer Register</spirit:displayName>
+          <spirit:description>S2MM DMA Tail Descriptor Pointer Register</spirit:description>
+          <spirit:addressOffset>0x44</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Tail_Descriptor_Pointer</spirit:name>
+            <spirit:displayName>Tail Descriptor Pointer</spirit:displayName>
+            <spirit:description>Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
+When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
+If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
+Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.S2MM_TAILDESC_MSB" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=1)">true</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_DA</spirit:name>
+          <spirit:displayName>S2MM DMA Destination Address Register</spirit:displayName>
+          <spirit:description>S2MM DMA Destination Address Register</spirit:description>
+          <spirit:addressOffset>0x48</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Destination_Address</spirit:name>
+            <spirit:displayName>Destination Address</spirit:displayName>
+            <spirit:description>Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
+Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.S2MM_DA" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_DA_MSB</spirit:name>
+          <spirit:displayName>S2MM Destination Address Register</spirit:displayName>
+          <spirit:description>S2MM Destination Address Register</spirit:description>
+          <spirit:addressOffset>0x4C</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Destination_Address</spirit:name>
+            <spirit:displayName>Destination Address</spirit:displayName>
+            <spirit:description>Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
+Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:vendorExtensions>
+            <xilinx:registerInfo>
+              <xilinx:enablement>
+                <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.S_AXI_LITE.REG.S2MM_DA_MSB" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_SG&apos;))=0)">false</xilinx:isEnabled>
+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>S2MM_LENGTH</spirit:name>
+          <spirit:displayName>S2MM DMA Transfer Length Register</spirit:displayName>
+          <spirit:description>S2MM DMA Transfer Length Register</spirit:description>
+          <spirit:addressOffset>0x58</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:volatile>true</spirit:volatile>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0x0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Length</spirit:name>
+            <spirit:displayName>Length</spirit:displayName>
+            <spirit:description>Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
+At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
+Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. 
+</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">26</spirit:bitWidth>
+            <spirit:volatile>true</spirit:volatile>
+            <spirit:access>read-write</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+              </xilinx:enablement>
+            </xilinx:registerInfo>
+          </spirit:vendorExtensions>
+        </spirit:register>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
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+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>axi_dma</spirit:modelName>
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+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>axi_dma_tstvec</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:presence>illegal</xilinx:presence>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="INTEGER">
+        <spirit:name>C_S_AXI_LITE_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S_AXI_LITE_ADDR_WIDTH" spirit:choiceRef="choice_list_6330c9d2">10</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_S_AXI_LITE_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S_AXI_LITE_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_DLYTMR_RESOLUTION</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DLYTMR_RESOLUTION" spirit:minimum="1" spirit:maximum="100000" spirit:rangeType="long">125</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRMRY_IS_ACLK_ASYNC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRMRY_IS_ACLK_ASYNC" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_MULTI_CHANNEL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_MULTI_CHANNEL" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_NUM_MM2S_CHANNELS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_MM2S_CHANNELS" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_NUM_S2MM_CHANNELS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_S2MM_CHANNELS" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INCLUDE_SG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLUDE_SG" spirit:choiceRef="choice_list_8af5a703">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_SG_INCLUDE_STSCNTRL_STRM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SG_INCLUDE_STSCNTRL_STRM" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_SG_USE_STSAPP_LENGTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SG_USE_STSAPP_LENGTH" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_SG_LENGTH_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SG_LENGTH_WIDTH" spirit:minimum="8" spirit:maximum="26" spirit:rangeType="long">16</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_M_AXI_SG_ADDR_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_SG_ADDR_WIDTH" spirit:order="5950" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_M_AXI_SG_DATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_M_AXI_SG_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_MM2S&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_SG_INCLUDE_STSCNTRL_STRM&apos;)) = 1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_S_AXIS_S2MM_STS_TDATA_WIDTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXIS_S2MM_STS_TDATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="MODELPARAM_ENABLEMENT.C_S_AXIS_S2MM_STS_TDATA_WIDTH" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_INCLUDE_S2MM&apos;)) = 1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_SG_INCLUDE_STSCNT