Working 10G hw for ZCu106
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# Copyright 2020 Xilinx Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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## enable tx by forcing 0 from design. sfp0,1,2,3 => a12, a13, b13, c13
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set_property PACKAGE_PIN AE22 [get_ports {sfp_tx_dis[0]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {sfp_tx_dis[0]}]
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#sfp2
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set_property PACKAGE_PIN AA2 [get_ports gt_rx_gt_port_0_p]
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set_property PACKAGE_PIN AA1 [get_ports gt_rx_gt_port_0_n]
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set_property PACKAGE_PIN Y4 [get_ports gt_tx_gt_port_0_p]
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set_property PACKAGE_PIN Y3 [get_ports gt_tx_gt_port_0_n]
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#USER_MGT_SI570_CLOCK2_C_P
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set_property PACKAGE_PIN U10 [get_ports gt_ref_clk_clk_p]
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create_clock -period 6.400 -name gt_ref_clk [get_ports gt_ref_clk_clk_p]
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#LED 2 and 3
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# led 0 .. 7 => ag14, af13, ae13, aj14, aj15, ah13, ah14, al12
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#set_property IOSTANDARD LVCMOS25 [get_ports *led]
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#set_property PACKAGE_PIN AF13 [get_ports axil_reset_led]
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#set_property PACKAGE_PIN AJ14 [get_ports {axi_lite_clk_led[0]}]
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#set_property PACKAGE_PIN AH13 [get_ports {mgt_clk_led[0]}]
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#set_property PACKAGE_PIN AH14 [get_ports {rx_clk_led[0]}]
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#set_property PACKAGE_PIN AG14 [get_ports {sys_reset_led}]
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#set_property PACKAGE_PIN AL12 [get_ports {gtwiz_rst_led}]
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#CR 965826
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 6.40
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 6.40
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_0] -datapath_only 6.40
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0] -datapath_only 6.40
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#set_max_delay -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 10.000
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#set_max_delay -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 10.000
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version:1
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3130:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:33:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636f6e73747261696e7473:32:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:34:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:33:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6578706f72745f6861726477617265:32:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f6d6967:32:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:34:00:00
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eof:1898407456
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version:1
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eof:503755933
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version:1
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6d6f64655f636f756e7465727c4755494d6f6465:4
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eof:
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version:1
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||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:5b7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||||
|
eof:3126106825
|
||||||
|
|
@ -0,0 +1,3 @@
|
||||||
|
version:1
|
||||||
|
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
|
||||||
|
eof:2511430288
|
||||||
|
|
@ -0,0 +1,94 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" ?>
|
||||||
|
<document>
|
||||||
|
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||||
|
The structure and the elements are likely to change over the next few releases.
|
||||||
|
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||||
|
<application name="pa" timeStamp="Fri Oct 20 16:41:35 2023">
|
||||||
|
<section name="Project Information" visible="false">
|
||||||
|
<property name="ProjectID" value="e44f545a56b248f4976b49478b84eb20" type="ProjectID"/>
|
||||||
|
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||||
|
</section>
|
||||||
|
<section name="PlanAhead Usage" visible="true">
|
||||||
|
<item name="Project Data">
|
||||||
|
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||||
|
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||||
|
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||||
|
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||||
|
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||||
|
</item>
|
||||||
|
<item name="Java Command Handlers">
|
||||||
|
<property name="AutoConnectTarget" value="7" type="JavaHandler"/>
|
||||||
|
<property name="CustomizeRSBBlock" value="6" type="JavaHandler"/>
|
||||||
|
<property name="ExitApp" value="4" type="JavaHandler"/>
|
||||||
|
<property name="LaunchOpenTarget" value="2" type="JavaHandler"/>
|
||||||
|
<property name="LaunchProgramFpga" value="7" type="JavaHandler"/>
|
||||||
|
<property name="NewExportHardware" value="2" type="JavaHandler"/>
|
||||||
|
<property name="OpenHardwareManager" value="19" type="JavaHandler"/>
|
||||||
|
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||||
|
<property name="OpenRecentTarget" value="14" type="JavaHandler"/>
|
||||||
|
<property name="ProgramDevice" value="9" type="JavaHandler"/>
|
||||||
|
<property name="RefreshServer" value="2" type="JavaHandler"/>
|
||||||
|
<property name="RefreshTarget" value="1" type="JavaHandler"/>
|
||||||
|
<property name="RunBitgen" value="2" type="JavaHandler"/>
|
||||||
|
<property name="RunImplementation" value="2" type="JavaHandler"/>
|
||||||
|
<property name="RunSynthesis" value="3" type="JavaHandler"/>
|
||||||
|
<property name="SaveRSBDesign" value="1" type="JavaHandler"/>
|
||||||
|
<property name="ShowView" value="1" type="JavaHandler"/>
|
||||||
|
<property name="ToolsSettings" value="1" type="JavaHandler"/>
|
||||||
|
<property name="ViewTaskImplementation" value="2" type="JavaHandler"/>
|
||||||
|
<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
|
||||||
|
</item>
|
||||||
|
<item name="Gui Handlers">
|
||||||
|
<property name="BaseDialog_OK" value="10" type="GuiHandlerData"/>
|
||||||
|
<property name="CmdMsgDialog_OK" value="15" type="GuiHandlerData"/>
|
||||||
|
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiHandlerData"/>
|
||||||
|
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="3" type="GuiHandlerData"/>
|
||||||
|
<property name="ExportPlatformWizard_FIXED_POST_IMPL" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="ExportPlatformWizard_OUTPUT_XSA_NAME" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="22" type="GuiHandlerData"/>
|
||||||
|
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="40" type="GuiHandlerData"/>
|
||||||
|
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="8" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_CHECKPOINT" value="3" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_EXPORT" value="4" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_FILE" value="8" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_IMPORT" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
|
||||||
|
<property name="MainMenuMgr_TEXT_EDITOR" value="5" type="GuiHandlerData"/>
|
||||||
|
<property name="MainToolbarMgr_RUN" value="3" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="7" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_EXPORT_HARDWARE" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_OPEN_TARGET_WIZARD" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_REFRESH_SERVER" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_REFRESH_TARGET" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_RUN_BITGEN" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
|
||||||
|
<property name="PAViews_DASHBOARD" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="PAViews_MIG" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="PAViews_PROJECT_SUMMARY" value="4" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSPanelClockingPage_PLL_OPTIONS" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSPanelClockingPage_TABBED_PANE" value="6" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSPanelDDRPage_OTHER_OPTIONS" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSPanelMainPage_SWITCH_TO_ADVANCED_MODE" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSTreeTablePanelBuilder_ADV_CLK_TREE" value="47" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSTreeTablePanelBuilder_CLK_TREE" value="7" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSTreeTablePanelBuilder_GENERAL_TREE" value="12" type="GuiHandlerData"/>
|
||||||
|
<property name="PSSTreeTablePanelBuilder_MIO_TREE" value="8" type="GuiHandlerData"/>
|
||||||
|
<property name="ProgramFpgaDialog_PROGRAM" value="7" type="GuiHandlerData"/>
|
||||||
|
<property name="RunGadget_SHOW_ERROR_AND_CRITICAL_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="SettingsDialog_PROJECT_TREE" value="6" type="GuiHandlerData"/>
|
||||||
|
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
|
||||||
|
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="TclConsoleView_COPY" value="1" type="GuiHandlerData"/>
|
||||||
|
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="5" type="GuiHandlerData"/>
|
||||||
|
</item>
|
||||||
|
<item name="Other">
|
||||||
|
<property name="GuiMode" value="50" type="GuiMode"/>
|
||||||
|
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||||
|
<property name="TclMode" value="32" type="TclMode"/>
|
||||||
|
</item>
|
||||||
|
</section>
|
||||||
|
</application>
|
||||||
|
</document>
|
||||||
|
|
@ -0,0 +1,44 @@
|
||||||
|
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||||
|
//--------------------------------------------------------------------------------
|
||||||
|
//Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
|
||||||
|
//Date : Fri Oct 20 12:44:41 2023
|
||||||
|
//Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200)
|
||||||
|
//Command : generate_target pl_eth_10g_wrapper.bd
|
||||||
|
//Design : pl_eth_10g_wrapper
|
||||||
|
//Purpose : IP block netlist
|
||||||
|
//--------------------------------------------------------------------------------
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module pl_eth_10g_wrapper
|
||||||
|
(gt_ref_clk_clk_n,
|
||||||
|
gt_ref_clk_clk_p,
|
||||||
|
gt_rx_gt_port_0_n,
|
||||||
|
gt_rx_gt_port_0_p,
|
||||||
|
gt_tx_gt_port_0_n,
|
||||||
|
gt_tx_gt_port_0_p,
|
||||||
|
sfp_tx_dis);
|
||||||
|
input gt_ref_clk_clk_n;
|
||||||
|
input gt_ref_clk_clk_p;
|
||||||
|
input gt_rx_gt_port_0_n;
|
||||||
|
input gt_rx_gt_port_0_p;
|
||||||
|
output gt_tx_gt_port_0_n;
|
||||||
|
output gt_tx_gt_port_0_p;
|
||||||
|
output [0:0]sfp_tx_dis;
|
||||||
|
|
||||||
|
wire gt_ref_clk_clk_n;
|
||||||
|
wire gt_ref_clk_clk_p;
|
||||||
|
wire gt_rx_gt_port_0_n;
|
||||||
|
wire gt_rx_gt_port_0_p;
|
||||||
|
wire gt_tx_gt_port_0_n;
|
||||||
|
wire gt_tx_gt_port_0_p;
|
||||||
|
wire [0:0]sfp_tx_dis;
|
||||||
|
|
||||||
|
pl_eth_10g pl_eth_10g_i
|
||||||
|
(.gt_ref_clk_clk_n(gt_ref_clk_clk_n),
|
||||||
|
.gt_ref_clk_clk_p(gt_ref_clk_clk_p),
|
||||||
|
.gt_rx_gt_port_0_n(gt_rx_gt_port_0_n),
|
||||||
|
.gt_rx_gt_port_0_p(gt_rx_gt_port_0_p),
|
||||||
|
.gt_tx_gt_port_0_n(gt_tx_gt_port_0_n),
|
||||||
|
.gt_tx_gt_port_0_p(gt_tx_gt_port_0_p),
|
||||||
|
.sfp_tx_dis(sfp_tx_dis));
|
||||||
|
endmodule
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,33 @@
|
||||||
|
###############################################################################################################
|
||||||
|
# Core-Level Timing Constraints for axi_clock_converter Component "pl_eth_10g_auto_cc_0"
|
||||||
|
###############################################################################################################
|
||||||
|
#
|
||||||
|
# This component is configured to perform asynchronous clock-domain-crossing.
|
||||||
|
# In order for these core-level constraints to work properly,
|
||||||
|
# the following rules apply to your system-level timing constraints:
|
||||||
|
# 1. Each of the nets connected to the s_axi_aclk and m_axi_aclk ports of this component
|
||||||
|
# must have exactly one clock defined on it, using either
|
||||||
|
# a) a create_clock command on a top-level clock pin specified in your system XDC file, or
|
||||||
|
# b) a create_generated_clock command, typically generated automatically by a core
|
||||||
|
# producing a derived clock signal.
|
||||||
|
# 2. The s_axi_aclk and m_axi_aclk ports of this component should not be connected to the
|
||||||
|
# same clock source.
|
||||||
|
#
|
||||||
|
set s_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
|
||||||
|
set m_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance m_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
|
||||||
|
set_false_path -from [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == O}]
|
||||||
|
set_false_path -from [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == O}]
|
||||||
|
create_waiver -internal -scope -type CDC -id CDC-10 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
|
||||||
|
-description {Waiving CDC-10 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock. Hence there should not be any issues cause by this logic}
|
||||||
|
|
||||||
|
create_waiver -internal -scope -type CDC -id CDC-11 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
|
||||||
|
-description {Waiving CDC-11 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock. Hence there should not be any issues cause by this logic}
|
||||||
|
|
||||||
|
create_waiver -internal -scope -type CDC -id CDC-15 -user axi_clock_converter -tags "1024442" -from [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_*/RAM*/CLK]\
|
||||||
|
-to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg*/D]\
|
||||||
|
-description {Waiving CDC-15 Timing constraints are processed during implementation, not synthesis. The xdc is marked only to be used during implementation, as advised by the XDC folks at the time.}
|
||||||
|
|
||||||
|
create_waiver -internal -scope -type METHODOLOGY -id {LUTAR-1} -user "axi_clock_converter" -desc {the pathway is completely within fifo-gen, and that path is present dual-clock usage}\
|
||||||
|
-tags "1024444"\
|
||||||
|
-objects [get_cells -hierarchical "*gen_clock_conv.gen_async_conv.asyncfifo_axi*"] \
|
||||||
|
-objects [get_pins -hierarchical * -filter "(NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg*/PRE) || (NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg*/PRE)"]
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,460 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_CC_0_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_CC_0_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_cc_0_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_cc_0 : public pl_eth_10g_auto_cc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_CC_0_H_
|
||||||
|
|
@ -0,0 +1,290 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
|
||||||
|
// IP Revision: 21
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_cc_0 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_aclk,
|
||||||
|
m_axi_aresetn,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NU\
|
||||||
|
M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
|
||||||
|
input wire m_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
|
||||||
|
input wire m_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [127 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_clock_converter_v2_1_21_axi_clock_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_AXI_DATA_WIDTH(128),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(1),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(0),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(32'H00000000),
|
||||||
|
.s_axi_awlen(8'H00),
|
||||||
|
.s_axi_awsize(3'H0),
|
||||||
|
.s_axi_awburst(2'H1),
|
||||||
|
.s_axi_awlock(1'H0),
|
||||||
|
.s_axi_awcache(4'H0),
|
||||||
|
.s_axi_awprot(3'H0),
|
||||||
|
.s_axi_awregion(4'H0),
|
||||||
|
.s_axi_awqos(4'H0),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(1'H0),
|
||||||
|
.s_axi_awready(),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(128'H00000000000000000000000000000000),
|
||||||
|
.s_axi_wstrb(16'HFFFF),
|
||||||
|
.s_axi_wlast(1'H1),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(1'H0),
|
||||||
|
.s_axi_wready(),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(),
|
||||||
|
.s_axi_bready(1'H0),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(m_axi_aclk),
|
||||||
|
.m_axi_aresetn(m_axi_aresetn),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(),
|
||||||
|
.m_axi_awready(1'H0),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(),
|
||||||
|
.m_axi_wstrb(),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(),
|
||||||
|
.m_axi_wready(1'H0),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(2'H0),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(1'H0),
|
||||||
|
.m_axi_bready(),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_cc_0_sc.h"
|
||||||
|
|
||||||
|
#include "axi_clock_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0_sc::pl_eth_10g_auto_cc_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_cc_0", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_AXI_ID_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_AXI_DATA_WIDTH", "128");
|
||||||
|
model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
|
||||||
|
model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
|
||||||
|
model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "1");
|
||||||
|
model_param_props.addLong("C_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
|
||||||
|
model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "0");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||||
|
model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_clock_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
S_TARGET_rd_socket = mp_impl->S_TARGET_rd_socket;
|
||||||
|
S_TARGET_wr_socket = mp_impl->S_TARGET_wr_socket;
|
||||||
|
M_INITIATOR_rd_socket = mp_impl->M_INITIATOR_rd_socket;
|
||||||
|
M_INITIATOR_wr_socket = mp_impl->M_INITIATOR_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0_sc::~pl_eth_10g_auto_cc_0_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_CC_0_SC_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_CC_0_SC_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
class axi_clock_converter;
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_cc_0_sc : public sc_core::sc_module
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0_sc(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_0_sc();
|
||||||
|
|
||||||
|
// module socket-to-socket AXI TLM interfaces
|
||||||
|
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
|
||||||
|
|
||||||
|
// module socket-to-socket TLM interfaces
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
axi_clock_converter* mp_impl;
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_0_sc(const pl_eth_10g_auto_cc_0_sc&);
|
||||||
|
const pl_eth_10g_auto_cc_0_sc& operator=(const pl_eth_10g_auto_cc_0_sc&);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_CC_0_SC_H_
|
||||||
|
|
@ -0,0 +1,194 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
// Filename: pl_eth_10g_auto_cc_0_stub.sv
|
||||||
|
// Description: This HDL file is intended to be used with following simulators only:
|
||||||
|
//
|
||||||
|
// Vivado Simulator (XSim)
|
||||||
|
// Cadence Xcelium Simulator
|
||||||
|
// Aldec Riviera-PRO Simulator
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
`ifdef XILINX_SIMULATOR
|
||||||
|
|
||||||
|
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||||
|
`define XILINX_SIMULATOR_BITASBOOL
|
||||||
|
typedef bit bit_as_bool;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_cc_0 (
|
||||||
|
input bit_as_bool s_axi_aclk,
|
||||||
|
input bit_as_bool s_axi_aresetn,
|
||||||
|
input bit [31 : 0] s_axi_araddr,
|
||||||
|
input bit [7 : 0] s_axi_arlen,
|
||||||
|
input bit [2 : 0] s_axi_arsize,
|
||||||
|
input bit [1 : 0] s_axi_arburst,
|
||||||
|
input bit [0 : 0] s_axi_arlock,
|
||||||
|
input bit [3 : 0] s_axi_arcache,
|
||||||
|
input bit [2 : 0] s_axi_arprot,
|
||||||
|
input bit [3 : 0] s_axi_arregion,
|
||||||
|
input bit [3 : 0] s_axi_arqos,
|
||||||
|
input bit_as_bool s_axi_arvalid,
|
||||||
|
output bit_as_bool s_axi_arready,
|
||||||
|
output bit [127 : 0] s_axi_rdata,
|
||||||
|
output bit [1 : 0] s_axi_rresp,
|
||||||
|
output bit_as_bool s_axi_rlast,
|
||||||
|
output bit_as_bool s_axi_rvalid,
|
||||||
|
input bit_as_bool s_axi_rready,
|
||||||
|
input bit_as_bool m_axi_aclk,
|
||||||
|
input bit_as_bool m_axi_aresetn,
|
||||||
|
output bit [31 : 0] m_axi_araddr,
|
||||||
|
output bit [7 : 0] m_axi_arlen,
|
||||||
|
output bit [2 : 0] m_axi_arsize,
|
||||||
|
output bit [1 : 0] m_axi_arburst,
|
||||||
|
output bit [0 : 0] m_axi_arlock,
|
||||||
|
output bit [3 : 0] m_axi_arcache,
|
||||||
|
output bit [2 : 0] m_axi_arprot,
|
||||||
|
output bit [3 : 0] m_axi_arregion,
|
||||||
|
output bit [3 : 0] m_axi_arqos,
|
||||||
|
output bit_as_bool m_axi_arvalid,
|
||||||
|
input bit_as_bool m_axi_arready,
|
||||||
|
input bit [127 : 0] m_axi_rdata,
|
||||||
|
input bit [1 : 0] m_axi_rresp,
|
||||||
|
input bit_as_bool m_axi_rlast,
|
||||||
|
input bit_as_bool m_axi_rvalid,
|
||||||
|
output bit_as_bool m_axi_rready
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef XCELIUM
|
||||||
|
(* XMSC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_cc_0 (s_axi_aclk,s_axi_aresetn,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
(* integer foreign = "SystemC";
|
||||||
|
*);
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
input bit m_axi_aclk;
|
||||||
|
input bit m_axi_aresetn;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [127 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef RIVIERA
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_cc_0 (s_axi_aclk,s_axi_aresetn,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
input bit m_axi_aclk;
|
||||||
|
input bit m_axi_aresetn;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [127 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,292 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
|
||||||
|
// IP Revision: 21
|
||||||
|
|
||||||
|
(* X_CORE_INFO = "axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2" *)
|
||||||
|
(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_cc_0,axi_clock_converter_v2_1_21_axi_clock_converter,{}" *)
|
||||||
|
(* CORE_GENERATION_INFO = "pl_eth_10g_auto_cc_0,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUS\
|
||||||
|
ER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=0,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=3}" *)
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_cc_0 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_aclk,
|
||||||
|
m_axi_aresetn,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NU\
|
||||||
|
M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
|
||||||
|
input wire m_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
|
||||||
|
input wire m_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [127 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_clock_converter_v2_1_21_axi_clock_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_AXI_DATA_WIDTH(128),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(1),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(0),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(32'H00000000),
|
||||||
|
.s_axi_awlen(8'H00),
|
||||||
|
.s_axi_awsize(3'H0),
|
||||||
|
.s_axi_awburst(2'H1),
|
||||||
|
.s_axi_awlock(1'H0),
|
||||||
|
.s_axi_awcache(4'H0),
|
||||||
|
.s_axi_awprot(3'H0),
|
||||||
|
.s_axi_awregion(4'H0),
|
||||||
|
.s_axi_awqos(4'H0),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(1'H0),
|
||||||
|
.s_axi_awready(),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(128'H00000000000000000000000000000000),
|
||||||
|
.s_axi_wstrb(16'HFFFF),
|
||||||
|
.s_axi_wlast(1'H1),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(1'H0),
|
||||||
|
.s_axi_wready(),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(),
|
||||||
|
.s_axi_bready(1'H0),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(m_axi_aclk),
|
||||||
|
.m_axi_aresetn(m_axi_aresetn),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(),
|
||||||
|
.m_axi_awready(1'H0),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(),
|
||||||
|
.m_axi_wstrb(),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(),
|
||||||
|
.m_axi_wready(1'H0),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(2'H0),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(1'H0),
|
||||||
|
.m_axi_bready(),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
#include "axi_clock_converter.h"
|
||||||
|
#include <sstream>
|
||||||
|
|
||||||
|
axi_clock_converter::axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
|
||||||
|
sc_module(module_name) {
|
||||||
|
M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
|
||||||
|
M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
|
||||||
|
S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
|
||||||
|
S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
|
||||||
|
P1 = new xtlm::xtlm_aximm_passthru_module("P1");
|
||||||
|
P2 = new xtlm::xtlm_aximm_passthru_module("P2");
|
||||||
|
P1->initiator_socket->bind(*M_INITIATOR_rd_socket);
|
||||||
|
P2->initiator_socket->bind(*M_INITIATOR_wr_socket);
|
||||||
|
S_TARGET_rd_socket->bind(*(P1->target_socket));
|
||||||
|
S_TARGET_wr_socket->bind(*(P2->target_socket));
|
||||||
|
}
|
||||||
|
axi_clock_converter::~axi_clock_converter() {
|
||||||
|
delete M_INITIATOR_wr_socket;
|
||||||
|
delete M_INITIATOR_rd_socket;
|
||||||
|
delete S_TARGET_wr_socket;
|
||||||
|
delete S_TARGET_rd_socket;
|
||||||
|
delete P1;
|
||||||
|
delete P2;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
#ifndef _axi_clock_converter_
|
||||||
|
#define _axi_clock_converter_
|
||||||
|
#include <xtlm.h>
|
||||||
|
#include <utils/xtlm_aximm_passthru_module.h>
|
||||||
|
#include <systemc>
|
||||||
|
|
||||||
|
class axi_clock_converter:public sc_module{
|
||||||
|
public:
|
||||||
|
axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||||
|
virtual ~axi_clock_converter();
|
||||||
|
SC_HAS_PROCESS(axi_clock_converter);
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
|
||||||
|
sc_in<bool> s_axi_aclk;
|
||||||
|
sc_in<bool> s_axi_aresetn;
|
||||||
|
sc_in<bool> m_axi_aclk;
|
||||||
|
sc_in<bool> m_axi_aresetn;
|
||||||
|
|
||||||
|
private:
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P1;
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P2;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,33 @@
|
||||||
|
###############################################################################################################
|
||||||
|
# Core-Level Timing Constraints for axi_clock_converter Component "pl_eth_10g_auto_cc_1"
|
||||||
|
###############################################################################################################
|
||||||
|
#
|
||||||
|
# This component is configured to perform asynchronous clock-domain-crossing.
|
||||||
|
# In order for these core-level constraints to work properly,
|
||||||
|
# the following rules apply to your system-level timing constraints:
|
||||||
|
# 1. Each of the nets connected to the s_axi_aclk and m_axi_aclk ports of this component
|
||||||
|
# must have exactly one clock defined on it, using either
|
||||||
|
# a) a create_clock command on a top-level clock pin specified in your system XDC file, or
|
||||||
|
# b) a create_generated_clock command, typically generated automatically by a core
|
||||||
|
# producing a derived clock signal.
|
||||||
|
# 2. The s_axi_aclk and m_axi_aclk ports of this component should not be connected to the
|
||||||
|
# same clock source.
|
||||||
|
#
|
||||||
|
set s_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance s_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
|
||||||
|
set m_ram_cells [filter [all_fanout -from [get_ports -scoped_to_current_instance m_axi_aclk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]
|
||||||
|
set_false_path -from [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $s_ram_cells -filter {REF_PIN_NAME == O}]
|
||||||
|
set_false_path -from [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == CLK}] -through [get_pins -of $m_ram_cells -filter {REF_PIN_NAME == O}]
|
||||||
|
create_waiver -internal -scope -type CDC -id CDC-10 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
|
||||||
|
-description {Waiving CDC-10 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock. Hence there should not be any issues cause by this logic}
|
||||||
|
|
||||||
|
create_waiver -internal -scope -type CDC -id CDC-11 -user axi_clock_converter -tags "1024161" -to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_*_reg2_inst/arststages_ff_reg[0]/PRE]\
|
||||||
|
-description {Waiving CDC-11 Although there is combo logic going into FIFO Gen reset, the expectation/rule is that the reset signal will be held for 1 clk cycles on the slowest clock. Hence there should not be any issues cause by this logic}
|
||||||
|
|
||||||
|
create_waiver -internal -scope -type CDC -id CDC-15 -user axi_clock_converter -tags "1024442" -from [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_*/RAM*/CLK]\
|
||||||
|
-to [get_pins -quiet *gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg*/D]\
|
||||||
|
-description {Waiving CDC-15 Timing constraints are processed during implementation, not synthesis. The xdc is marked only to be used during implementation, as advised by the XDC folks at the time.}
|
||||||
|
|
||||||
|
create_waiver -internal -scope -type METHODOLOGY -id {LUTAR-1} -user "axi_clock_converter" -desc {the pathway is completely within fifo-gen, and that path is present dual-clock usage}\
|
||||||
|
-tags "1024444"\
|
||||||
|
-objects [get_cells -hierarchical "*gen_clock_conv.gen_async_conv.asyncfifo_axi*"] \
|
||||||
|
-objects [get_pins -hierarchical * -filter "(NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg*/PRE) || (NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg*/PRE)"]
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,490 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_CC_1_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_CC_1_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_cc_1_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_cc_1 : public pl_eth_10g_auto_cc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< bool > m_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > m_axi_aresetn;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_rd_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_CC_1_H_
|
||||||
|
|
@ -0,0 +1,308 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
|
||||||
|
// IP Revision: 21
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_cc_1 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
m_axi_aclk,
|
||||||
|
m_axi_aresetn,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [127 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [15 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
|
||||||
|
M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
|
||||||
|
input wire m_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
|
||||||
|
input wire m_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
|
||||||
|
axi_clock_converter_v2_1_21_axi_clock_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_AXI_DATA_WIDTH(128),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(1),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(0),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(32'H00000000),
|
||||||
|
.s_axi_arlen(8'H00),
|
||||||
|
.s_axi_arsize(3'H0),
|
||||||
|
.s_axi_arburst(2'H1),
|
||||||
|
.s_axi_arlock(1'H0),
|
||||||
|
.s_axi_arcache(4'H0),
|
||||||
|
.s_axi_arprot(3'H0),
|
||||||
|
.s_axi_arregion(4'H0),
|
||||||
|
.s_axi_arqos(4'H0),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(1'H0),
|
||||||
|
.s_axi_arready(),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(),
|
||||||
|
.s_axi_rresp(),
|
||||||
|
.s_axi_rlast(),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(),
|
||||||
|
.s_axi_rready(1'H0),
|
||||||
|
.m_axi_aclk(m_axi_aclk),
|
||||||
|
.m_axi_aresetn(m_axi_aresetn),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(),
|
||||||
|
.m_axi_arlen(),
|
||||||
|
.m_axi_arsize(),
|
||||||
|
.m_axi_arburst(),
|
||||||
|
.m_axi_arlock(),
|
||||||
|
.m_axi_arcache(),
|
||||||
|
.m_axi_arprot(),
|
||||||
|
.m_axi_arregion(),
|
||||||
|
.m_axi_arqos(),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(),
|
||||||
|
.m_axi_arready(1'H0),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(128'H00000000000000000000000000000000),
|
||||||
|
.m_axi_rresp(2'H0),
|
||||||
|
.m_axi_rlast(1'H1),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(1'H0),
|
||||||
|
.m_axi_rready()
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,97 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_cc_1_sc.h"
|
||||||
|
|
||||||
|
#include "axi_clock_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1_sc::pl_eth_10g_auto_cc_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_cc_1", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_AXI_ID_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_AXI_DATA_WIDTH", "128");
|
||||||
|
model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
|
||||||
|
model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
|
||||||
|
model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "1");
|
||||||
|
model_param_props.addLong("C_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
|
||||||
|
model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "0");
|
||||||
|
model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_clock_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
S_TARGET_rd_socket = mp_impl->S_TARGET_rd_socket;
|
||||||
|
S_TARGET_wr_socket = mp_impl->S_TARGET_wr_socket;
|
||||||
|
M_INITIATOR_rd_socket = mp_impl->M_INITIATOR_rd_socket;
|
||||||
|
M_INITIATOR_wr_socket = mp_impl->M_INITIATOR_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1_sc::~pl_eth_10g_auto_cc_1_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_CC_1_SC_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_CC_1_SC_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
class axi_clock_converter;
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_cc_1_sc : public sc_core::sc_module
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1_sc(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_cc_1_sc();
|
||||||
|
|
||||||
|
// module socket-to-socket AXI TLM interfaces
|
||||||
|
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
|
||||||
|
|
||||||
|
// module socket-to-socket TLM interfaces
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
axi_clock_converter* mp_impl;
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_cc_1_sc(const pl_eth_10g_auto_cc_1_sc&);
|
||||||
|
const pl_eth_10g_auto_cc_1_sc& operator=(const pl_eth_10g_auto_cc_1_sc&);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_CC_1_SC_H_
|
||||||
|
|
@ -0,0 +1,212 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
// Filename: pl_eth_10g_auto_cc_1_stub.sv
|
||||||
|
// Description: This HDL file is intended to be used with following simulators only:
|
||||||
|
//
|
||||||
|
// Vivado Simulator (XSim)
|
||||||
|
// Cadence Xcelium Simulator
|
||||||
|
// Aldec Riviera-PRO Simulator
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
`ifdef XILINX_SIMULATOR
|
||||||
|
|
||||||
|
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||||
|
`define XILINX_SIMULATOR_BITASBOOL
|
||||||
|
typedef bit bit_as_bool;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_cc_1 (
|
||||||
|
input bit_as_bool s_axi_aclk,
|
||||||
|
input bit_as_bool s_axi_aresetn,
|
||||||
|
input bit [31 : 0] s_axi_awaddr,
|
||||||
|
input bit [7 : 0] s_axi_awlen,
|
||||||
|
input bit [2 : 0] s_axi_awsize,
|
||||||
|
input bit [1 : 0] s_axi_awburst,
|
||||||
|
input bit [0 : 0] s_axi_awlock,
|
||||||
|
input bit [3 : 0] s_axi_awcache,
|
||||||
|
input bit [2 : 0] s_axi_awprot,
|
||||||
|
input bit [3 : 0] s_axi_awregion,
|
||||||
|
input bit [3 : 0] s_axi_awqos,
|
||||||
|
input bit_as_bool s_axi_awvalid,
|
||||||
|
output bit_as_bool s_axi_awready,
|
||||||
|
input bit [127 : 0] s_axi_wdata,
|
||||||
|
input bit [15 : 0] s_axi_wstrb,
|
||||||
|
input bit_as_bool s_axi_wlast,
|
||||||
|
input bit_as_bool s_axi_wvalid,
|
||||||
|
output bit_as_bool s_axi_wready,
|
||||||
|
output bit [1 : 0] s_axi_bresp,
|
||||||
|
output bit_as_bool s_axi_bvalid,
|
||||||
|
input bit_as_bool s_axi_bready,
|
||||||
|
input bit_as_bool m_axi_aclk,
|
||||||
|
input bit_as_bool m_axi_aresetn,
|
||||||
|
output bit [31 : 0] m_axi_awaddr,
|
||||||
|
output bit [7 : 0] m_axi_awlen,
|
||||||
|
output bit [2 : 0] m_axi_awsize,
|
||||||
|
output bit [1 : 0] m_axi_awburst,
|
||||||
|
output bit [0 : 0] m_axi_awlock,
|
||||||
|
output bit [3 : 0] m_axi_awcache,
|
||||||
|
output bit [2 : 0] m_axi_awprot,
|
||||||
|
output bit [3 : 0] m_axi_awregion,
|
||||||
|
output bit [3 : 0] m_axi_awqos,
|
||||||
|
output bit_as_bool m_axi_awvalid,
|
||||||
|
input bit_as_bool m_axi_awready,
|
||||||
|
output bit [127 : 0] m_axi_wdata,
|
||||||
|
output bit [15 : 0] m_axi_wstrb,
|
||||||
|
output bit_as_bool m_axi_wlast,
|
||||||
|
output bit_as_bool m_axi_wvalid,
|
||||||
|
input bit_as_bool m_axi_wready,
|
||||||
|
input bit [1 : 0] m_axi_bresp,
|
||||||
|
input bit_as_bool m_axi_bvalid,
|
||||||
|
output bit_as_bool m_axi_bready
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef XCELIUM
|
||||||
|
(* XMSC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_cc_1 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,m_axi_aclk,m_axi_aresetn,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready)
|
||||||
|
(* integer foreign = "SystemC";
|
||||||
|
*);
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [127 : 0] s_axi_wdata;
|
||||||
|
input bit [15 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit m_axi_aclk;
|
||||||
|
input bit m_axi_aresetn;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef RIVIERA
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_cc_1 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,m_axi_aclk,m_axi_aresetn,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready)
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [127 : 0] s_axi_wdata;
|
||||||
|
input bit [15 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit m_axi_aclk;
|
||||||
|
input bit m_axi_aresetn;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,310 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
|
||||||
|
// IP Revision: 21
|
||||||
|
|
||||||
|
(* X_CORE_INFO = "axi_clock_converter_v2_1_21_axi_clock_converter,Vivado 2020.2" *)
|
||||||
|
(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_cc_1,axi_clock_converter_v2_1_21_axi_clock_converter,{}" *)
|
||||||
|
(* CORE_GENERATION_INFO = "pl_eth_10g_auto_cc_1,axi_clock_converter_v2_1_21_axi_clock_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUS\
|
||||||
|
ER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_SYNCHRONIZER_STAGE=3}" *)
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_cc_1 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
m_axi_aclk,
|
||||||
|
m_axi_aresetn,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [127 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [15 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
|
||||||
|
M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET M_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
|
||||||
|
input wire m_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME MI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
|
||||||
|
input wire m_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
|
||||||
|
axi_clock_converter_v2_1_21_axi_clock_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_AXI_DATA_WIDTH(128),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(1),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(0),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(32'H00000000),
|
||||||
|
.s_axi_arlen(8'H00),
|
||||||
|
.s_axi_arsize(3'H0),
|
||||||
|
.s_axi_arburst(2'H1),
|
||||||
|
.s_axi_arlock(1'H0),
|
||||||
|
.s_axi_arcache(4'H0),
|
||||||
|
.s_axi_arprot(3'H0),
|
||||||
|
.s_axi_arregion(4'H0),
|
||||||
|
.s_axi_arqos(4'H0),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(1'H0),
|
||||||
|
.s_axi_arready(),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(),
|
||||||
|
.s_axi_rresp(),
|
||||||
|
.s_axi_rlast(),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(),
|
||||||
|
.s_axi_rready(1'H0),
|
||||||
|
.m_axi_aclk(m_axi_aclk),
|
||||||
|
.m_axi_aresetn(m_axi_aresetn),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(),
|
||||||
|
.m_axi_arlen(),
|
||||||
|
.m_axi_arsize(),
|
||||||
|
.m_axi_arburst(),
|
||||||
|
.m_axi_arlock(),
|
||||||
|
.m_axi_arcache(),
|
||||||
|
.m_axi_arprot(),
|
||||||
|
.m_axi_arregion(),
|
||||||
|
.m_axi_arqos(),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(),
|
||||||
|
.m_axi_arready(1'H0),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(128'H00000000000000000000000000000000),
|
||||||
|
.m_axi_rresp(2'H0),
|
||||||
|
.m_axi_rlast(1'H1),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(1'H0),
|
||||||
|
.m_axi_rready()
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
#include "axi_clock_converter.h"
|
||||||
|
#include <sstream>
|
||||||
|
|
||||||
|
axi_clock_converter::axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
|
||||||
|
sc_module(module_name) {
|
||||||
|
M_INITIATOR_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
|
||||||
|
M_INITIATOR_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
|
||||||
|
S_TARGET_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
|
||||||
|
S_TARGET_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
|
||||||
|
P1 = new xtlm::xtlm_aximm_passthru_module("P1");
|
||||||
|
P2 = new xtlm::xtlm_aximm_passthru_module("P2");
|
||||||
|
P1->initiator_socket->bind(*M_INITIATOR_rd_socket);
|
||||||
|
P2->initiator_socket->bind(*M_INITIATOR_wr_socket);
|
||||||
|
S_TARGET_rd_socket->bind(*(P1->target_socket));
|
||||||
|
S_TARGET_wr_socket->bind(*(P2->target_socket));
|
||||||
|
}
|
||||||
|
axi_clock_converter::~axi_clock_converter() {
|
||||||
|
delete M_INITIATOR_wr_socket;
|
||||||
|
delete M_INITIATOR_rd_socket;
|
||||||
|
delete S_TARGET_wr_socket;
|
||||||
|
delete S_TARGET_rd_socket;
|
||||||
|
delete P1;
|
||||||
|
delete P2;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
#ifndef _axi_clock_converter_
|
||||||
|
#define _axi_clock_converter_
|
||||||
|
#include <xtlm.h>
|
||||||
|
#include <utils/xtlm_aximm_passthru_module.h>
|
||||||
|
#include <systemc>
|
||||||
|
|
||||||
|
class axi_clock_converter:public sc_module{
|
||||||
|
public:
|
||||||
|
axi_clock_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||||
|
virtual ~axi_clock_converter();
|
||||||
|
SC_HAS_PROCESS(axi_clock_converter);
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* M_INITIATOR_wr_socket;
|
||||||
|
sc_in<bool> s_axi_aclk;
|
||||||
|
sc_in<bool> s_axi_aresetn;
|
||||||
|
sc_in<bool> m_axi_aclk;
|
||||||
|
sc_in<bool> m_axi_aresetn;
|
||||||
|
|
||||||
|
private:
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P1;
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P2;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,7 @@
|
||||||
|
###############################################################################################################
|
||||||
|
# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_ds_0"
|
||||||
|
###############################################################################################################
|
||||||
|
#
|
||||||
|
# This component is not configured to perform asynchronous clock-domain-crossing.
|
||||||
|
# No timing core-level constraints are needed.
|
||||||
|
# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,668 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_DS_0_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_DS_0_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_ds_0_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_ds_0 : public pl_eth_10g_auto_ds_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,40,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_DS_0_H_
|
||||||
|
|
@ -0,0 +1,391 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_ds_0 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awid,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bid,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_arid,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rid,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||||
|
input wire [15 : 0] s_axi_awid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [127 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [15 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||||
|
input wire [15 : 0] s_axi_arid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_dwidth_converter_v2_1_22_top #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_S_AXI_ID_WIDTH(16),
|
||||||
|
.C_SUPPORTS_ID(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(40),
|
||||||
|
.C_S_AXI_DATA_WIDTH(128),
|
||||||
|
.C_M_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_FIFO_MODE(0),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(0),
|
||||||
|
.C_MAX_SPLIT_BEATS(256),
|
||||||
|
.C_PACKING_LEVEL(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(s_axi_awid),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(s_axi_bid),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(s_axi_arid),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(s_axi_rid),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(1'H0),
|
||||||
|
.m_axi_aresetn(1'H0),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_ds_0_sc.h"
|
||||||
|
|
||||||
|
#include "axi_dwidth_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0_sc::pl_eth_10g_auto_ds_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_ds_0", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ID_WIDTH", "16");
|
||||||
|
model_param_props.addLong("C_SUPPORTS_ID", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "40");
|
||||||
|
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "128");
|
||||||
|
model_param_props.addLong("C_M_AXI_DATA_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||||
|
model_param_props.addLong("C_FIFO_MODE", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
|
||||||
|
model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
|
||||||
|
model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
|
||||||
|
model_param_props.addLong("C_MAX_SPLIT_BEATS", "256");
|
||||||
|
model_param_props.addLong("C_PACKING_LEVEL", "1");
|
||||||
|
model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_dwidth_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
target_rd_socket = mp_impl->target_rd_socket;
|
||||||
|
target_wr_socket = mp_impl->target_wr_socket;
|
||||||
|
initiator_rd_socket = mp_impl->initiator_rd_socket;
|
||||||
|
initiator_wr_socket = mp_impl->initiator_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0_sc::~pl_eth_10g_auto_ds_0_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_DS_0_SC_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_DS_0_SC_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
class axi_dwidth_converter;
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_ds_0_sc : public sc_core::sc_module
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0_sc(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_0_sc();
|
||||||
|
|
||||||
|
// module socket-to-socket AXI TLM interfaces
|
||||||
|
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
|
||||||
|
// module socket-to-socket TLM interfaces
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
axi_dwidth_converter* mp_impl;
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_0_sc(const pl_eth_10g_auto_ds_0_sc&);
|
||||||
|
const pl_eth_10g_auto_ds_0_sc& operator=(const pl_eth_10g_auto_ds_0_sc&);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_DS_0_SC_H_
|
||||||
|
|
@ -0,0 +1,314 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
// Filename: pl_eth_10g_auto_ds_0_stub.sv
|
||||||
|
// Description: This HDL file is intended to be used with following simulators only:
|
||||||
|
//
|
||||||
|
// Vivado Simulator (XSim)
|
||||||
|
// Cadence Xcelium Simulator
|
||||||
|
// Aldec Riviera-PRO Simulator
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
`ifdef XILINX_SIMULATOR
|
||||||
|
|
||||||
|
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||||
|
`define XILINX_SIMULATOR_BITASBOOL
|
||||||
|
typedef bit bit_as_bool;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_ds_0 (
|
||||||
|
input bit_as_bool s_axi_aclk,
|
||||||
|
input bit_as_bool s_axi_aresetn,
|
||||||
|
input bit [15 : 0] s_axi_awid,
|
||||||
|
input bit [39 : 0] s_axi_awaddr,
|
||||||
|
input bit [7 : 0] s_axi_awlen,
|
||||||
|
input bit [2 : 0] s_axi_awsize,
|
||||||
|
input bit [1 : 0] s_axi_awburst,
|
||||||
|
input bit [0 : 0] s_axi_awlock,
|
||||||
|
input bit [3 : 0] s_axi_awcache,
|
||||||
|
input bit [2 : 0] s_axi_awprot,
|
||||||
|
input bit [3 : 0] s_axi_awregion,
|
||||||
|
input bit [3 : 0] s_axi_awqos,
|
||||||
|
input bit_as_bool s_axi_awvalid,
|
||||||
|
output bit_as_bool s_axi_awready,
|
||||||
|
input bit [127 : 0] s_axi_wdata,
|
||||||
|
input bit [15 : 0] s_axi_wstrb,
|
||||||
|
input bit_as_bool s_axi_wlast,
|
||||||
|
input bit_as_bool s_axi_wvalid,
|
||||||
|
output bit_as_bool s_axi_wready,
|
||||||
|
output bit [15 : 0] s_axi_bid,
|
||||||
|
output bit [1 : 0] s_axi_bresp,
|
||||||
|
output bit_as_bool s_axi_bvalid,
|
||||||
|
input bit_as_bool s_axi_bready,
|
||||||
|
input bit [15 : 0] s_axi_arid,
|
||||||
|
input bit [39 : 0] s_axi_araddr,
|
||||||
|
input bit [7 : 0] s_axi_arlen,
|
||||||
|
input bit [2 : 0] s_axi_arsize,
|
||||||
|
input bit [1 : 0] s_axi_arburst,
|
||||||
|
input bit [0 : 0] s_axi_arlock,
|
||||||
|
input bit [3 : 0] s_axi_arcache,
|
||||||
|
input bit [2 : 0] s_axi_arprot,
|
||||||
|
input bit [3 : 0] s_axi_arregion,
|
||||||
|
input bit [3 : 0] s_axi_arqos,
|
||||||
|
input bit_as_bool s_axi_arvalid,
|
||||||
|
output bit_as_bool s_axi_arready,
|
||||||
|
output bit [15 : 0] s_axi_rid,
|
||||||
|
output bit [127 : 0] s_axi_rdata,
|
||||||
|
output bit [1 : 0] s_axi_rresp,
|
||||||
|
output bit_as_bool s_axi_rlast,
|
||||||
|
output bit_as_bool s_axi_rvalid,
|
||||||
|
input bit_as_bool s_axi_rready,
|
||||||
|
output bit [39 : 0] m_axi_awaddr,
|
||||||
|
output bit [7 : 0] m_axi_awlen,
|
||||||
|
output bit [2 : 0] m_axi_awsize,
|
||||||
|
output bit [1 : 0] m_axi_awburst,
|
||||||
|
output bit [0 : 0] m_axi_awlock,
|
||||||
|
output bit [3 : 0] m_axi_awcache,
|
||||||
|
output bit [2 : 0] m_axi_awprot,
|
||||||
|
output bit [3 : 0] m_axi_awregion,
|
||||||
|
output bit [3 : 0] m_axi_awqos,
|
||||||
|
output bit_as_bool m_axi_awvalid,
|
||||||
|
input bit_as_bool m_axi_awready,
|
||||||
|
output bit [31 : 0] m_axi_wdata,
|
||||||
|
output bit [3 : 0] m_axi_wstrb,
|
||||||
|
output bit_as_bool m_axi_wlast,
|
||||||
|
output bit_as_bool m_axi_wvalid,
|
||||||
|
input bit_as_bool m_axi_wready,
|
||||||
|
input bit [1 : 0] m_axi_bresp,
|
||||||
|
input bit_as_bool m_axi_bvalid,
|
||||||
|
output bit_as_bool m_axi_bready,
|
||||||
|
output bit [39 : 0] m_axi_araddr,
|
||||||
|
output bit [7 : 0] m_axi_arlen,
|
||||||
|
output bit [2 : 0] m_axi_arsize,
|
||||||
|
output bit [1 : 0] m_axi_arburst,
|
||||||
|
output bit [0 : 0] m_axi_arlock,
|
||||||
|
output bit [3 : 0] m_axi_arcache,
|
||||||
|
output bit [2 : 0] m_axi_arprot,
|
||||||
|
output bit [3 : 0] m_axi_arregion,
|
||||||
|
output bit [3 : 0] m_axi_arqos,
|
||||||
|
output bit_as_bool m_axi_arvalid,
|
||||||
|
input bit_as_bool m_axi_arready,
|
||||||
|
input bit [31 : 0] m_axi_rdata,
|
||||||
|
input bit [1 : 0] m_axi_rresp,
|
||||||
|
input bit_as_bool m_axi_rlast,
|
||||||
|
input bit_as_bool m_axi_rvalid,
|
||||||
|
output bit_as_bool m_axi_rready
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef XCELIUM
|
||||||
|
(* XMSC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_ds_0 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
(* integer foreign = "SystemC";
|
||||||
|
*);
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [15 : 0] s_axi_awid;
|
||||||
|
input bit [39 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [127 : 0] s_axi_wdata;
|
||||||
|
input bit [15 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [15 : 0] s_axi_arid;
|
||||||
|
input bit [39 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef RIVIERA
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_ds_0 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [15 : 0] s_axi_awid;
|
||||||
|
input bit [39 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [127 : 0] s_axi_wdata;
|
||||||
|
input bit [15 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [15 : 0] s_axi_arid;
|
||||||
|
input bit [39 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,527 @@
|
||||||
|
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
||||||
|
// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#include "axi_dwidth_converter.h"
|
||||||
|
#define PAYLOAD_LOG_LEVEL 3
|
||||||
|
|
||||||
|
axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
|
||||||
|
xsc::common_cpp::properties& m_properties) :
|
||||||
|
sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
|
||||||
|
nullptr),m_logger((std::string) (p_name)) {
|
||||||
|
|
||||||
|
initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
|
||||||
|
"rd_trace_socket", 32);
|
||||||
|
initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
|
||||||
|
"wr_trace_socket", 32);
|
||||||
|
target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
|
||||||
|
32);
|
||||||
|
target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
|
||||||
|
32);
|
||||||
|
rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
|
||||||
|
xtlm::aximm::TRANSACTION, 32);
|
||||||
|
wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
|
||||||
|
xtlm::aximm::TRANSACTION, 32);
|
||||||
|
rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
|
||||||
|
"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
|
||||||
|
wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
|
||||||
|
"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
|
||||||
|
target_rd_socket->bind(rd_target_util->rd_socket);
|
||||||
|
target_wr_socket->bind(wr_target_util->wr_socket);
|
||||||
|
rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
|
||||||
|
wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
|
||||||
|
|
||||||
|
mem_manager = new xtlm::xtlm_aximm_mem_manager();
|
||||||
|
SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
|
||||||
|
MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
|
||||||
|
FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
|
||||||
|
|
||||||
|
|
||||||
|
ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
|
||||||
|
if(FIFO_MODE!=2)
|
||||||
|
{
|
||||||
|
m_axi_aclk(clk);
|
||||||
|
m_axi_aresetn(resetn);
|
||||||
|
}
|
||||||
|
|
||||||
|
SC_METHOD(wr_handler);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_target_util->transaction_available;
|
||||||
|
sensitive << event_trig_wr_handler;
|
||||||
|
|
||||||
|
SC_METHOD(rd_handler);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << rd_target_util->addr_available;
|
||||||
|
sensitive << event_trig_rd_handler;
|
||||||
|
|
||||||
|
SC_METHOD(m_downsize_interface_txn_sender);
|
||||||
|
sensitive << event_downsize_trig_txn_sender;
|
||||||
|
sensitive << wr_initiator_util->transaction_sampled;
|
||||||
|
sensitive << rd_initiator_util->transaction_sampled;
|
||||||
|
dont_initialize();
|
||||||
|
|
||||||
|
SC_METHOD(m_upsize_interface_txn_sender);
|
||||||
|
sensitive << event_upsize_trig_txn_sender;
|
||||||
|
dont_initialize();
|
||||||
|
|
||||||
|
SC_METHOD(m_downsize_interface_response_sender);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_initiator_util->resp_available;
|
||||||
|
sensitive << rd_initiator_util->data_available;
|
||||||
|
sensitive << rd_target_util->data_sampled;
|
||||||
|
sensitive << wr_target_util->resp_sampled;
|
||||||
|
|
||||||
|
SC_METHOD(m_upsize_interface_response_sender);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_initiator_util->resp_available;
|
||||||
|
sensitive << rd_initiator_util->data_available;
|
||||||
|
sensitive << rd_target_util->data_sampled;
|
||||||
|
sensitive << wr_target_util->resp_sampled;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::wr_handler() {
|
||||||
|
if(wr_initiator_util->is_slave_ready() &&
|
||||||
|
wr_target_util->is_trans_available() )
|
||||||
|
{
|
||||||
|
m_wr_trans = wr_target_util->get_transaction();
|
||||||
|
m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG);
|
||||||
|
ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
|
||||||
|
if (ratio <= 1)
|
||||||
|
wr_upsizing();
|
||||||
|
else
|
||||||
|
wr_downsizing();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::rd_handler() {
|
||||||
|
if(rd_initiator_util->is_slave_ready() &&
|
||||||
|
rd_target_util->is_trans_available() )
|
||||||
|
{
|
||||||
|
m_rd_trans = rd_target_util->get_transaction();
|
||||||
|
|
||||||
|
m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
ratio = m_rd_trans->get_burst_size() / MI_DATA_WIDTH;
|
||||||
|
if (ratio <= 1)
|
||||||
|
rd_upsizing();
|
||||||
|
else
|
||||||
|
rd_downsizing();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::rd_downsizing() {
|
||||||
|
auto beat_l = m_rd_trans->get_burst_length();
|
||||||
|
auto data = m_rd_trans->get_data_ptr();
|
||||||
|
auto new_beat_l = beat_l * (ratio);
|
||||||
|
auto strb = m_rd_trans->get_byte_enable_ptr();
|
||||||
|
auto s_addr = m_rd_trans->get_address();
|
||||||
|
auto num_byte_counter = 0;
|
||||||
|
auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
|
||||||
|
auto cur_beat_l = 0;
|
||||||
|
auto t_total_txns = 0;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down Sizing input transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_response_list = new std::list<xtlm::aximm_payload*>;
|
||||||
|
do {
|
||||||
|
if (new_beat_l > 256)
|
||||||
|
cur_beat_l = 256;
|
||||||
|
else
|
||||||
|
cur_beat_l = new_beat_l;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_rd_trans);
|
||||||
|
t_trans->set_address(s_addr + num_byte_counter);
|
||||||
|
t_trans->set_data_ptr(data + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH);
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_length(cur_beat_l);
|
||||||
|
num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
|
||||||
|
m_interface_rd_payload_queue.push(t_trans);
|
||||||
|
m_response_list->push_back(t_trans);
|
||||||
|
t_total_txns++;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down sized output transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
} while (num_byte_counter < total_num_bytes);
|
||||||
|
m_response_mapper_downsize[m_rd_trans] = m_response_list;
|
||||||
|
event_downsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::wr_downsizing() {
|
||||||
|
auto beat_l = m_wr_trans->get_burst_length();
|
||||||
|
auto data = m_wr_trans->get_data_ptr();
|
||||||
|
auto strb = m_wr_trans->get_byte_enable_ptr();
|
||||||
|
auto new_beat_l = beat_l * (ratio);
|
||||||
|
auto s_addr = m_wr_trans->get_address();
|
||||||
|
auto num_byte_counter = 0;
|
||||||
|
auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
|
||||||
|
auto cur_beat_l = 0;
|
||||||
|
auto t_total_txns = 0;
|
||||||
|
m_response_list = new std::list<xtlm::aximm_payload*>;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down Sizing input transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
do {
|
||||||
|
if (new_beat_l > 256)
|
||||||
|
cur_beat_l = 256;
|
||||||
|
else
|
||||||
|
cur_beat_l = new_beat_l;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_wr_trans);
|
||||||
|
t_trans->set_address(s_addr + num_byte_counter);
|
||||||
|
t_trans->set_data_ptr(data + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_length(cur_beat_l);
|
||||||
|
num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
|
||||||
|
m_interface_wr_payload_queue.push(t_trans);
|
||||||
|
m_response_list->push_back(t_trans);
|
||||||
|
t_total_txns++;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down sized output transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
} while (num_byte_counter < total_num_bytes);
|
||||||
|
|
||||||
|
m_response_mapper_downsize[m_wr_trans] = m_response_list;
|
||||||
|
event_downsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::m_downsize_interface_txn_sender() {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
if (wr_initiator_util->is_slave_ready()
|
||||||
|
&& (m_interface_wr_payload_queue.size() != 0)) {
|
||||||
|
m_log_msg = "Sending Write transaction " +
|
||||||
|
std::to_string(m_interface_wr_payload_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_initiator_util->send_transaction(
|
||||||
|
*m_interface_wr_payload_queue.front(), zero_delay);
|
||||||
|
m_interface_wr_payload_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
//For Read transaction
|
||||||
|
zero_delay = SC_ZERO_TIME;
|
||||||
|
if (rd_initiator_util->is_slave_ready()
|
||||||
|
&& (m_interface_rd_payload_queue.size() != 0)) {
|
||||||
|
m_log_msg = "Sending Read transaction " +
|
||||||
|
std::to_string(m_interface_rd_payload_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_initiator_util->send_transaction(
|
||||||
|
*m_interface_rd_payload_queue.front(), zero_delay);
|
||||||
|
m_interface_rd_payload_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::m_downsize_interface_response_sender() {
|
||||||
|
if (ratio <= 1)
|
||||||
|
return;
|
||||||
|
if (wr_initiator_util->is_resp_available()
|
||||||
|
&& (m_response_mapper_downsize.size() != 0)
|
||||||
|
&& (wr_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
|
||||||
|
m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::list<xtlm::aximm_payload*>::iterator itrlist;
|
||||||
|
std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
|
||||||
|
for (itr = m_response_mapper_downsize.begin();
|
||||||
|
itr != m_response_mapper_downsize.end(); itr++) {
|
||||||
|
itrlist = (std::find(itr->second->begin(), itr->second->end(),
|
||||||
|
response_payld));
|
||||||
|
if (itrlist != itr->second->end()) {
|
||||||
|
itr->second->remove(response_payld);
|
||||||
|
if (itr->second->size() == 0) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
itr->first->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Write : " +
|
||||||
|
std::to_string(itr->first->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_target_util->send_resp(*(itr->first), zero_delay);
|
||||||
|
delete (itr->second);
|
||||||
|
m_response_mapper_downsize.erase(itr);
|
||||||
|
event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
response_payld->release();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rd_initiator_util->is_data_available()
|
||||||
|
&& (m_response_mapper_downsize.size() != 0)
|
||||||
|
&& (rd_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
|
||||||
|
m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::list<xtlm::aximm_payload*>::iterator itrlist;
|
||||||
|
std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
|
||||||
|
for (itr = m_response_mapper_downsize.begin();
|
||||||
|
itr != m_response_mapper_downsize.end(); itr++) {
|
||||||
|
itrlist = (std::find(itr->second->begin(), itr->second->end(),
|
||||||
|
response_payld));
|
||||||
|
if (itrlist != itr->second->end()) {
|
||||||
|
itr->second->remove(response_payld);
|
||||||
|
if (itr->second->size() == 0) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
itr->first->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Read : " +
|
||||||
|
std::to_string(itr->first->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_target_util->send_data(*(itr->first), zero_delay);
|
||||||
|
delete (itr->second);
|
||||||
|
event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
m_response_mapper_downsize.erase(itr);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
//Release the transaction to memory manager
|
||||||
|
response_payld->release();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::wr_upsizing() {
|
||||||
|
auto si_addr = m_wr_trans->get_address();
|
||||||
|
auto si_burst_len = m_wr_trans->get_burst_length();
|
||||||
|
auto si_burst_size = m_wr_trans->get_burst_size();
|
||||||
|
auto strb = m_wr_trans->get_byte_enable_ptr();
|
||||||
|
auto data = m_wr_trans->get_data_ptr();
|
||||||
|
auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
|
||||||
|
auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
|
||||||
|
+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
|
||||||
|
* MI_DATA_WIDTH;
|
||||||
|
auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_wr_trans);
|
||||||
|
t_trans->set_address(si_addr);
|
||||||
|
t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_length(mi_len);
|
||||||
|
m_upsize_wr_payld_queue.push(t_trans);
|
||||||
|
m_response_mapper_upsize[t_trans] = m_wr_trans;
|
||||||
|
|
||||||
|
m_log_msg = "Upsizing input Txn ";
|
||||||
|
std::string payload_log;
|
||||||
|
m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_log_msg = "Upsized output Txn ";
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
event_upsize_trig_txn_sender.notify();
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::rd_upsizing() {
|
||||||
|
auto si_addr = m_rd_trans->get_address();
|
||||||
|
auto si_burst_len = m_rd_trans->get_burst_length();
|
||||||
|
auto si_burst_size = m_rd_trans->get_burst_size();
|
||||||
|
auto strb = m_rd_trans->get_byte_enable_ptr();
|
||||||
|
auto data = m_rd_trans->get_data_ptr();
|
||||||
|
auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
|
||||||
|
auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
|
||||||
|
+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
|
||||||
|
* MI_DATA_WIDTH;
|
||||||
|
auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_rd_trans);
|
||||||
|
t_trans->set_address(si_addr);
|
||||||
|
t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_length(mi_len);
|
||||||
|
m_upsize_rd_payld_queue.push(t_trans);
|
||||||
|
m_response_mapper_upsize[t_trans] = m_rd_trans;
|
||||||
|
|
||||||
|
m_log_msg = "Upsizing input Txn ";
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_log_msg = "Upsized output Txn ";
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
event_upsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::m_upsize_interface_txn_sender() {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
if (wr_initiator_util->is_slave_ready()
|
||||||
|
&& (m_upsize_wr_payld_queue.size() != 0)) {
|
||||||
|
|
||||||
|
m_log_msg = "Sending Write transaction " +
|
||||||
|
std::to_string(m_upsize_wr_payld_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
|
||||||
|
zero_delay);
|
||||||
|
m_upsize_wr_payld_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
//For Read transaction
|
||||||
|
zero_delay = SC_ZERO_TIME;
|
||||||
|
if (rd_initiator_util->is_slave_ready()
|
||||||
|
&& (m_upsize_rd_payld_queue.size() != 0)) {
|
||||||
|
|
||||||
|
m_log_msg = "Sending Read transaction " +
|
||||||
|
std::to_string(m_upsize_rd_payld_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
|
||||||
|
zero_delay);
|
||||||
|
m_upsize_rd_payld_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::m_upsize_interface_response_sender() {
|
||||||
|
if (ratio > 1)
|
||||||
|
return;
|
||||||
|
if (wr_initiator_util->is_resp_available()
|
||||||
|
&& (m_response_mapper_upsize.size() != 0)
|
||||||
|
&& (wr_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
|
||||||
|
m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
|
||||||
|
itr = (m_response_mapper_upsize.find(response_payld));
|
||||||
|
if (itr != m_response_mapper_upsize.end()) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
m_response_mapper_upsize[response_payld]->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Write : " +
|
||||||
|
std::to_string(m_response_mapper_upsize[response_payld]->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
|
||||||
|
zero_delay);
|
||||||
|
response_payld->release();
|
||||||
|
m_response_mapper_upsize.erase(response_payld);
|
||||||
|
event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rd_initiator_util->is_data_available()
|
||||||
|
&& (m_response_mapper_upsize.size() != 0)
|
||||||
|
&& (rd_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
|
||||||
|
m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
|
||||||
|
itr = m_response_mapper_upsize.find(response_payld);
|
||||||
|
if (itr != m_response_mapper_upsize.end()) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
m_response_mapper_upsize[response_payld]->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Read : " +
|
||||||
|
std::to_string(m_response_mapper_upsize[response_payld]->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
|
||||||
|
zero_delay);
|
||||||
|
|
||||||
|
response_payld->release();
|
||||||
|
m_response_mapper_upsize.erase(response_payld);
|
||||||
|
event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
axi_dwidth_converter::~axi_dwidth_converter() {
|
||||||
|
delete mem_manager;
|
||||||
|
delete target_rd_socket;
|
||||||
|
delete target_wr_socket;
|
||||||
|
delete initiator_rd_socket;
|
||||||
|
delete initiator_wr_socket;
|
||||||
|
delete rd_target_util;
|
||||||
|
delete wr_target_util;
|
||||||
|
delete wr_initiator_util;
|
||||||
|
delete rd_initiator_util;
|
||||||
|
delete m_rd_trans;
|
||||||
|
delete m_wr_trans;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
||||||
|
// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#ifndef _AXI_DWIDTH_CONVERTER_H_
|
||||||
|
#define _AXI_DWIDTH_CONVERTER_H_
|
||||||
|
|
||||||
|
#include "xtlm.h"
|
||||||
|
#include "report_handler.h"
|
||||||
|
|
||||||
|
class axi_dwidth_converter: public sc_core::sc_module {
|
||||||
|
public:
|
||||||
|
SC_HAS_PROCESS(axi_dwidth_converter);
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
sc_core::sc_in<bool> s_axi_aclk;
|
||||||
|
sc_core::sc_in<bool> s_axi_aresetn;
|
||||||
|
sc_core::sc_in<bool> m_axi_aclk;
|
||||||
|
sc_core::sc_in<bool> m_axi_aresetn;
|
||||||
|
sc_core::sc_signal<bool> clk;
|
||||||
|
sc_core::sc_signal<bool> resetn;
|
||||||
|
axi_dwidth_converter(sc_core::sc_module_name p_name,
|
||||||
|
xsc::common_cpp::properties& m_properties);
|
||||||
|
xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
|
||||||
|
xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
|
||||||
|
xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
|
||||||
|
xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
|
||||||
|
xtlm::xtlm_aximm_mem_manager* mem_manager;
|
||||||
|
~axi_dwidth_converter();
|
||||||
|
unsigned int SI_DATA_WIDTH;
|
||||||
|
unsigned int MI_DATA_WIDTH;
|
||||||
|
unsigned int FIFO_MODE;
|
||||||
|
unsigned int ratio;
|
||||||
|
|
||||||
|
void wr_handler();
|
||||||
|
void rd_handler();
|
||||||
|
void wr_upsizing();
|
||||||
|
void wr_downsizing();
|
||||||
|
void rd_upsizing();
|
||||||
|
void rd_downsizing();
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Method to send transaction on master interface
|
||||||
|
*/
|
||||||
|
void m_downsize_interface_txn_sender();
|
||||||
|
void m_upsize_interface_txn_sender();
|
||||||
|
|
||||||
|
void m_downsize_interface_response_sender();
|
||||||
|
void m_upsize_interface_response_sender();
|
||||||
|
|
||||||
|
private:
|
||||||
|
xtlm::aximm_payload* m_rd_trans;
|
||||||
|
xtlm::aximm_payload* m_wr_trans;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
|
||||||
|
sc_core::sc_event event_downsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||||
|
sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||||
|
sc_core::sc_event event_trig_rd_handler;
|
||||||
|
sc_core::sc_event event_trig_wr_handler;
|
||||||
|
std::list<xtlm::aximm_payload* > *m_response_list;
|
||||||
|
std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
|
||||||
|
std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
|
||||||
|
xsc::common_cpp::report_handler m_logger;
|
||||||
|
std::string m_log_msg;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _AXI_DWIDTH_CONVERTER_H_ */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,393 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
|
||||||
|
(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_ds_0,axi_dwidth_converter_v2_1_22_top,{}" *)
|
||||||
|
(* CORE_GENERATION_INFO = "pl_eth_10g_auto_ds_0,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=16,C_SUPPORTS_ID=1,C_AXI_ADDR_WIDTH=40,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_B\
|
||||||
|
EATS=256,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_ds_0 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awid,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bid,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_arid,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rid,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||||
|
input wire [15 : 0] s_axi_awid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [127 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [15 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||||
|
input wire [15 : 0] s_axi_arid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_dwidth_converter_v2_1_22_top #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_S_AXI_ID_WIDTH(16),
|
||||||
|
.C_SUPPORTS_ID(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(40),
|
||||||
|
.C_S_AXI_DATA_WIDTH(128),
|
||||||
|
.C_M_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_FIFO_MODE(0),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(0),
|
||||||
|
.C_MAX_SPLIT_BEATS(256),
|
||||||
|
.C_PACKING_LEVEL(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(s_axi_awid),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(s_axi_bid),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(s_axi_arid),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(s_axi_rid),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(1'H0),
|
||||||
|
.m_axi_aresetn(1'H0),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,7 @@
|
||||||
|
###############################################################################################################
|
||||||
|
# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_ds_1"
|
||||||
|
###############################################################################################################
|
||||||
|
#
|
||||||
|
# This component is not configured to perform asynchronous clock-domain-crossing.
|
||||||
|
# No timing core-level constraints are needed.
|
||||||
|
# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,668 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_DS_1_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_DS_1_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_ds_1_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_ds_1 : public pl_eth_10g_auto_ds_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_bid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_arid;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > s_axi_rid;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<128,32,16,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_DS_1_H_
|
||||||
|
|
@ -0,0 +1,391 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_ds_1 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awid,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bid,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_arid,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rid,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||||
|
input wire [15 : 0] s_axi_awid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [127 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [15 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||||
|
input wire [15 : 0] s_axi_arid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_dwidth_converter_v2_1_22_top #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_S_AXI_ID_WIDTH(16),
|
||||||
|
.C_SUPPORTS_ID(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_S_AXI_DATA_WIDTH(128),
|
||||||
|
.C_M_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_FIFO_MODE(0),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(0),
|
||||||
|
.C_MAX_SPLIT_BEATS(256),
|
||||||
|
.C_PACKING_LEVEL(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(s_axi_awid),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(s_axi_bid),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(s_axi_arid),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(s_axi_rid),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(1'H0),
|
||||||
|
.m_axi_aresetn(1'H0),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_ds_1_sc.h"
|
||||||
|
|
||||||
|
#include "axi_dwidth_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1_sc::pl_eth_10g_auto_ds_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_ds_1", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ID_WIDTH", "16");
|
||||||
|
model_param_props.addLong("C_SUPPORTS_ID", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "128");
|
||||||
|
model_param_props.addLong("C_M_AXI_DATA_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||||
|
model_param_props.addLong("C_FIFO_MODE", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
|
||||||
|
model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
|
||||||
|
model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
|
||||||
|
model_param_props.addLong("C_MAX_SPLIT_BEATS", "256");
|
||||||
|
model_param_props.addLong("C_PACKING_LEVEL", "1");
|
||||||
|
model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_dwidth_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
target_rd_socket = mp_impl->target_rd_socket;
|
||||||
|
target_wr_socket = mp_impl->target_wr_socket;
|
||||||
|
initiator_rd_socket = mp_impl->initiator_rd_socket;
|
||||||
|
initiator_wr_socket = mp_impl->initiator_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1_sc::~pl_eth_10g_auto_ds_1_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_DS_1_SC_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_DS_1_SC_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
class axi_dwidth_converter;
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_ds_1_sc : public sc_core::sc_module
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1_sc(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_ds_1_sc();
|
||||||
|
|
||||||
|
// module socket-to-socket AXI TLM interfaces
|
||||||
|
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
|
||||||
|
// module socket-to-socket TLM interfaces
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
axi_dwidth_converter* mp_impl;
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_ds_1_sc(const pl_eth_10g_auto_ds_1_sc&);
|
||||||
|
const pl_eth_10g_auto_ds_1_sc& operator=(const pl_eth_10g_auto_ds_1_sc&);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_DS_1_SC_H_
|
||||||
|
|
@ -0,0 +1,314 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
// Filename: pl_eth_10g_auto_ds_1_stub.sv
|
||||||
|
// Description: This HDL file is intended to be used with following simulators only:
|
||||||
|
//
|
||||||
|
// Vivado Simulator (XSim)
|
||||||
|
// Cadence Xcelium Simulator
|
||||||
|
// Aldec Riviera-PRO Simulator
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
`ifdef XILINX_SIMULATOR
|
||||||
|
|
||||||
|
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||||
|
`define XILINX_SIMULATOR_BITASBOOL
|
||||||
|
typedef bit bit_as_bool;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_ds_1 (
|
||||||
|
input bit_as_bool s_axi_aclk,
|
||||||
|
input bit_as_bool s_axi_aresetn,
|
||||||
|
input bit [15 : 0] s_axi_awid,
|
||||||
|
input bit [31 : 0] s_axi_awaddr,
|
||||||
|
input bit [7 : 0] s_axi_awlen,
|
||||||
|
input bit [2 : 0] s_axi_awsize,
|
||||||
|
input bit [1 : 0] s_axi_awburst,
|
||||||
|
input bit [0 : 0] s_axi_awlock,
|
||||||
|
input bit [3 : 0] s_axi_awcache,
|
||||||
|
input bit [2 : 0] s_axi_awprot,
|
||||||
|
input bit [3 : 0] s_axi_awregion,
|
||||||
|
input bit [3 : 0] s_axi_awqos,
|
||||||
|
input bit_as_bool s_axi_awvalid,
|
||||||
|
output bit_as_bool s_axi_awready,
|
||||||
|
input bit [127 : 0] s_axi_wdata,
|
||||||
|
input bit [15 : 0] s_axi_wstrb,
|
||||||
|
input bit_as_bool s_axi_wlast,
|
||||||
|
input bit_as_bool s_axi_wvalid,
|
||||||
|
output bit_as_bool s_axi_wready,
|
||||||
|
output bit [15 : 0] s_axi_bid,
|
||||||
|
output bit [1 : 0] s_axi_bresp,
|
||||||
|
output bit_as_bool s_axi_bvalid,
|
||||||
|
input bit_as_bool s_axi_bready,
|
||||||
|
input bit [15 : 0] s_axi_arid,
|
||||||
|
input bit [31 : 0] s_axi_araddr,
|
||||||
|
input bit [7 : 0] s_axi_arlen,
|
||||||
|
input bit [2 : 0] s_axi_arsize,
|
||||||
|
input bit [1 : 0] s_axi_arburst,
|
||||||
|
input bit [0 : 0] s_axi_arlock,
|
||||||
|
input bit [3 : 0] s_axi_arcache,
|
||||||
|
input bit [2 : 0] s_axi_arprot,
|
||||||
|
input bit [3 : 0] s_axi_arregion,
|
||||||
|
input bit [3 : 0] s_axi_arqos,
|
||||||
|
input bit_as_bool s_axi_arvalid,
|
||||||
|
output bit_as_bool s_axi_arready,
|
||||||
|
output bit [15 : 0] s_axi_rid,
|
||||||
|
output bit [127 : 0] s_axi_rdata,
|
||||||
|
output bit [1 : 0] s_axi_rresp,
|
||||||
|
output bit_as_bool s_axi_rlast,
|
||||||
|
output bit_as_bool s_axi_rvalid,
|
||||||
|
input bit_as_bool s_axi_rready,
|
||||||
|
output bit [31 : 0] m_axi_awaddr,
|
||||||
|
output bit [7 : 0] m_axi_awlen,
|
||||||
|
output bit [2 : 0] m_axi_awsize,
|
||||||
|
output bit [1 : 0] m_axi_awburst,
|
||||||
|
output bit [0 : 0] m_axi_awlock,
|
||||||
|
output bit [3 : 0] m_axi_awcache,
|
||||||
|
output bit [2 : 0] m_axi_awprot,
|
||||||
|
output bit [3 : 0] m_axi_awregion,
|
||||||
|
output bit [3 : 0] m_axi_awqos,
|
||||||
|
output bit_as_bool m_axi_awvalid,
|
||||||
|
input bit_as_bool m_axi_awready,
|
||||||
|
output bit [31 : 0] m_axi_wdata,
|
||||||
|
output bit [3 : 0] m_axi_wstrb,
|
||||||
|
output bit_as_bool m_axi_wlast,
|
||||||
|
output bit_as_bool m_axi_wvalid,
|
||||||
|
input bit_as_bool m_axi_wready,
|
||||||
|
input bit [1 : 0] m_axi_bresp,
|
||||||
|
input bit_as_bool m_axi_bvalid,
|
||||||
|
output bit_as_bool m_axi_bready,
|
||||||
|
output bit [31 : 0] m_axi_araddr,
|
||||||
|
output bit [7 : 0] m_axi_arlen,
|
||||||
|
output bit [2 : 0] m_axi_arsize,
|
||||||
|
output bit [1 : 0] m_axi_arburst,
|
||||||
|
output bit [0 : 0] m_axi_arlock,
|
||||||
|
output bit [3 : 0] m_axi_arcache,
|
||||||
|
output bit [2 : 0] m_axi_arprot,
|
||||||
|
output bit [3 : 0] m_axi_arregion,
|
||||||
|
output bit [3 : 0] m_axi_arqos,
|
||||||
|
output bit_as_bool m_axi_arvalid,
|
||||||
|
input bit_as_bool m_axi_arready,
|
||||||
|
input bit [31 : 0] m_axi_rdata,
|
||||||
|
input bit [1 : 0] m_axi_rresp,
|
||||||
|
input bit_as_bool m_axi_rlast,
|
||||||
|
input bit_as_bool m_axi_rvalid,
|
||||||
|
output bit_as_bool m_axi_rready
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef XCELIUM
|
||||||
|
(* XMSC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_ds_1 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
(* integer foreign = "SystemC";
|
||||||
|
*);
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [15 : 0] s_axi_awid;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [127 : 0] s_axi_wdata;
|
||||||
|
input bit [15 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [15 : 0] s_axi_arid;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef RIVIERA
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_ds_1 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [15 : 0] s_axi_awid;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [127 : 0] s_axi_wdata;
|
||||||
|
input bit [15 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [15 : 0] s_axi_arid;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,527 @@
|
||||||
|
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
||||||
|
// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#include "axi_dwidth_converter.h"
|
||||||
|
#define PAYLOAD_LOG_LEVEL 3
|
||||||
|
|
||||||
|
axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
|
||||||
|
xsc::common_cpp::properties& m_properties) :
|
||||||
|
sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
|
||||||
|
nullptr),m_logger((std::string) (p_name)) {
|
||||||
|
|
||||||
|
initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
|
||||||
|
"rd_trace_socket", 32);
|
||||||
|
initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
|
||||||
|
"wr_trace_socket", 32);
|
||||||
|
target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
|
||||||
|
32);
|
||||||
|
target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
|
||||||
|
32);
|
||||||
|
rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
|
||||||
|
xtlm::aximm::TRANSACTION, 32);
|
||||||
|
wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
|
||||||
|
xtlm::aximm::TRANSACTION, 32);
|
||||||
|
rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
|
||||||
|
"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
|
||||||
|
wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
|
||||||
|
"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
|
||||||
|
target_rd_socket->bind(rd_target_util->rd_socket);
|
||||||
|
target_wr_socket->bind(wr_target_util->wr_socket);
|
||||||
|
rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
|
||||||
|
wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
|
||||||
|
|
||||||
|
mem_manager = new xtlm::xtlm_aximm_mem_manager();
|
||||||
|
SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
|
||||||
|
MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
|
||||||
|
FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
|
||||||
|
|
||||||
|
|
||||||
|
ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
|
||||||
|
if(FIFO_MODE!=2)
|
||||||
|
{
|
||||||
|
m_axi_aclk(clk);
|
||||||
|
m_axi_aresetn(resetn);
|
||||||
|
}
|
||||||
|
|
||||||
|
SC_METHOD(wr_handler);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_target_util->transaction_available;
|
||||||
|
sensitive << event_trig_wr_handler;
|
||||||
|
|
||||||
|
SC_METHOD(rd_handler);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << rd_target_util->addr_available;
|
||||||
|
sensitive << event_trig_rd_handler;
|
||||||
|
|
||||||
|
SC_METHOD(m_downsize_interface_txn_sender);
|
||||||
|
sensitive << event_downsize_trig_txn_sender;
|
||||||
|
sensitive << wr_initiator_util->transaction_sampled;
|
||||||
|
sensitive << rd_initiator_util->transaction_sampled;
|
||||||
|
dont_initialize();
|
||||||
|
|
||||||
|
SC_METHOD(m_upsize_interface_txn_sender);
|
||||||
|
sensitive << event_upsize_trig_txn_sender;
|
||||||
|
dont_initialize();
|
||||||
|
|
||||||
|
SC_METHOD(m_downsize_interface_response_sender);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_initiator_util->resp_available;
|
||||||
|
sensitive << rd_initiator_util->data_available;
|
||||||
|
sensitive << rd_target_util->data_sampled;
|
||||||
|
sensitive << wr_target_util->resp_sampled;
|
||||||
|
|
||||||
|
SC_METHOD(m_upsize_interface_response_sender);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_initiator_util->resp_available;
|
||||||
|
sensitive << rd_initiator_util->data_available;
|
||||||
|
sensitive << rd_target_util->data_sampled;
|
||||||
|
sensitive << wr_target_util->resp_sampled;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::wr_handler() {
|
||||||
|
if(wr_initiator_util->is_slave_ready() &&
|
||||||
|
wr_target_util->is_trans_available() )
|
||||||
|
{
|
||||||
|
m_wr_trans = wr_target_util->get_transaction();
|
||||||
|
m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG);
|
||||||
|
ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
|
||||||
|
if (ratio <= 1)
|
||||||
|
wr_upsizing();
|
||||||
|
else
|
||||||
|
wr_downsizing();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::rd_handler() {
|
||||||
|
if(rd_initiator_util->is_slave_ready() &&
|
||||||
|
rd_target_util->is_trans_available() )
|
||||||
|
{
|
||||||
|
m_rd_trans = rd_target_util->get_transaction();
|
||||||
|
|
||||||
|
m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
ratio = m_rd_trans->get_burst_size() / MI_DATA_WIDTH;
|
||||||
|
if (ratio <= 1)
|
||||||
|
rd_upsizing();
|
||||||
|
else
|
||||||
|
rd_downsizing();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::rd_downsizing() {
|
||||||
|
auto beat_l = m_rd_trans->get_burst_length();
|
||||||
|
auto data = m_rd_trans->get_data_ptr();
|
||||||
|
auto new_beat_l = beat_l * (ratio);
|
||||||
|
auto strb = m_rd_trans->get_byte_enable_ptr();
|
||||||
|
auto s_addr = m_rd_trans->get_address();
|
||||||
|
auto num_byte_counter = 0;
|
||||||
|
auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
|
||||||
|
auto cur_beat_l = 0;
|
||||||
|
auto t_total_txns = 0;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down Sizing input transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_response_list = new std::list<xtlm::aximm_payload*>;
|
||||||
|
do {
|
||||||
|
if (new_beat_l > 256)
|
||||||
|
cur_beat_l = 256;
|
||||||
|
else
|
||||||
|
cur_beat_l = new_beat_l;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_rd_trans);
|
||||||
|
t_trans->set_address(s_addr + num_byte_counter);
|
||||||
|
t_trans->set_data_ptr(data + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH);
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_length(cur_beat_l);
|
||||||
|
num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
|
||||||
|
m_interface_rd_payload_queue.push(t_trans);
|
||||||
|
m_response_list->push_back(t_trans);
|
||||||
|
t_total_txns++;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down sized output transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
} while (num_byte_counter < total_num_bytes);
|
||||||
|
m_response_mapper_downsize[m_rd_trans] = m_response_list;
|
||||||
|
event_downsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::wr_downsizing() {
|
||||||
|
auto beat_l = m_wr_trans->get_burst_length();
|
||||||
|
auto data = m_wr_trans->get_data_ptr();
|
||||||
|
auto strb = m_wr_trans->get_byte_enable_ptr();
|
||||||
|
auto new_beat_l = beat_l * (ratio);
|
||||||
|
auto s_addr = m_wr_trans->get_address();
|
||||||
|
auto num_byte_counter = 0;
|
||||||
|
auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
|
||||||
|
auto cur_beat_l = 0;
|
||||||
|
auto t_total_txns = 0;
|
||||||
|
m_response_list = new std::list<xtlm::aximm_payload*>;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down Sizing input transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
do {
|
||||||
|
if (new_beat_l > 256)
|
||||||
|
cur_beat_l = 256;
|
||||||
|
else
|
||||||
|
cur_beat_l = new_beat_l;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_wr_trans);
|
||||||
|
t_trans->set_address(s_addr + num_byte_counter);
|
||||||
|
t_trans->set_data_ptr(data + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_length(cur_beat_l);
|
||||||
|
num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
|
||||||
|
m_interface_wr_payload_queue.push(t_trans);
|
||||||
|
m_response_list->push_back(t_trans);
|
||||||
|
t_total_txns++;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down sized output transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
} while (num_byte_counter < total_num_bytes);
|
||||||
|
|
||||||
|
m_response_mapper_downsize[m_wr_trans] = m_response_list;
|
||||||
|
event_downsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::m_downsize_interface_txn_sender() {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
if (wr_initiator_util->is_slave_ready()
|
||||||
|
&& (m_interface_wr_payload_queue.size() != 0)) {
|
||||||
|
m_log_msg = "Sending Write transaction " +
|
||||||
|
std::to_string(m_interface_wr_payload_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_initiator_util->send_transaction(
|
||||||
|
*m_interface_wr_payload_queue.front(), zero_delay);
|
||||||
|
m_interface_wr_payload_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
//For Read transaction
|
||||||
|
zero_delay = SC_ZERO_TIME;
|
||||||
|
if (rd_initiator_util->is_slave_ready()
|
||||||
|
&& (m_interface_rd_payload_queue.size() != 0)) {
|
||||||
|
m_log_msg = "Sending Read transaction " +
|
||||||
|
std::to_string(m_interface_rd_payload_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_initiator_util->send_transaction(
|
||||||
|
*m_interface_rd_payload_queue.front(), zero_delay);
|
||||||
|
m_interface_rd_payload_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::m_downsize_interface_response_sender() {
|
||||||
|
if (ratio <= 1)
|
||||||
|
return;
|
||||||
|
if (wr_initiator_util->is_resp_available()
|
||||||
|
&& (m_response_mapper_downsize.size() != 0)
|
||||||
|
&& (wr_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
|
||||||
|
m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::list<xtlm::aximm_payload*>::iterator itrlist;
|
||||||
|
std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
|
||||||
|
for (itr = m_response_mapper_downsize.begin();
|
||||||
|
itr != m_response_mapper_downsize.end(); itr++) {
|
||||||
|
itrlist = (std::find(itr->second->begin(), itr->second->end(),
|
||||||
|
response_payld));
|
||||||
|
if (itrlist != itr->second->end()) {
|
||||||
|
itr->second->remove(response_payld);
|
||||||
|
if (itr->second->size() == 0) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
itr->first->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Write : " +
|
||||||
|
std::to_string(itr->first->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_target_util->send_resp(*(itr->first), zero_delay);
|
||||||
|
delete (itr->second);
|
||||||
|
m_response_mapper_downsize.erase(itr);
|
||||||
|
event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
response_payld->release();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rd_initiator_util->is_data_available()
|
||||||
|
&& (m_response_mapper_downsize.size() != 0)
|
||||||
|
&& (rd_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
|
||||||
|
m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::list<xtlm::aximm_payload*>::iterator itrlist;
|
||||||
|
std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
|
||||||
|
for (itr = m_response_mapper_downsize.begin();
|
||||||
|
itr != m_response_mapper_downsize.end(); itr++) {
|
||||||
|
itrlist = (std::find(itr->second->begin(), itr->second->end(),
|
||||||
|
response_payld));
|
||||||
|
if (itrlist != itr->second->end()) {
|
||||||
|
itr->second->remove(response_payld);
|
||||||
|
if (itr->second->size() == 0) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
itr->first->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Read : " +
|
||||||
|
std::to_string(itr->first->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_target_util->send_data(*(itr->first), zero_delay);
|
||||||
|
delete (itr->second);
|
||||||
|
event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
m_response_mapper_downsize.erase(itr);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
//Release the transaction to memory manager
|
||||||
|
response_payld->release();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::wr_upsizing() {
|
||||||
|
auto si_addr = m_wr_trans->get_address();
|
||||||
|
auto si_burst_len = m_wr_trans->get_burst_length();
|
||||||
|
auto si_burst_size = m_wr_trans->get_burst_size();
|
||||||
|
auto strb = m_wr_trans->get_byte_enable_ptr();
|
||||||
|
auto data = m_wr_trans->get_data_ptr();
|
||||||
|
auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
|
||||||
|
auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
|
||||||
|
+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
|
||||||
|
* MI_DATA_WIDTH;
|
||||||
|
auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_wr_trans);
|
||||||
|
t_trans->set_address(si_addr);
|
||||||
|
t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_length(mi_len);
|
||||||
|
m_upsize_wr_payld_queue.push(t_trans);
|
||||||
|
m_response_mapper_upsize[t_trans] = m_wr_trans;
|
||||||
|
|
||||||
|
m_log_msg = "Upsizing input Txn ";
|
||||||
|
std::string payload_log;
|
||||||
|
m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_log_msg = "Upsized output Txn ";
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
event_upsize_trig_txn_sender.notify();
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::rd_upsizing() {
|
||||||
|
auto si_addr = m_rd_trans->get_address();
|
||||||
|
auto si_burst_len = m_rd_trans->get_burst_length();
|
||||||
|
auto si_burst_size = m_rd_trans->get_burst_size();
|
||||||
|
auto strb = m_rd_trans->get_byte_enable_ptr();
|
||||||
|
auto data = m_rd_trans->get_data_ptr();
|
||||||
|
auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
|
||||||
|
auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
|
||||||
|
+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
|
||||||
|
* MI_DATA_WIDTH;
|
||||||
|
auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_rd_trans);
|
||||||
|
t_trans->set_address(si_addr);
|
||||||
|
t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_length(mi_len);
|
||||||
|
m_upsize_rd_payld_queue.push(t_trans);
|
||||||
|
m_response_mapper_upsize[t_trans] = m_rd_trans;
|
||||||
|
|
||||||
|
m_log_msg = "Upsizing input Txn ";
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_log_msg = "Upsized output Txn ";
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
event_upsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::m_upsize_interface_txn_sender() {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
if (wr_initiator_util->is_slave_ready()
|
||||||
|
&& (m_upsize_wr_payld_queue.size() != 0)) {
|
||||||
|
|
||||||
|
m_log_msg = "Sending Write transaction " +
|
||||||
|
std::to_string(m_upsize_wr_payld_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
|
||||||
|
zero_delay);
|
||||||
|
m_upsize_wr_payld_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
//For Read transaction
|
||||||
|
zero_delay = SC_ZERO_TIME;
|
||||||
|
if (rd_initiator_util->is_slave_ready()
|
||||||
|
&& (m_upsize_rd_payld_queue.size() != 0)) {
|
||||||
|
|
||||||
|
m_log_msg = "Sending Read transaction " +
|
||||||
|
std::to_string(m_upsize_rd_payld_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
|
||||||
|
zero_delay);
|
||||||
|
m_upsize_rd_payld_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::m_upsize_interface_response_sender() {
|
||||||
|
if (ratio > 1)
|
||||||
|
return;
|
||||||
|
if (wr_initiator_util->is_resp_available()
|
||||||
|
&& (m_response_mapper_upsize.size() != 0)
|
||||||
|
&& (wr_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
|
||||||
|
m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
|
||||||
|
itr = (m_response_mapper_upsize.find(response_payld));
|
||||||
|
if (itr != m_response_mapper_upsize.end()) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
m_response_mapper_upsize[response_payld]->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Write : " +
|
||||||
|
std::to_string(m_response_mapper_upsize[response_payld]->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
|
||||||
|
zero_delay);
|
||||||
|
response_payld->release();
|
||||||
|
m_response_mapper_upsize.erase(response_payld);
|
||||||
|
event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rd_initiator_util->is_data_available()
|
||||||
|
&& (m_response_mapper_upsize.size() != 0)
|
||||||
|
&& (rd_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
|
||||||
|
m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
|
||||||
|
itr = m_response_mapper_upsize.find(response_payld);
|
||||||
|
if (itr != m_response_mapper_upsize.end()) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
m_response_mapper_upsize[response_payld]->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Read : " +
|
||||||
|
std::to_string(m_response_mapper_upsize[response_payld]->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
|
||||||
|
zero_delay);
|
||||||
|
|
||||||
|
response_payld->release();
|
||||||
|
m_response_mapper_upsize.erase(response_payld);
|
||||||
|
event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
axi_dwidth_converter::~axi_dwidth_converter() {
|
||||||
|
delete mem_manager;
|
||||||
|
delete target_rd_socket;
|
||||||
|
delete target_wr_socket;
|
||||||
|
delete initiator_rd_socket;
|
||||||
|
delete initiator_wr_socket;
|
||||||
|
delete rd_target_util;
|
||||||
|
delete wr_target_util;
|
||||||
|
delete wr_initiator_util;
|
||||||
|
delete rd_initiator_util;
|
||||||
|
delete m_rd_trans;
|
||||||
|
delete m_wr_trans;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
||||||
|
// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#ifndef _AXI_DWIDTH_CONVERTER_H_
|
||||||
|
#define _AXI_DWIDTH_CONVERTER_H_
|
||||||
|
|
||||||
|
#include "xtlm.h"
|
||||||
|
#include "report_handler.h"
|
||||||
|
|
||||||
|
class axi_dwidth_converter: public sc_core::sc_module {
|
||||||
|
public:
|
||||||
|
SC_HAS_PROCESS(axi_dwidth_converter);
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
sc_core::sc_in<bool> s_axi_aclk;
|
||||||
|
sc_core::sc_in<bool> s_axi_aresetn;
|
||||||
|
sc_core::sc_in<bool> m_axi_aclk;
|
||||||
|
sc_core::sc_in<bool> m_axi_aresetn;
|
||||||
|
sc_core::sc_signal<bool> clk;
|
||||||
|
sc_core::sc_signal<bool> resetn;
|
||||||
|
axi_dwidth_converter(sc_core::sc_module_name p_name,
|
||||||
|
xsc::common_cpp::properties& m_properties);
|
||||||
|
xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
|
||||||
|
xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
|
||||||
|
xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
|
||||||
|
xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
|
||||||
|
xtlm::xtlm_aximm_mem_manager* mem_manager;
|
||||||
|
~axi_dwidth_converter();
|
||||||
|
unsigned int SI_DATA_WIDTH;
|
||||||
|
unsigned int MI_DATA_WIDTH;
|
||||||
|
unsigned int FIFO_MODE;
|
||||||
|
unsigned int ratio;
|
||||||
|
|
||||||
|
void wr_handler();
|
||||||
|
void rd_handler();
|
||||||
|
void wr_upsizing();
|
||||||
|
void wr_downsizing();
|
||||||
|
void rd_upsizing();
|
||||||
|
void rd_downsizing();
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Method to send transaction on master interface
|
||||||
|
*/
|
||||||
|
void m_downsize_interface_txn_sender();
|
||||||
|
void m_upsize_interface_txn_sender();
|
||||||
|
|
||||||
|
void m_downsize_interface_response_sender();
|
||||||
|
void m_upsize_interface_response_sender();
|
||||||
|
|
||||||
|
private:
|
||||||
|
xtlm::aximm_payload* m_rd_trans;
|
||||||
|
xtlm::aximm_payload* m_wr_trans;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
|
||||||
|
sc_core::sc_event event_downsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||||
|
sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||||
|
sc_core::sc_event event_trig_rd_handler;
|
||||||
|
sc_core::sc_event event_trig_wr_handler;
|
||||||
|
std::list<xtlm::aximm_payload* > *m_response_list;
|
||||||
|
std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
|
||||||
|
std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
|
||||||
|
xsc::common_cpp::report_handler m_logger;
|
||||||
|
std::string m_log_msg;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _AXI_DWIDTH_CONVERTER_H_ */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,393 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
|
||||||
|
(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_ds_1,axi_dwidth_converter_v2_1_22_top,{}" *)
|
||||||
|
(* CORE_GENERATION_INFO = "pl_eth_10g_auto_ds_1,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=16,C_SUPPORTS_ID=1,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_B\
|
||||||
|
EATS=256,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_ds_1 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awid,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bid,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_arid,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rid,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||||
|
input wire [15 : 0] s_axi_awid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [127 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [15 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||||
|
output wire [15 : 0] s_axi_bid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||||
|
input wire [15 : 0] s_axi_arid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||||
|
output wire [15 : 0] s_axi_rid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [127 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 16, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_dwidth_converter_v2_1_22_top #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_S_AXI_ID_WIDTH(16),
|
||||||
|
.C_SUPPORTS_ID(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_S_AXI_DATA_WIDTH(128),
|
||||||
|
.C_M_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_FIFO_MODE(0),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(0),
|
||||||
|
.C_MAX_SPLIT_BEATS(256),
|
||||||
|
.C_PACKING_LEVEL(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(s_axi_awid),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(s_axi_bid),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(s_axi_arid),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(s_axi_rid),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(1'H0),
|
||||||
|
.m_axi_aresetn(1'H0),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,50 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports aclk]
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,538 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_PC_0_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_PC_0_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_pc_0_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_pc_0 : public pl_eth_10g_auto_pc_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<40> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<40> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,40,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,40,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_PC_0_H_
|
||||||
|
|
@ -0,0 +1,345 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_pc_0 (
|
||||||
|
aclk,
|
||||||
|
aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||||
|
input wire aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||||
|
input wire aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [31 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [3 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_protocol_converter_v2_1_22_axi_protocol_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_M_AXI_PROTOCOL(2),
|
||||||
|
.C_S_AXI_PROTOCOL(0),
|
||||||
|
.C_IGNORE_ID(1),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(40),
|
||||||
|
.C_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_TRANSLATION_MODE(2)
|
||||||
|
) inst (
|
||||||
|
.aclk(aclk),
|
||||||
|
.aresetn(aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(),
|
||||||
|
.m_axi_arsize(),
|
||||||
|
.m_axi_arburst(),
|
||||||
|
.m_axi_arlock(),
|
||||||
|
.m_axi_arcache(),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(),
|
||||||
|
.m_axi_arqos(),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(1'H1),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_pc_0_sc.h"
|
||||||
|
|
||||||
|
#include "axi_protocol_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0_sc::pl_eth_10g_auto_pc_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_pc_0", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_M_AXI_PROTOCOL", "2");
|
||||||
|
model_param_props.addLong("C_S_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_IGNORE_ID", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ID_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "40");
|
||||||
|
model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
|
||||||
|
model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_TRANSLATION_MODE", "2");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_protocol_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
target_rd_socket = mp_impl->target_rd_socket;
|
||||||
|
target_wr_socket = mp_impl->target_wr_socket;
|
||||||
|
initiator_rd_socket = mp_impl->initiator_rd_socket;
|
||||||
|
initiator_wr_socket = mp_impl->initiator_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0_sc::~pl_eth_10g_auto_pc_0_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_PC_0_SC_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_PC_0_SC_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
class axi_protocol_converter;
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_pc_0_sc : public sc_core::sc_module
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0_sc(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_0_sc();
|
||||||
|
|
||||||
|
// module socket-to-socket AXI TLM interfaces
|
||||||
|
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
|
||||||
|
// module socket-to-socket TLM interfaces
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
axi_protocol_converter* mp_impl;
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_0_sc(const pl_eth_10g_auto_pc_0_sc&);
|
||||||
|
const pl_eth_10g_auto_pc_0_sc& operator=(const pl_eth_10g_auto_pc_0_sc&);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_PC_0_SC_H_
|
||||||
|
|
@ -0,0 +1,254 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
// Filename: pl_eth_10g_auto_pc_0_stub.sv
|
||||||
|
// Description: This HDL file is intended to be used with following simulators only:
|
||||||
|
//
|
||||||
|
// Vivado Simulator (XSim)
|
||||||
|
// Cadence Xcelium Simulator
|
||||||
|
// Aldec Riviera-PRO Simulator
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
`ifdef XILINX_SIMULATOR
|
||||||
|
|
||||||
|
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||||
|
`define XILINX_SIMULATOR_BITASBOOL
|
||||||
|
typedef bit bit_as_bool;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_pc_0 (
|
||||||
|
input bit_as_bool aclk,
|
||||||
|
input bit_as_bool aresetn,
|
||||||
|
input bit [39 : 0] s_axi_awaddr,
|
||||||
|
input bit [7 : 0] s_axi_awlen,
|
||||||
|
input bit [2 : 0] s_axi_awsize,
|
||||||
|
input bit [1 : 0] s_axi_awburst,
|
||||||
|
input bit [0 : 0] s_axi_awlock,
|
||||||
|
input bit [3 : 0] s_axi_awcache,
|
||||||
|
input bit [2 : 0] s_axi_awprot,
|
||||||
|
input bit [3 : 0] s_axi_awregion,
|
||||||
|
input bit [3 : 0] s_axi_awqos,
|
||||||
|
input bit_as_bool s_axi_awvalid,
|
||||||
|
output bit_as_bool s_axi_awready,
|
||||||
|
input bit [31 : 0] s_axi_wdata,
|
||||||
|
input bit [3 : 0] s_axi_wstrb,
|
||||||
|
input bit_as_bool s_axi_wlast,
|
||||||
|
input bit_as_bool s_axi_wvalid,
|
||||||
|
output bit_as_bool s_axi_wready,
|
||||||
|
output bit [1 : 0] s_axi_bresp,
|
||||||
|
output bit_as_bool s_axi_bvalid,
|
||||||
|
input bit_as_bool s_axi_bready,
|
||||||
|
input bit [39 : 0] s_axi_araddr,
|
||||||
|
input bit [7 : 0] s_axi_arlen,
|
||||||
|
input bit [2 : 0] s_axi_arsize,
|
||||||
|
input bit [1 : 0] s_axi_arburst,
|
||||||
|
input bit [0 : 0] s_axi_arlock,
|
||||||
|
input bit [3 : 0] s_axi_arcache,
|
||||||
|
input bit [2 : 0] s_axi_arprot,
|
||||||
|
input bit [3 : 0] s_axi_arregion,
|
||||||
|
input bit [3 : 0] s_axi_arqos,
|
||||||
|
input bit_as_bool s_axi_arvalid,
|
||||||
|
output bit_as_bool s_axi_arready,
|
||||||
|
output bit [31 : 0] s_axi_rdata,
|
||||||
|
output bit [1 : 0] s_axi_rresp,
|
||||||
|
output bit_as_bool s_axi_rlast,
|
||||||
|
output bit_as_bool s_axi_rvalid,
|
||||||
|
input bit_as_bool s_axi_rready,
|
||||||
|
output bit [39 : 0] m_axi_awaddr,
|
||||||
|
output bit [2 : 0] m_axi_awprot,
|
||||||
|
output bit_as_bool m_axi_awvalid,
|
||||||
|
input bit_as_bool m_axi_awready,
|
||||||
|
output bit [31 : 0] m_axi_wdata,
|
||||||
|
output bit [3 : 0] m_axi_wstrb,
|
||||||
|
output bit_as_bool m_axi_wvalid,
|
||||||
|
input bit_as_bool m_axi_wready,
|
||||||
|
input bit [1 : 0] m_axi_bresp,
|
||||||
|
input bit_as_bool m_axi_bvalid,
|
||||||
|
output bit_as_bool m_axi_bready,
|
||||||
|
output bit [39 : 0] m_axi_araddr,
|
||||||
|
output bit [2 : 0] m_axi_arprot,
|
||||||
|
output bit_as_bool m_axi_arvalid,
|
||||||
|
input bit_as_bool m_axi_arready,
|
||||||
|
input bit [31 : 0] m_axi_rdata,
|
||||||
|
input bit [1 : 0] m_axi_rresp,
|
||||||
|
input bit_as_bool m_axi_rvalid,
|
||||||
|
output bit_as_bool m_axi_rready
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef XCELIUM
|
||||||
|
(* XMSC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_pc_0 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||||
|
(* integer foreign = "SystemC";
|
||||||
|
*);
|
||||||
|
input bit aclk;
|
||||||
|
input bit aresetn;
|
||||||
|
input bit [39 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [31 : 0] s_axi_wdata;
|
||||||
|
input bit [3 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [39 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef RIVIERA
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_pc_0 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||||
|
input bit aclk;
|
||||||
|
input bit aresetn;
|
||||||
|
input bit [39 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [31 : 0] s_axi_wdata;
|
||||||
|
input bit [3 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [39 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
#include "axi_protocol_converter.h"
|
||||||
|
#include <sstream>
|
||||||
|
|
||||||
|
axi_protocol_converter::axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
|
||||||
|
sc_module(module_name) {
|
||||||
|
initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
|
||||||
|
initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
|
||||||
|
target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
|
||||||
|
target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
|
||||||
|
P1 = new xtlm::xtlm_aximm_passthru_module("P1");
|
||||||
|
P2 = new xtlm::xtlm_aximm_passthru_module("P2");
|
||||||
|
P1->initiator_socket->bind(*initiator_rd_socket);
|
||||||
|
P2->initiator_socket->bind(*initiator_wr_socket);
|
||||||
|
target_rd_socket->bind(*(P1->target_socket));
|
||||||
|
target_wr_socket->bind(*(P2->target_socket));
|
||||||
|
}
|
||||||
|
|
||||||
|
axi_protocol_converter::~axi_protocol_converter() {
|
||||||
|
delete initiator_wr_socket;
|
||||||
|
delete initiator_rd_socket;
|
||||||
|
delete target_wr_socket;
|
||||||
|
delete target_rd_socket;
|
||||||
|
delete P1;
|
||||||
|
delete P2;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
#ifndef _axi_protocol_converter_
|
||||||
|
#define _axi_protocol_converter_
|
||||||
|
#include <xtlm.h>
|
||||||
|
#include <utils/xtlm_aximm_passthru_module.h>
|
||||||
|
#include <systemc>
|
||||||
|
|
||||||
|
class axi_protocol_converter:public sc_module{
|
||||||
|
public:
|
||||||
|
axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||||
|
virtual ~axi_protocol_converter();
|
||||||
|
SC_HAS_PROCESS(axi_protocol_converter);
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
sc_in<bool> aclk;
|
||||||
|
sc_in<bool> aresetn;
|
||||||
|
private:
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P1;
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P2;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
@ -0,0 +1,347 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
(* X_CORE_INFO = "axi_protocol_converter_v2_1_22_axi_protocol_converter,Vivado 2020.2" *)
|
||||||
|
(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_pc_0,axi_protocol_converter_v2_1_22_axi_protocol_converter,{}" *)
|
||||||
|
(* CORE_GENERATION_INFO = "pl_eth_10g_auto_pc_0,axi_protocol_converter_v2_1_22_axi_protocol_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=40,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI\
|
||||||
|
_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_pc_0 (
|
||||||
|
aclk,
|
||||||
|
aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||||
|
input wire aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||||
|
input wire aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [31 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [3 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [39 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [39 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_protocol_converter_v2_1_22_axi_protocol_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_M_AXI_PROTOCOL(2),
|
||||||
|
.C_S_AXI_PROTOCOL(0),
|
||||||
|
.C_IGNORE_ID(1),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(40),
|
||||||
|
.C_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_TRANSLATION_MODE(2)
|
||||||
|
) inst (
|
||||||
|
.aclk(aclk),
|
||||||
|
.aresetn(aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(),
|
||||||
|
.m_axi_arsize(),
|
||||||
|
.m_axi_arburst(),
|
||||||
|
.m_axi_arlock(),
|
||||||
|
.m_axi_arcache(),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(),
|
||||||
|
.m_axi_arqos(),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(1'H1),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,50 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports aclk]
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,538 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_PC_1_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_PC_1_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_pc_1_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_pc_1 : public pl_eth_10g_auto_pc_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > aclk;
|
||||||
|
sc_core::sc_in< bool > aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_PC_1_H_
|
||||||
|
|
@ -0,0 +1,345 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_pc_1 (
|
||||||
|
aclk,
|
||||||
|
aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||||
|
input wire aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||||
|
input wire aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [31 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [3 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_protocol_converter_v2_1_22_axi_protocol_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_M_AXI_PROTOCOL(2),
|
||||||
|
.C_S_AXI_PROTOCOL(0),
|
||||||
|
.C_IGNORE_ID(1),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_TRANSLATION_MODE(2)
|
||||||
|
) inst (
|
||||||
|
.aclk(aclk),
|
||||||
|
.aresetn(aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(),
|
||||||
|
.m_axi_arsize(),
|
||||||
|
.m_axi_arburst(),
|
||||||
|
.m_axi_arlock(),
|
||||||
|
.m_axi_arcache(),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(),
|
||||||
|
.m_axi_arqos(),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(1'H1),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_pc_1_sc.h"
|
||||||
|
|
||||||
|
#include "axi_protocol_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1_sc::pl_eth_10g_auto_pc_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_pc_1", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_M_AXI_PROTOCOL", "2");
|
||||||
|
model_param_props.addLong("C_S_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_IGNORE_ID", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ID_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
|
||||||
|
model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_TRANSLATION_MODE", "2");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_protocol_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
target_rd_socket = mp_impl->target_rd_socket;
|
||||||
|
target_wr_socket = mp_impl->target_wr_socket;
|
||||||
|
initiator_rd_socket = mp_impl->initiator_rd_socket;
|
||||||
|
initiator_wr_socket = mp_impl->initiator_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1_sc::~pl_eth_10g_auto_pc_1_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_PC_1_SC_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_PC_1_SC_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
class axi_protocol_converter;
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_pc_1_sc : public sc_core::sc_module
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1_sc(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_pc_1_sc();
|
||||||
|
|
||||||
|
// module socket-to-socket AXI TLM interfaces
|
||||||
|
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
|
||||||
|
// module socket-to-socket TLM interfaces
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
axi_protocol_converter* mp_impl;
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_pc_1_sc(const pl_eth_10g_auto_pc_1_sc&);
|
||||||
|
const pl_eth_10g_auto_pc_1_sc& operator=(const pl_eth_10g_auto_pc_1_sc&);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_PC_1_SC_H_
|
||||||
|
|
@ -0,0 +1,254 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
// Filename: pl_eth_10g_auto_pc_1_stub.sv
|
||||||
|
// Description: This HDL file is intended to be used with following simulators only:
|
||||||
|
//
|
||||||
|
// Vivado Simulator (XSim)
|
||||||
|
// Cadence Xcelium Simulator
|
||||||
|
// Aldec Riviera-PRO Simulator
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
`ifdef XILINX_SIMULATOR
|
||||||
|
|
||||||
|
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||||
|
`define XILINX_SIMULATOR_BITASBOOL
|
||||||
|
typedef bit bit_as_bool;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_pc_1 (
|
||||||
|
input bit_as_bool aclk,
|
||||||
|
input bit_as_bool aresetn,
|
||||||
|
input bit [31 : 0] s_axi_awaddr,
|
||||||
|
input bit [7 : 0] s_axi_awlen,
|
||||||
|
input bit [2 : 0] s_axi_awsize,
|
||||||
|
input bit [1 : 0] s_axi_awburst,
|
||||||
|
input bit [0 : 0] s_axi_awlock,
|
||||||
|
input bit [3 : 0] s_axi_awcache,
|
||||||
|
input bit [2 : 0] s_axi_awprot,
|
||||||
|
input bit [3 : 0] s_axi_awregion,
|
||||||
|
input bit [3 : 0] s_axi_awqos,
|
||||||
|
input bit_as_bool s_axi_awvalid,
|
||||||
|
output bit_as_bool s_axi_awready,
|
||||||
|
input bit [31 : 0] s_axi_wdata,
|
||||||
|
input bit [3 : 0] s_axi_wstrb,
|
||||||
|
input bit_as_bool s_axi_wlast,
|
||||||
|
input bit_as_bool s_axi_wvalid,
|
||||||
|
output bit_as_bool s_axi_wready,
|
||||||
|
output bit [1 : 0] s_axi_bresp,
|
||||||
|
output bit_as_bool s_axi_bvalid,
|
||||||
|
input bit_as_bool s_axi_bready,
|
||||||
|
input bit [31 : 0] s_axi_araddr,
|
||||||
|
input bit [7 : 0] s_axi_arlen,
|
||||||
|
input bit [2 : 0] s_axi_arsize,
|
||||||
|
input bit [1 : 0] s_axi_arburst,
|
||||||
|
input bit [0 : 0] s_axi_arlock,
|
||||||
|
input bit [3 : 0] s_axi_arcache,
|
||||||
|
input bit [2 : 0] s_axi_arprot,
|
||||||
|
input bit [3 : 0] s_axi_arregion,
|
||||||
|
input bit [3 : 0] s_axi_arqos,
|
||||||
|
input bit_as_bool s_axi_arvalid,
|
||||||
|
output bit_as_bool s_axi_arready,
|
||||||
|
output bit [31 : 0] s_axi_rdata,
|
||||||
|
output bit [1 : 0] s_axi_rresp,
|
||||||
|
output bit_as_bool s_axi_rlast,
|
||||||
|
output bit_as_bool s_axi_rvalid,
|
||||||
|
input bit_as_bool s_axi_rready,
|
||||||
|
output bit [31 : 0] m_axi_awaddr,
|
||||||
|
output bit [2 : 0] m_axi_awprot,
|
||||||
|
output bit_as_bool m_axi_awvalid,
|
||||||
|
input bit_as_bool m_axi_awready,
|
||||||
|
output bit [31 : 0] m_axi_wdata,
|
||||||
|
output bit [3 : 0] m_axi_wstrb,
|
||||||
|
output bit_as_bool m_axi_wvalid,
|
||||||
|
input bit_as_bool m_axi_wready,
|
||||||
|
input bit [1 : 0] m_axi_bresp,
|
||||||
|
input bit_as_bool m_axi_bvalid,
|
||||||
|
output bit_as_bool m_axi_bready,
|
||||||
|
output bit [31 : 0] m_axi_araddr,
|
||||||
|
output bit [2 : 0] m_axi_arprot,
|
||||||
|
output bit_as_bool m_axi_arvalid,
|
||||||
|
input bit_as_bool m_axi_arready,
|
||||||
|
input bit [31 : 0] m_axi_rdata,
|
||||||
|
input bit [1 : 0] m_axi_rresp,
|
||||||
|
input bit_as_bool m_axi_rvalid,
|
||||||
|
output bit_as_bool m_axi_rready
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef XCELIUM
|
||||||
|
(* XMSC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_pc_1 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||||
|
(* integer foreign = "SystemC";
|
||||||
|
*);
|
||||||
|
input bit aclk;
|
||||||
|
input bit aresetn;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [31 : 0] s_axi_wdata;
|
||||||
|
input bit [3 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef RIVIERA
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_pc_1 (aclk,aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||||
|
input bit aclk;
|
||||||
|
input bit aresetn;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [31 : 0] s_axi_wdata;
|
||||||
|
input bit [3 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [31 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
#include "axi_protocol_converter.h"
|
||||||
|
#include <sstream>
|
||||||
|
|
||||||
|
axi_protocol_converter::axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
|
||||||
|
sc_module(module_name) {
|
||||||
|
initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
|
||||||
|
initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
|
||||||
|
target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
|
||||||
|
target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
|
||||||
|
P1 = new xtlm::xtlm_aximm_passthru_module("P1");
|
||||||
|
P2 = new xtlm::xtlm_aximm_passthru_module("P2");
|
||||||
|
P1->initiator_socket->bind(*initiator_rd_socket);
|
||||||
|
P2->initiator_socket->bind(*initiator_wr_socket);
|
||||||
|
target_rd_socket->bind(*(P1->target_socket));
|
||||||
|
target_wr_socket->bind(*(P2->target_socket));
|
||||||
|
}
|
||||||
|
|
||||||
|
axi_protocol_converter::~axi_protocol_converter() {
|
||||||
|
delete initiator_wr_socket;
|
||||||
|
delete initiator_rd_socket;
|
||||||
|
delete target_wr_socket;
|
||||||
|
delete target_rd_socket;
|
||||||
|
delete P1;
|
||||||
|
delete P2;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
#ifndef _axi_protocol_converter_
|
||||||
|
#define _axi_protocol_converter_
|
||||||
|
#include <xtlm.h>
|
||||||
|
#include <utils/xtlm_aximm_passthru_module.h>
|
||||||
|
#include <systemc>
|
||||||
|
|
||||||
|
class axi_protocol_converter:public sc_module{
|
||||||
|
public:
|
||||||
|
axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||||
|
virtual ~axi_protocol_converter();
|
||||||
|
SC_HAS_PROCESS(axi_protocol_converter);
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
sc_in<bool> aclk;
|
||||||
|
sc_in<bool> aresetn;
|
||||||
|
private:
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P1;
|
||||||
|
xtlm::xtlm_aximm_passthru_module *P2;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
@ -0,0 +1,347 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
(* X_CORE_INFO = "axi_protocol_converter_v2_1_22_axi_protocol_converter,Vivado 2020.2" *)
|
||||||
|
(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_pc_1,axi_protocol_converter_v2_1_22_axi_protocol_converter,{}" *)
|
||||||
|
(* CORE_GENERATION_INFO = "pl_eth_10g_auto_pc_1,axi_protocol_converter_v2_1_22_axi_protocol_converter,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI\
|
||||||
|
_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_pc_1 (
|
||||||
|
aclk,
|
||||||
|
aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||||
|
input wire aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||||
|
input wire aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [31 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [3 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
|
||||||
|
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [31 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [3 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [31 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1\
|
||||||
|
, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_protocol_converter_v2_1_22_axi_protocol_converter #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_M_AXI_PROTOCOL(2),
|
||||||
|
.C_S_AXI_PROTOCOL(0),
|
||||||
|
.C_IGNORE_ID(1),
|
||||||
|
.C_AXI_ID_WIDTH(1),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_AXI_DATA_WIDTH(32),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||||
|
.C_AXI_AWUSER_WIDTH(1),
|
||||||
|
.C_AXI_ARUSER_WIDTH(1),
|
||||||
|
.C_AXI_WUSER_WIDTH(1),
|
||||||
|
.C_AXI_RUSER_WIDTH(1),
|
||||||
|
.C_AXI_BUSER_WIDTH(1),
|
||||||
|
.C_TRANSLATION_MODE(2)
|
||||||
|
) inst (
|
||||||
|
.aclk(aclk),
|
||||||
|
.aresetn(aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awuser(1'H0),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wid(1'H0),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wuser(1'H0),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_buser(),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_aruser(1'H0),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_ruser(),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_awid(),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awuser(),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wid(),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wuser(),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bid(1'H0),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_buser(1'H0),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_arid(),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(),
|
||||||
|
.m_axi_arsize(),
|
||||||
|
.m_axi_arburst(),
|
||||||
|
.m_axi_arlock(),
|
||||||
|
.m_axi_arcache(),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(),
|
||||||
|
.m_axi_arqos(),
|
||||||
|
.m_axi_aruser(),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rid(1'H0),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(1'H1),
|
||||||
|
.m_axi_ruser(1'H0),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,7 @@
|
||||||
|
###############################################################################################################
|
||||||
|
# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_us_0"
|
||||||
|
###############################################################################################################
|
||||||
|
#
|
||||||
|
# This component is not configured to perform asynchronous clock-domain-crossing.
|
||||||
|
# No timing core-level constraints are needed.
|
||||||
|
# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,648 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_US_0_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_US_0_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_us_0_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_us_0 : public pl_eth_10g_auto_us_0_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_0();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_awvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_awready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||||
|
sc_core::sc_in< bool > s_axi_wlast;
|
||||||
|
sc_core::sc_in< bool > s_axi_wvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_wready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_bvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_bready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_awvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_awready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
|
||||||
|
sc_core::sc_out< bool > m_axi_wlast;
|
||||||
|
sc_core::sc_out< bool > m_axi_wvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_wready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_bvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_bready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_awlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_US_0_H_
|
||||||
|
|
@ -0,0 +1,379 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_us_0 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [31 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [3 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
|
||||||
|
UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [127 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
|
||||||
|
UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_dwidth_converter_v2_1_22_top #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_S_AXI_ID_WIDTH(1),
|
||||||
|
.C_SUPPORTS_ID(0),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_S_AXI_DATA_WIDTH(32),
|
||||||
|
.C_M_AXI_DATA_WIDTH(128),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_FIFO_MODE(0),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(0),
|
||||||
|
.C_MAX_SPLIT_BEATS(16),
|
||||||
|
.C_PACKING_LEVEL(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(1'H0),
|
||||||
|
.m_axi_aresetn(1'H0),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_us_0_sc.h"
|
||||||
|
|
||||||
|
#include "axi_dwidth_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0_sc::pl_eth_10g_auto_us_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_us_0", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_SUPPORTS_ID", "0");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_M_AXI_DATA_WIDTH", "128");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||||
|
model_param_props.addLong("C_FIFO_MODE", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
|
||||||
|
model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
|
||||||
|
model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
|
||||||
|
model_param_props.addLong("C_MAX_SPLIT_BEATS", "16");
|
||||||
|
model_param_props.addLong("C_PACKING_LEVEL", "1");
|
||||||
|
model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_dwidth_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
target_rd_socket = mp_impl->target_rd_socket;
|
||||||
|
target_wr_socket = mp_impl->target_wr_socket;
|
||||||
|
initiator_rd_socket = mp_impl->initiator_rd_socket;
|
||||||
|
initiator_wr_socket = mp_impl->initiator_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0_sc::~pl_eth_10g_auto_us_0_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_US_0_SC_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_US_0_SC_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
class axi_dwidth_converter;
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_us_0_sc : public sc_core::sc_module
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0_sc(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_0_sc();
|
||||||
|
|
||||||
|
// module socket-to-socket AXI TLM interfaces
|
||||||
|
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
|
||||||
|
// module socket-to-socket TLM interfaces
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
axi_dwidth_converter* mp_impl;
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_0_sc(const pl_eth_10g_auto_us_0_sc&);
|
||||||
|
const pl_eth_10g_auto_us_0_sc& operator=(const pl_eth_10g_auto_us_0_sc&);
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_US_0_SC_H_
|
||||||
|
|
@ -0,0 +1,302 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
// Filename: pl_eth_10g_auto_us_0_stub.sv
|
||||||
|
// Description: This HDL file is intended to be used with following simulators only:
|
||||||
|
//
|
||||||
|
// Vivado Simulator (XSim)
|
||||||
|
// Cadence Xcelium Simulator
|
||||||
|
// Aldec Riviera-PRO Simulator
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------------
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
`ifdef XILINX_SIMULATOR
|
||||||
|
|
||||||
|
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||||
|
`define XILINX_SIMULATOR_BITASBOOL
|
||||||
|
typedef bit bit_as_bool;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_us_0 (
|
||||||
|
input bit_as_bool s_axi_aclk,
|
||||||
|
input bit_as_bool s_axi_aresetn,
|
||||||
|
input bit [31 : 0] s_axi_awaddr,
|
||||||
|
input bit [7 : 0] s_axi_awlen,
|
||||||
|
input bit [2 : 0] s_axi_awsize,
|
||||||
|
input bit [1 : 0] s_axi_awburst,
|
||||||
|
input bit [0 : 0] s_axi_awlock,
|
||||||
|
input bit [3 : 0] s_axi_awcache,
|
||||||
|
input bit [2 : 0] s_axi_awprot,
|
||||||
|
input bit [3 : 0] s_axi_awregion,
|
||||||
|
input bit [3 : 0] s_axi_awqos,
|
||||||
|
input bit_as_bool s_axi_awvalid,
|
||||||
|
output bit_as_bool s_axi_awready,
|
||||||
|
input bit [31 : 0] s_axi_wdata,
|
||||||
|
input bit [3 : 0] s_axi_wstrb,
|
||||||
|
input bit_as_bool s_axi_wlast,
|
||||||
|
input bit_as_bool s_axi_wvalid,
|
||||||
|
output bit_as_bool s_axi_wready,
|
||||||
|
output bit [1 : 0] s_axi_bresp,
|
||||||
|
output bit_as_bool s_axi_bvalid,
|
||||||
|
input bit_as_bool s_axi_bready,
|
||||||
|
input bit [31 : 0] s_axi_araddr,
|
||||||
|
input bit [7 : 0] s_axi_arlen,
|
||||||
|
input bit [2 : 0] s_axi_arsize,
|
||||||
|
input bit [1 : 0] s_axi_arburst,
|
||||||
|
input bit [0 : 0] s_axi_arlock,
|
||||||
|
input bit [3 : 0] s_axi_arcache,
|
||||||
|
input bit [2 : 0] s_axi_arprot,
|
||||||
|
input bit [3 : 0] s_axi_arregion,
|
||||||
|
input bit [3 : 0] s_axi_arqos,
|
||||||
|
input bit_as_bool s_axi_arvalid,
|
||||||
|
output bit_as_bool s_axi_arready,
|
||||||
|
output bit [31 : 0] s_axi_rdata,
|
||||||
|
output bit [1 : 0] s_axi_rresp,
|
||||||
|
output bit_as_bool s_axi_rlast,
|
||||||
|
output bit_as_bool s_axi_rvalid,
|
||||||
|
input bit_as_bool s_axi_rready,
|
||||||
|
output bit [31 : 0] m_axi_awaddr,
|
||||||
|
output bit [7 : 0] m_axi_awlen,
|
||||||
|
output bit [2 : 0] m_axi_awsize,
|
||||||
|
output bit [1 : 0] m_axi_awburst,
|
||||||
|
output bit [0 : 0] m_axi_awlock,
|
||||||
|
output bit [3 : 0] m_axi_awcache,
|
||||||
|
output bit [2 : 0] m_axi_awprot,
|
||||||
|
output bit [3 : 0] m_axi_awregion,
|
||||||
|
output bit [3 : 0] m_axi_awqos,
|
||||||
|
output bit_as_bool m_axi_awvalid,
|
||||||
|
input bit_as_bool m_axi_awready,
|
||||||
|
output bit [127 : 0] m_axi_wdata,
|
||||||
|
output bit [15 : 0] m_axi_wstrb,
|
||||||
|
output bit_as_bool m_axi_wlast,
|
||||||
|
output bit_as_bool m_axi_wvalid,
|
||||||
|
input bit_as_bool m_axi_wready,
|
||||||
|
input bit [1 : 0] m_axi_bresp,
|
||||||
|
input bit_as_bool m_axi_bvalid,
|
||||||
|
output bit_as_bool m_axi_bready,
|
||||||
|
output bit [31 : 0] m_axi_araddr,
|
||||||
|
output bit [7 : 0] m_axi_arlen,
|
||||||
|
output bit [2 : 0] m_axi_arsize,
|
||||||
|
output bit [1 : 0] m_axi_arburst,
|
||||||
|
output bit [0 : 0] m_axi_arlock,
|
||||||
|
output bit [3 : 0] m_axi_arcache,
|
||||||
|
output bit [2 : 0] m_axi_arprot,
|
||||||
|
output bit [3 : 0] m_axi_arregion,
|
||||||
|
output bit [3 : 0] m_axi_arqos,
|
||||||
|
output bit_as_bool m_axi_arvalid,
|
||||||
|
input bit_as_bool m_axi_arready,
|
||||||
|
input bit [127 : 0] m_axi_rdata,
|
||||||
|
input bit [1 : 0] m_axi_rresp,
|
||||||
|
input bit_as_bool m_axi_rlast,
|
||||||
|
input bit_as_bool m_axi_rvalid,
|
||||||
|
output bit_as_bool m_axi_rready
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef XCELIUM
|
||||||
|
(* XMSC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_us_0 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
(* integer foreign = "SystemC";
|
||||||
|
*);
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [31 : 0] s_axi_wdata;
|
||||||
|
input bit [3 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [127 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
||||||
|
`ifdef RIVIERA
|
||||||
|
(* SC_MODULE_EXPORT *)
|
||||||
|
module pl_eth_10g_auto_us_0 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awregion,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arregion,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awregion,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arregion,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||||
|
input bit s_axi_aclk;
|
||||||
|
input bit s_axi_aresetn;
|
||||||
|
input bit [31 : 0] s_axi_awaddr;
|
||||||
|
input bit [7 : 0] s_axi_awlen;
|
||||||
|
input bit [2 : 0] s_axi_awsize;
|
||||||
|
input bit [1 : 0] s_axi_awburst;
|
||||||
|
input bit [0 : 0] s_axi_awlock;
|
||||||
|
input bit [3 : 0] s_axi_awcache;
|
||||||
|
input bit [2 : 0] s_axi_awprot;
|
||||||
|
input bit [3 : 0] s_axi_awregion;
|
||||||
|
input bit [3 : 0] s_axi_awqos;
|
||||||
|
input bit s_axi_awvalid;
|
||||||
|
output wire s_axi_awready;
|
||||||
|
input bit [31 : 0] s_axi_wdata;
|
||||||
|
input bit [3 : 0] s_axi_wstrb;
|
||||||
|
input bit s_axi_wlast;
|
||||||
|
input bit s_axi_wvalid;
|
||||||
|
output wire s_axi_wready;
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
input bit s_axi_bready;
|
||||||
|
input bit [31 : 0] s_axi_araddr;
|
||||||
|
input bit [7 : 0] s_axi_arlen;
|
||||||
|
input bit [2 : 0] s_axi_arsize;
|
||||||
|
input bit [1 : 0] s_axi_arburst;
|
||||||
|
input bit [0 : 0] s_axi_arlock;
|
||||||
|
input bit [3 : 0] s_axi_arcache;
|
||||||
|
input bit [2 : 0] s_axi_arprot;
|
||||||
|
input bit [3 : 0] s_axi_arregion;
|
||||||
|
input bit [3 : 0] s_axi_arqos;
|
||||||
|
input bit s_axi_arvalid;
|
||||||
|
output wire s_axi_arready;
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
input bit s_axi_rready;
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
input bit m_axi_awready;
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
input bit m_axi_wready;
|
||||||
|
input bit [1 : 0] m_axi_bresp;
|
||||||
|
input bit m_axi_bvalid;
|
||||||
|
output wire m_axi_bready;
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
input bit m_axi_arready;
|
||||||
|
input bit [127 : 0] m_axi_rdata;
|
||||||
|
input bit [1 : 0] m_axi_rresp;
|
||||||
|
input bit m_axi_rlast;
|
||||||
|
input bit m_axi_rvalid;
|
||||||
|
output wire m_axi_rready;
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,527 @@
|
||||||
|
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
||||||
|
// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#include "axi_dwidth_converter.h"
|
||||||
|
#define PAYLOAD_LOG_LEVEL 3
|
||||||
|
|
||||||
|
axi_dwidth_converter::axi_dwidth_converter(sc_core::sc_module_name p_name,
|
||||||
|
xsc::common_cpp::properties& m_properties) :
|
||||||
|
sc_core::sc_module(p_name), m_wr_trans(nullptr), m_rd_trans(nullptr), m_response_list(
|
||||||
|
nullptr),m_logger((std::string) (p_name)) {
|
||||||
|
|
||||||
|
initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket(
|
||||||
|
"rd_trace_socket", 32);
|
||||||
|
initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket(
|
||||||
|
"wr_trace_socket", 32);
|
||||||
|
target_rd_socket = new xtlm::xtlm_aximm_target_socket("rd_trace_socket",
|
||||||
|
32);
|
||||||
|
target_wr_socket = new xtlm::xtlm_aximm_target_socket("wr_trace_socket",
|
||||||
|
32);
|
||||||
|
rd_target_util = new xtlm::xtlm_aximm_target_rd_socket_util("rd_tar_util",
|
||||||
|
xtlm::aximm::TRANSACTION, 32);
|
||||||
|
wr_target_util = new xtlm::xtlm_aximm_target_wr_socket_util("wr_tar_util",
|
||||||
|
xtlm::aximm::TRANSACTION, 32);
|
||||||
|
rd_initiator_util = new xtlm::xtlm_aximm_initiator_rd_socket_util(
|
||||||
|
"rd_ini_util", xtlm::aximm::TRANSACTION, 32);
|
||||||
|
wr_initiator_util = new xtlm::xtlm_aximm_initiator_wr_socket_util(
|
||||||
|
"wr_ini_util", xtlm::aximm::TRANSACTION, 32);
|
||||||
|
target_rd_socket->bind(rd_target_util->rd_socket);
|
||||||
|
target_wr_socket->bind(wr_target_util->wr_socket);
|
||||||
|
rd_initiator_util->rd_socket.bind(*initiator_rd_socket);
|
||||||
|
wr_initiator_util->wr_socket.bind(*initiator_wr_socket);
|
||||||
|
|
||||||
|
mem_manager = new xtlm::xtlm_aximm_mem_manager();
|
||||||
|
SI_DATA_WIDTH = m_properties.getLongLong("C_S_AXI_DATA_WIDTH")/8;
|
||||||
|
MI_DATA_WIDTH = m_properties.getLongLong("C_M_AXI_DATA_WIDTH")/8;
|
||||||
|
FIFO_MODE = m_properties.getLongLong("C_FIFO_MODE");
|
||||||
|
|
||||||
|
|
||||||
|
ratio = 0; //SI_DATA_WIDTH/MI_DATA_WIDTH;
|
||||||
|
if(FIFO_MODE!=2)
|
||||||
|
{
|
||||||
|
m_axi_aclk(clk);
|
||||||
|
m_axi_aresetn(resetn);
|
||||||
|
}
|
||||||
|
|
||||||
|
SC_METHOD(wr_handler);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_target_util->transaction_available;
|
||||||
|
sensitive << event_trig_wr_handler;
|
||||||
|
|
||||||
|
SC_METHOD(rd_handler);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << rd_target_util->addr_available;
|
||||||
|
sensitive << event_trig_rd_handler;
|
||||||
|
|
||||||
|
SC_METHOD(m_downsize_interface_txn_sender);
|
||||||
|
sensitive << event_downsize_trig_txn_sender;
|
||||||
|
sensitive << wr_initiator_util->transaction_sampled;
|
||||||
|
sensitive << rd_initiator_util->transaction_sampled;
|
||||||
|
dont_initialize();
|
||||||
|
|
||||||
|
SC_METHOD(m_upsize_interface_txn_sender);
|
||||||
|
sensitive << event_upsize_trig_txn_sender;
|
||||||
|
dont_initialize();
|
||||||
|
|
||||||
|
SC_METHOD(m_downsize_interface_response_sender);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_initiator_util->resp_available;
|
||||||
|
sensitive << rd_initiator_util->data_available;
|
||||||
|
sensitive << rd_target_util->data_sampled;
|
||||||
|
sensitive << wr_target_util->resp_sampled;
|
||||||
|
|
||||||
|
SC_METHOD(m_upsize_interface_response_sender);
|
||||||
|
dont_initialize();
|
||||||
|
sensitive << wr_initiator_util->resp_available;
|
||||||
|
sensitive << rd_initiator_util->data_available;
|
||||||
|
sensitive << rd_target_util->data_sampled;
|
||||||
|
sensitive << wr_target_util->resp_sampled;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::wr_handler() {
|
||||||
|
if(wr_initiator_util->is_slave_ready() &&
|
||||||
|
wr_target_util->is_trans_available() )
|
||||||
|
{
|
||||||
|
m_wr_trans = wr_target_util->get_transaction();
|
||||||
|
m_log_msg = "Sampled Write transaction on slave interface : " + std::to_string(m_wr_trans->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG);
|
||||||
|
ratio = m_wr_trans->get_burst_size() / MI_DATA_WIDTH;
|
||||||
|
if (ratio <= 1)
|
||||||
|
wr_upsizing();
|
||||||
|
else
|
||||||
|
wr_downsizing();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::rd_handler() {
|
||||||
|
if(rd_initiator_util->is_slave_ready() &&
|
||||||
|
rd_target_util->is_trans_available() )
|
||||||
|
{
|
||||||
|
m_rd_trans = rd_target_util->get_transaction();
|
||||||
|
|
||||||
|
m_log_msg = "Sampled Read transaction on slave interface : " + std::to_string( m_rd_trans->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::001",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
ratio = m_rd_trans->get_burst_size() / MI_DATA_WIDTH;
|
||||||
|
if (ratio <= 1)
|
||||||
|
rd_upsizing();
|
||||||
|
else
|
||||||
|
rd_downsizing();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::rd_downsizing() {
|
||||||
|
auto beat_l = m_rd_trans->get_burst_length();
|
||||||
|
auto data = m_rd_trans->get_data_ptr();
|
||||||
|
auto new_beat_l = beat_l * (ratio);
|
||||||
|
auto strb = m_rd_trans->get_byte_enable_ptr();
|
||||||
|
auto s_addr = m_rd_trans->get_address();
|
||||||
|
auto num_byte_counter = 0;
|
||||||
|
auto total_num_bytes = beat_l * m_rd_trans->get_burst_size();
|
||||||
|
auto cur_beat_l = 0;
|
||||||
|
auto t_total_txns = 0;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down Sizing input transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_response_list = new std::list<xtlm::aximm_payload*>;
|
||||||
|
do {
|
||||||
|
if (new_beat_l > 256)
|
||||||
|
cur_beat_l = 256;
|
||||||
|
else
|
||||||
|
cur_beat_l = new_beat_l;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_rd_trans);
|
||||||
|
t_trans->set_address(s_addr + num_byte_counter);
|
||||||
|
t_trans->set_data_ptr(data + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH);
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_length(cur_beat_l);
|
||||||
|
num_byte_counter += cur_beat_l * MI_DATA_WIDTH ;
|
||||||
|
m_interface_rd_payload_queue.push(t_trans);
|
||||||
|
m_response_list->push_back(t_trans);
|
||||||
|
t_total_txns++;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down sized output transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
} while (num_byte_counter < total_num_bytes);
|
||||||
|
m_response_mapper_downsize[m_rd_trans] = m_response_list;
|
||||||
|
event_downsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::wr_downsizing() {
|
||||||
|
auto beat_l = m_wr_trans->get_burst_length();
|
||||||
|
auto data = m_wr_trans->get_data_ptr();
|
||||||
|
auto strb = m_wr_trans->get_byte_enable_ptr();
|
||||||
|
auto new_beat_l = beat_l * (ratio);
|
||||||
|
auto s_addr = m_wr_trans->get_address();
|
||||||
|
auto num_byte_counter = 0;
|
||||||
|
auto total_num_bytes = beat_l * m_wr_trans->get_burst_size();
|
||||||
|
auto cur_beat_l = 0;
|
||||||
|
auto t_total_txns = 0;
|
||||||
|
m_response_list = new std::list<xtlm::aximm_payload*>;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down Sizing input transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
do {
|
||||||
|
if (new_beat_l > 256)
|
||||||
|
cur_beat_l = 256;
|
||||||
|
else
|
||||||
|
cur_beat_l = new_beat_l;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_wr_trans);
|
||||||
|
t_trans->set_address(s_addr + num_byte_counter);
|
||||||
|
t_trans->set_data_ptr(data + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH);
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb + num_byte_counter,
|
||||||
|
cur_beat_l * MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_length(cur_beat_l);
|
||||||
|
num_byte_counter += cur_beat_l * MI_DATA_WIDTH;
|
||||||
|
m_interface_wr_payload_queue.push(t_trans);
|
||||||
|
m_response_list->push_back(t_trans);
|
||||||
|
t_total_txns++;
|
||||||
|
|
||||||
|
std::string payload_log;
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg = "Down sized output transaction : " + payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::002",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
} while (num_byte_counter < total_num_bytes);
|
||||||
|
|
||||||
|
m_response_mapper_downsize[m_wr_trans] = m_response_list;
|
||||||
|
event_downsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::m_downsize_interface_txn_sender() {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
if (wr_initiator_util->is_slave_ready()
|
||||||
|
&& (m_interface_wr_payload_queue.size() != 0)) {
|
||||||
|
m_log_msg = "Sending Write transaction " +
|
||||||
|
std::to_string(m_interface_wr_payload_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_initiator_util->send_transaction(
|
||||||
|
*m_interface_wr_payload_queue.front(), zero_delay);
|
||||||
|
m_interface_wr_payload_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
//For Read transaction
|
||||||
|
zero_delay = SC_ZERO_TIME;
|
||||||
|
if (rd_initiator_util->is_slave_ready()
|
||||||
|
&& (m_interface_rd_payload_queue.size() != 0)) {
|
||||||
|
m_log_msg = "Sending Read transaction " +
|
||||||
|
std::to_string(m_interface_rd_payload_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_initiator_util->send_transaction(
|
||||||
|
*m_interface_rd_payload_queue.front(), zero_delay);
|
||||||
|
m_interface_rd_payload_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::m_downsize_interface_response_sender() {
|
||||||
|
if (ratio <= 1)
|
||||||
|
return;
|
||||||
|
if (wr_initiator_util->is_resp_available()
|
||||||
|
&& (m_response_mapper_downsize.size() != 0)
|
||||||
|
&& (wr_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
|
||||||
|
m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::list<xtlm::aximm_payload*>::iterator itrlist;
|
||||||
|
std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
|
||||||
|
for (itr = m_response_mapper_downsize.begin();
|
||||||
|
itr != m_response_mapper_downsize.end(); itr++) {
|
||||||
|
itrlist = (std::find(itr->second->begin(), itr->second->end(),
|
||||||
|
response_payld));
|
||||||
|
if (itrlist != itr->second->end()) {
|
||||||
|
itr->second->remove(response_payld);
|
||||||
|
if (itr->second->size() == 0) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
itr->first->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Write : " +
|
||||||
|
std::to_string(itr->first->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_target_util->send_resp(*(itr->first), zero_delay);
|
||||||
|
delete (itr->second);
|
||||||
|
m_response_mapper_downsize.erase(itr);
|
||||||
|
event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
response_payld->release();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rd_initiator_util->is_data_available()
|
||||||
|
&& (m_response_mapper_downsize.size() != 0)
|
||||||
|
&& (rd_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
|
||||||
|
m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::list<xtlm::aximm_payload*>::iterator itrlist;
|
||||||
|
std::map<xtlm::aximm_payload*, std::list<xtlm::aximm_payload*>*>::iterator itr;
|
||||||
|
for (itr = m_response_mapper_downsize.begin();
|
||||||
|
itr != m_response_mapper_downsize.end(); itr++) {
|
||||||
|
itrlist = (std::find(itr->second->begin(), itr->second->end(),
|
||||||
|
response_payld));
|
||||||
|
if (itrlist != itr->second->end()) {
|
||||||
|
itr->second->remove(response_payld);
|
||||||
|
if (itr->second->size() == 0) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
itr->first->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Read : " +
|
||||||
|
std::to_string(itr->first->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::003",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_target_util->send_data(*(itr->first), zero_delay);
|
||||||
|
delete (itr->second);
|
||||||
|
event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
m_response_mapper_downsize.erase(itr);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
//Release the transaction to memory manager
|
||||||
|
response_payld->release();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::wr_upsizing() {
|
||||||
|
auto si_addr = m_wr_trans->get_address();
|
||||||
|
auto si_burst_len = m_wr_trans->get_burst_length();
|
||||||
|
auto si_burst_size = m_wr_trans->get_burst_size();
|
||||||
|
auto strb = m_wr_trans->get_byte_enable_ptr();
|
||||||
|
auto data = m_wr_trans->get_data_ptr();
|
||||||
|
auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
|
||||||
|
auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
|
||||||
|
+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
|
||||||
|
* MI_DATA_WIDTH;
|
||||||
|
auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_wr_trans);
|
||||||
|
t_trans->set_address(si_addr);
|
||||||
|
t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH );
|
||||||
|
t_trans->set_burst_length(mi_len);
|
||||||
|
m_upsize_wr_payld_queue.push(t_trans);
|
||||||
|
m_response_mapper_upsize[t_trans] = m_wr_trans;
|
||||||
|
|
||||||
|
m_log_msg = "Upsizing input Txn ";
|
||||||
|
std::string payload_log;
|
||||||
|
m_wr_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_log_msg = "Upsized output Txn ";
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
event_upsize_trig_txn_sender.notify();
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::rd_upsizing() {
|
||||||
|
auto si_addr = m_rd_trans->get_address();
|
||||||
|
auto si_burst_len = m_rd_trans->get_burst_length();
|
||||||
|
auto si_burst_size = m_rd_trans->get_burst_size();
|
||||||
|
auto strb = m_rd_trans->get_byte_enable_ptr();
|
||||||
|
auto data = m_rd_trans->get_data_ptr();
|
||||||
|
auto aligned_start = (si_addr / MI_DATA_WIDTH) * MI_DATA_WIDTH;
|
||||||
|
auto aligned_end = ((((si_addr / SI_DATA_WIDTH) * SI_DATA_WIDTH)
|
||||||
|
+ (si_burst_len - 1) * si_burst_size) / MI_DATA_WIDTH)
|
||||||
|
* MI_DATA_WIDTH;
|
||||||
|
auto mi_len = (aligned_end - aligned_start) / MI_DATA_WIDTH + 1;
|
||||||
|
|
||||||
|
xtlm::aximm_payload* t_trans = mem_manager->get_payload();
|
||||||
|
t_trans->acquire();
|
||||||
|
t_trans->deep_copy_from(*m_rd_trans);
|
||||||
|
t_trans->set_address(si_addr);
|
||||||
|
t_trans->set_data_ptr(data, mi_len * MI_DATA_WIDTH );
|
||||||
|
if (strb != nullptr)
|
||||||
|
t_trans->set_byte_enable_ptr(strb, mi_len * MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_size(MI_DATA_WIDTH);
|
||||||
|
t_trans->set_burst_length(mi_len);
|
||||||
|
m_upsize_rd_payld_queue.push(t_trans);
|
||||||
|
m_response_mapper_upsize[t_trans] = m_rd_trans;
|
||||||
|
|
||||||
|
m_log_msg = "Upsizing input Txn ";
|
||||||
|
std::string payload_log;
|
||||||
|
m_rd_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
m_log_msg = "Upsized output Txn ";
|
||||||
|
t_trans->get_log(payload_log, PAYLOAD_LOG_LEVEL);
|
||||||
|
m_log_msg += payload_log;
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::004",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
event_upsize_trig_txn_sender.notify();
|
||||||
|
}
|
||||||
|
|
||||||
|
void axi_dwidth_converter::m_upsize_interface_txn_sender() {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
if (wr_initiator_util->is_slave_ready()
|
||||||
|
&& (m_upsize_wr_payld_queue.size() != 0)) {
|
||||||
|
|
||||||
|
m_log_msg = "Sending Write transaction " +
|
||||||
|
std::to_string(m_upsize_wr_payld_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_initiator_util->send_transaction(*m_upsize_wr_payld_queue.front(),
|
||||||
|
zero_delay);
|
||||||
|
m_upsize_wr_payld_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
//For Read transaction
|
||||||
|
zero_delay = SC_ZERO_TIME;
|
||||||
|
if (rd_initiator_util->is_slave_ready()
|
||||||
|
&& (m_upsize_rd_payld_queue.size() != 0)) {
|
||||||
|
|
||||||
|
m_log_msg = "Sending Read transaction " +
|
||||||
|
std::to_string(m_upsize_rd_payld_queue.front()->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::005",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_initiator_util->send_transaction(*m_upsize_rd_payld_queue.front(),
|
||||||
|
zero_delay);
|
||||||
|
m_upsize_rd_payld_queue.pop();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
void axi_dwidth_converter::m_upsize_interface_response_sender() {
|
||||||
|
if (ratio > 1)
|
||||||
|
return;
|
||||||
|
if (wr_initiator_util->is_resp_available()
|
||||||
|
&& (m_response_mapper_upsize.size() != 0)
|
||||||
|
&& (wr_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = wr_initiator_util->get_resp();
|
||||||
|
m_log_msg = "Sampled Response for Write : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
|
||||||
|
itr = (m_response_mapper_upsize.find(response_payld));
|
||||||
|
if (itr != m_response_mapper_upsize.end()) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
m_response_mapper_upsize[response_payld]->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Write : " +
|
||||||
|
std::to_string(m_response_mapper_upsize[response_payld]->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
wr_target_util->send_resp(*m_response_mapper_upsize[response_payld],
|
||||||
|
zero_delay);
|
||||||
|
response_payld->release();
|
||||||
|
m_response_mapper_upsize.erase(response_payld);
|
||||||
|
event_trig_wr_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rd_initiator_util->is_data_available()
|
||||||
|
&& (m_response_mapper_upsize.size() != 0)
|
||||||
|
&& (rd_target_util->is_master_ready())) {
|
||||||
|
xtlm::aximm_payload* response_payld = rd_initiator_util->get_data();
|
||||||
|
m_log_msg = "Sampled Response for Read : " + std::to_string(response_payld->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
std::map<xtlm::aximm_payload*, xtlm::aximm_payload*>::iterator itr;
|
||||||
|
itr = m_response_mapper_upsize.find(response_payld);
|
||||||
|
if (itr != m_response_mapper_upsize.end()) {
|
||||||
|
sc_core::sc_time zero_delay = SC_ZERO_TIME;
|
||||||
|
m_response_mapper_upsize[response_payld]->set_axi_response_status(
|
||||||
|
response_payld->get_axi_response_status());
|
||||||
|
m_log_msg = "Sending Response for Read : " +
|
||||||
|
std::to_string(m_response_mapper_upsize[response_payld]->get_address());
|
||||||
|
XSC_REPORT_INFO_VERB(m_logger, "DWIDTH::006",m_log_msg.c_str(), DEBUG);
|
||||||
|
|
||||||
|
rd_target_util->send_data(*m_response_mapper_upsize[response_payld],
|
||||||
|
zero_delay);
|
||||||
|
|
||||||
|
response_payld->release();
|
||||||
|
m_response_mapper_upsize.erase(response_payld);
|
||||||
|
event_trig_rd_handler.notify(sc_core::SC_ZERO_TIME);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
axi_dwidth_converter::~axi_dwidth_converter() {
|
||||||
|
delete mem_manager;
|
||||||
|
delete target_rd_socket;
|
||||||
|
delete target_wr_socket;
|
||||||
|
delete initiator_rd_socket;
|
||||||
|
delete initiator_wr_socket;
|
||||||
|
delete rd_target_util;
|
||||||
|
delete wr_target_util;
|
||||||
|
delete wr_initiator_util;
|
||||||
|
delete rd_initiator_util;
|
||||||
|
delete m_rd_trans;
|
||||||
|
delete m_wr_trans;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
||||||
|
// (c) Copyright 2013 - 2019 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#ifndef _AXI_DWIDTH_CONVERTER_H_
|
||||||
|
#define _AXI_DWIDTH_CONVERTER_H_
|
||||||
|
|
||||||
|
#include "xtlm.h"
|
||||||
|
#include "report_handler.h"
|
||||||
|
|
||||||
|
class axi_dwidth_converter: public sc_core::sc_module {
|
||||||
|
public:
|
||||||
|
SC_HAS_PROCESS(axi_dwidth_converter);
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||||
|
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||||
|
sc_core::sc_in<bool> s_axi_aclk;
|
||||||
|
sc_core::sc_in<bool> s_axi_aresetn;
|
||||||
|
sc_core::sc_in<bool> m_axi_aclk;
|
||||||
|
sc_core::sc_in<bool> m_axi_aresetn;
|
||||||
|
sc_core::sc_signal<bool> clk;
|
||||||
|
sc_core::sc_signal<bool> resetn;
|
||||||
|
axi_dwidth_converter(sc_core::sc_module_name p_name,
|
||||||
|
xsc::common_cpp::properties& m_properties);
|
||||||
|
xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
|
||||||
|
xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
|
||||||
|
xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
|
||||||
|
xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
|
||||||
|
xtlm::xtlm_aximm_mem_manager* mem_manager;
|
||||||
|
~axi_dwidth_converter();
|
||||||
|
unsigned int SI_DATA_WIDTH;
|
||||||
|
unsigned int MI_DATA_WIDTH;
|
||||||
|
unsigned int FIFO_MODE;
|
||||||
|
unsigned int ratio;
|
||||||
|
|
||||||
|
void wr_handler();
|
||||||
|
void rd_handler();
|
||||||
|
void wr_upsizing();
|
||||||
|
void wr_downsizing();
|
||||||
|
void rd_upsizing();
|
||||||
|
void rd_downsizing();
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Method to send transaction on master interface
|
||||||
|
*/
|
||||||
|
void m_downsize_interface_txn_sender();
|
||||||
|
void m_upsize_interface_txn_sender();
|
||||||
|
|
||||||
|
void m_downsize_interface_response_sender();
|
||||||
|
void m_upsize_interface_response_sender();
|
||||||
|
|
||||||
|
private:
|
||||||
|
xtlm::aximm_payload* m_rd_trans;
|
||||||
|
xtlm::aximm_payload* m_wr_trans;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
|
||||||
|
std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
|
||||||
|
sc_core::sc_event event_downsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||||
|
sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||||
|
sc_core::sc_event event_trig_rd_handler;
|
||||||
|
sc_core::sc_event event_trig_wr_handler;
|
||||||
|
std::list<xtlm::aximm_payload* > *m_response_list;
|
||||||
|
std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
|
||||||
|
std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
|
||||||
|
xsc::common_cpp::report_handler m_logger;
|
||||||
|
std::string m_log_msg;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _AXI_DWIDTH_CONVERTER_H_ */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,381 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_22_top,Vivado 2020.2" *)
|
||||||
|
(* CHECK_LICENSE_TYPE = "pl_eth_10g_auto_us_0,axi_dwidth_converter_v2_1_22_top,{}" *)
|
||||||
|
(* CORE_GENERATION_INFO = "pl_eth_10g_auto_us_0,axi_dwidth_converter_v2_1_22_top,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=22,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=128,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BE\
|
||||||
|
ATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_us_0 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awlock,
|
||||||
|
s_axi_awcache,
|
||||||
|
s_axi_awprot,
|
||||||
|
s_axi_awregion,
|
||||||
|
s_axi_awqos,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_awaddr,
|
||||||
|
m_axi_awlen,
|
||||||
|
m_axi_awsize,
|
||||||
|
m_axi_awburst,
|
||||||
|
m_axi_awlock,
|
||||||
|
m_axi_awcache,
|
||||||
|
m_axi_awprot,
|
||||||
|
m_axi_awregion,
|
||||||
|
m_axi_awqos,
|
||||||
|
m_axi_awvalid,
|
||||||
|
m_axi_awready,
|
||||||
|
m_axi_wdata,
|
||||||
|
m_axi_wstrb,
|
||||||
|
m_axi_wlast,
|
||||||
|
m_axi_wvalid,
|
||||||
|
m_axi_wready,
|
||||||
|
m_axi_bresp,
|
||||||
|
m_axi_bvalid,
|
||||||
|
m_axi_bready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 124998749, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||||
|
input wire s_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||||
|
output wire s_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||||
|
input wire [31 : 0] s_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||||
|
input wire [3 : 0] s_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||||
|
input wire s_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||||
|
input wire s_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||||
|
output wire s_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||||
|
output wire s_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||||
|
input wire s_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [31 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
|
||||||
|
UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_awaddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_awlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_awsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_awburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_awlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_awcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_awprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_awregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_awqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||||
|
output wire m_axi_awvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||||
|
input wire m_axi_awready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||||
|
output wire [127 : 0] m_axi_wdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||||
|
output wire [15 : 0] m_axi_wstrb;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||||
|
output wire m_axi_wlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||||
|
output wire m_axi_wvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||||
|
input wire m_axi_wready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_bresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||||
|
input wire m_axi_bvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||||
|
output wire m_axi_bready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [127 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, N\
|
||||||
|
UM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_dwidth_converter_v2_1_22_top #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_S_AXI_ID_WIDTH(1),
|
||||||
|
.C_SUPPORTS_ID(0),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_S_AXI_DATA_WIDTH(32),
|
||||||
|
.C_M_AXI_DATA_WIDTH(128),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(1),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_FIFO_MODE(0),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(0),
|
||||||
|
.C_MAX_SPLIT_BEATS(16),
|
||||||
|
.C_PACKING_LEVEL(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(s_axi_awaddr),
|
||||||
|
.s_axi_awlen(s_axi_awlen),
|
||||||
|
.s_axi_awsize(s_axi_awsize),
|
||||||
|
.s_axi_awburst(s_axi_awburst),
|
||||||
|
.s_axi_awlock(s_axi_awlock),
|
||||||
|
.s_axi_awcache(s_axi_awcache),
|
||||||
|
.s_axi_awprot(s_axi_awprot),
|
||||||
|
.s_axi_awregion(s_axi_awregion),
|
||||||
|
.s_axi_awqos(s_axi_awqos),
|
||||||
|
.s_axi_awvalid(s_axi_awvalid),
|
||||||
|
.s_axi_awready(s_axi_awready),
|
||||||
|
.s_axi_wdata(s_axi_wdata),
|
||||||
|
.s_axi_wstrb(s_axi_wstrb),
|
||||||
|
.s_axi_wlast(s_axi_wlast),
|
||||||
|
.s_axi_wvalid(s_axi_wvalid),
|
||||||
|
.s_axi_wready(s_axi_wready),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(s_axi_bresp),
|
||||||
|
.s_axi_bvalid(s_axi_bvalid),
|
||||||
|
.s_axi_bready(s_axi_bready),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(1'H0),
|
||||||
|
.m_axi_aresetn(1'H0),
|
||||||
|
.m_axi_awaddr(m_axi_awaddr),
|
||||||
|
.m_axi_awlen(m_axi_awlen),
|
||||||
|
.m_axi_awsize(m_axi_awsize),
|
||||||
|
.m_axi_awburst(m_axi_awburst),
|
||||||
|
.m_axi_awlock(m_axi_awlock),
|
||||||
|
.m_axi_awcache(m_axi_awcache),
|
||||||
|
.m_axi_awprot(m_axi_awprot),
|
||||||
|
.m_axi_awregion(m_axi_awregion),
|
||||||
|
.m_axi_awqos(m_axi_awqos),
|
||||||
|
.m_axi_awvalid(m_axi_awvalid),
|
||||||
|
.m_axi_awready(m_axi_awready),
|
||||||
|
.m_axi_wdata(m_axi_wdata),
|
||||||
|
.m_axi_wstrb(m_axi_wstrb),
|
||||||
|
.m_axi_wlast(m_axi_wlast),
|
||||||
|
.m_axi_wvalid(m_axi_wvalid),
|
||||||
|
.m_axi_wready(m_axi_wready),
|
||||||
|
.m_axi_bresp(m_axi_bresp),
|
||||||
|
.m_axi_bvalid(m_axi_bvalid),
|
||||||
|
.m_axi_bready(m_axi_bready),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,7 @@
|
||||||
|
###############################################################################################################
|
||||||
|
# Core-Level Timing Constraints for axi_dwidth_converter Component "pl_eth_10g_auto_us_1"
|
||||||
|
###############################################################################################################
|
||||||
|
#
|
||||||
|
# This component is not configured to perform asynchronous clock-domain-crossing.
|
||||||
|
# No timing core-level constraints are needed.
|
||||||
|
# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
################################################################################
|
||||||
|
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
create_clock -period 100.0 -name aclk [get_ports *_axi_aclk]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,450 @@
|
||||||
|
#ifndef IP_PL_ETH_10G_AUTO_US_1_H_
|
||||||
|
#define IP_PL_ETH_10G_AUTO_US_1_H_
|
||||||
|
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef XTLM
|
||||||
|
#include "xtlm.h"
|
||||||
|
#endif
|
||||||
|
#ifndef SYSTEMC_INCLUDED
|
||||||
|
#include <systemc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(_MSC_VER)
|
||||||
|
#define DllExport __declspec(dllexport)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define DllExport __attribute__ ((visibility("default")))
|
||||||
|
#else
|
||||||
|
#define DllExport
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_us_1_sc.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XILINX_SIMULATOR
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XILINX_SIMULATOR
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef XM_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // XM_SYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef RIVIERA
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // RIVIERA
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef VCSSYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // VCSSYSTEMC
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef MTI_SYSTEMC
|
||||||
|
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||||
|
|
||||||
|
#include "utils/xtlm_aximm_target_stub.h"
|
||||||
|
|
||||||
|
class DllExport pl_eth_10g_auto_us_1 : public pl_eth_10g_auto_us_1_sc
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_1(const sc_core::sc_module_name& nm);
|
||||||
|
virtual ~pl_eth_10g_auto_us_1();
|
||||||
|
|
||||||
|
// module pin-to-pin RTL interface
|
||||||
|
|
||||||
|
sc_core::sc_in< bool > s_axi_aclk;
|
||||||
|
sc_core::sc_in< bool > s_axi_aresetn;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||||
|
sc_core::sc_in< bool > s_axi_arvalid;
|
||||||
|
sc_core::sc_out< bool > s_axi_arready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||||
|
sc_core::sc_out< bool > s_axi_rlast;
|
||||||
|
sc_core::sc_out< bool > s_axi_rvalid;
|
||||||
|
sc_core::sc_in< bool > s_axi_rready;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
|
||||||
|
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||||
|
sc_core::sc_out< bool > m_axi_arvalid;
|
||||||
|
sc_core::sc_in< bool > m_axi_arready;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
|
||||||
|
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||||
|
sc_core::sc_in< bool > m_axi_rlast;
|
||||||
|
sc_core::sc_in< bool > m_axi_rvalid;
|
||||||
|
sc_core::sc_out< bool > m_axi_rready;
|
||||||
|
|
||||||
|
// Dummy Signals for IP Ports
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
virtual void before_end_of_elaboration();
|
||||||
|
|
||||||
|
private:
|
||||||
|
|
||||||
|
xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||||
|
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||||
|
xtlm::xaximm_xtlm2pin_t<128,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||||
|
xsc::common::scalar2vectorN_converter<1>* mp_m_axi_arlock_converter;
|
||||||
|
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||||
|
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||||
|
|
||||||
|
// Transactor stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||||
|
|
||||||
|
// Socket stubs
|
||||||
|
xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
|
||||||
|
xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // MTI_SYSTEMC
|
||||||
|
#endif // IP_PL_ETH_10G_AUTO_US_1_H_
|
||||||
|
|
@ -0,0 +1,265 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||||
|
// IP Revision: 22
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module pl_eth_10g_auto_us_1 (
|
||||||
|
s_axi_aclk,
|
||||||
|
s_axi_aresetn,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arlock,
|
||||||
|
s_axi_arcache,
|
||||||
|
s_axi_arprot,
|
||||||
|
s_axi_arregion,
|
||||||
|
s_axi_arqos,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
m_axi_araddr,
|
||||||
|
m_axi_arlen,
|
||||||
|
m_axi_arsize,
|
||||||
|
m_axi_arburst,
|
||||||
|
m_axi_arlock,
|
||||||
|
m_axi_arcache,
|
||||||
|
m_axi_arprot,
|
||||||
|
m_axi_arregion,
|
||||||
|
m_axi_arqos,
|
||||||
|
m_axi_arvalid,
|
||||||
|
m_axi_arready,
|
||||||
|
m_axi_rdata,
|
||||||
|
m_axi_rresp,
|
||||||
|
m_axi_rlast,
|
||||||
|
m_axi_rvalid,
|
||||||
|
m_axi_rready
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 156250000, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||||
|
input wire s_axi_aclk;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||||
|
input wire s_axi_aresetn;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||||
|
input wire [31 : 0] s_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||||
|
input wire [7 : 0] s_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||||
|
input wire [2 : 0] s_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||||
|
input wire [1 : 0] s_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||||
|
input wire [0 : 0] s_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||||
|
input wire [3 : 0] s_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||||
|
input wire [2 : 0] s_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
|
||||||
|
input wire [3 : 0] s_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||||
|
input wire [3 : 0] s_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||||
|
input wire s_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||||
|
output wire s_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||||
|
output wire [63 : 0] s_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||||
|
output wire [1 : 0] s_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||||
|
output wire s_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||||
|
output wire s_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NUM\
|
||||||
|
_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||||
|
input wire s_axi_rready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||||
|
output wire [31 : 0] m_axi_araddr;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||||
|
output wire [7 : 0] m_axi_arlen;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||||
|
output wire [2 : 0] m_axi_arsize;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||||
|
output wire [1 : 0] m_axi_arburst;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||||
|
output wire [0 : 0] m_axi_arlock;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||||
|
output wire [3 : 0] m_axi_arcache;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||||
|
output wire [2 : 0] m_axi_arprot;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
|
||||||
|
output wire [3 : 0] m_axi_arregion;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||||
|
output wire [3 : 0] m_axi_arqos;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||||
|
output wire m_axi_arvalid;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||||
|
input wire m_axi_arready;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||||
|
input wire [127 : 0] m_axi_rdata;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||||
|
input wire [1 : 0] m_axi_rresp;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||||
|
input wire m_axi_rlast;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||||
|
input wire m_axi_rvalid;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 32, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_tx_clk_out_0, NUM_READ_THREADS 1, NU\
|
||||||
|
M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||||
|
output wire m_axi_rready;
|
||||||
|
|
||||||
|
axi_dwidth_converter_v2_1_22_top #(
|
||||||
|
.C_FAMILY("zynquplus"),
|
||||||
|
.C_AXI_PROTOCOL(0),
|
||||||
|
.C_S_AXI_ID_WIDTH(1),
|
||||||
|
.C_SUPPORTS_ID(0),
|
||||||
|
.C_AXI_ADDR_WIDTH(32),
|
||||||
|
.C_S_AXI_DATA_WIDTH(64),
|
||||||
|
.C_M_AXI_DATA_WIDTH(128),
|
||||||
|
.C_AXI_SUPPORTS_WRITE(0),
|
||||||
|
.C_AXI_SUPPORTS_READ(1),
|
||||||
|
.C_FIFO_MODE(0),
|
||||||
|
.C_S_AXI_ACLK_RATIO(1),
|
||||||
|
.C_M_AXI_ACLK_RATIO(2),
|
||||||
|
.C_AXI_IS_ACLK_ASYNC(0),
|
||||||
|
.C_MAX_SPLIT_BEATS(16),
|
||||||
|
.C_PACKING_LEVEL(1),
|
||||||
|
.C_SYNCHRONIZER_STAGE(3)
|
||||||
|
) inst (
|
||||||
|
.s_axi_aclk(s_axi_aclk),
|
||||||
|
.s_axi_aresetn(s_axi_aresetn),
|
||||||
|
.s_axi_awid(1'H0),
|
||||||
|
.s_axi_awaddr(32'H00000000),
|
||||||
|
.s_axi_awlen(8'H00),
|
||||||
|
.s_axi_awsize(3'H0),
|
||||||
|
.s_axi_awburst(2'H1),
|
||||||
|
.s_axi_awlock(1'H0),
|
||||||
|
.s_axi_awcache(4'H0),
|
||||||
|
.s_axi_awprot(3'H0),
|
||||||
|
.s_axi_awregion(4'H0),
|
||||||
|
.s_axi_awqos(4'H0),
|
||||||
|
.s_axi_awvalid(1'H0),
|
||||||
|
.s_axi_awready(),
|
||||||
|
.s_axi_wdata(64'H0000000000000000),
|
||||||
|
.s_axi_wstrb(8'HFF),
|
||||||
|
.s_axi_wlast(1'H1),
|
||||||
|
.s_axi_wvalid(1'H0),
|
||||||
|
.s_axi_wready(),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(),
|
||||||
|
.s_axi_bvalid(),
|
||||||
|
.s_axi_bready(1'H0),
|
||||||
|
.s_axi_arid(1'H0),
|
||||||
|
.s_axi_araddr(s_axi_araddr),
|
||||||
|
.s_axi_arlen(s_axi_arlen),
|
||||||
|
.s_axi_arsize(s_axi_arsize),
|
||||||
|
.s_axi_arburst(s_axi_arburst),
|
||||||
|
.s_axi_arlock(s_axi_arlock),
|
||||||
|
.s_axi_arcache(s_axi_arcache),
|
||||||
|
.s_axi_arprot(s_axi_arprot),
|
||||||
|
.s_axi_arregion(s_axi_arregion),
|
||||||
|
.s_axi_arqos(s_axi_arqos),
|
||||||
|
.s_axi_arvalid(s_axi_arvalid),
|
||||||
|
.s_axi_arready(s_axi_arready),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(s_axi_rdata),
|
||||||
|
.s_axi_rresp(s_axi_rresp),
|
||||||
|
.s_axi_rlast(s_axi_rlast),
|
||||||
|
.s_axi_rvalid(s_axi_rvalid),
|
||||||
|
.s_axi_rready(s_axi_rready),
|
||||||
|
.m_axi_aclk(1'H0),
|
||||||
|
.m_axi_aresetn(1'H0),
|
||||||
|
.m_axi_awaddr(),
|
||||||
|
.m_axi_awlen(),
|
||||||
|
.m_axi_awsize(),
|
||||||
|
.m_axi_awburst(),
|
||||||
|
.m_axi_awlock(),
|
||||||
|
.m_axi_awcache(),
|
||||||
|
.m_axi_awprot(),
|
||||||
|
.m_axi_awregion(),
|
||||||
|
.m_axi_awqos(),
|
||||||
|
.m_axi_awvalid(),
|
||||||
|
.m_axi_awready(1'H0),
|
||||||
|
.m_axi_wdata(),
|
||||||
|
.m_axi_wstrb(),
|
||||||
|
.m_axi_wlast(),
|
||||||
|
.m_axi_wvalid(),
|
||||||
|
.m_axi_wready(1'H0),
|
||||||
|
.m_axi_bresp(2'H0),
|
||||||
|
.m_axi_bvalid(1'H0),
|
||||||
|
.m_axi_bready(),
|
||||||
|
.m_axi_araddr(m_axi_araddr),
|
||||||
|
.m_axi_arlen(m_axi_arlen),
|
||||||
|
.m_axi_arsize(m_axi_arsize),
|
||||||
|
.m_axi_arburst(m_axi_arburst),
|
||||||
|
.m_axi_arlock(m_axi_arlock),
|
||||||
|
.m_axi_arcache(m_axi_arcache),
|
||||||
|
.m_axi_arprot(m_axi_arprot),
|
||||||
|
.m_axi_arregion(m_axi_arregion),
|
||||||
|
.m_axi_arqos(m_axi_arqos),
|
||||||
|
.m_axi_arvalid(m_axi_arvalid),
|
||||||
|
.m_axi_arready(m_axi_arready),
|
||||||
|
.m_axi_rdata(m_axi_rdata),
|
||||||
|
.m_axi_rresp(m_axi_rresp),
|
||||||
|
.m_axi_rlast(m_axi_rlast),
|
||||||
|
.m_axi_rvalid(m_axi_rvalid),
|
||||||
|
.m_axi_rready(m_axi_rready)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
#include "pl_eth_10g_auto_us_1_sc.h"
|
||||||
|
|
||||||
|
#include "axi_dwidth_converter.h"
|
||||||
|
|
||||||
|
#include <map>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_1_sc::pl_eth_10g_auto_us_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||||
|
{
|
||||||
|
// configure connectivity manager
|
||||||
|
xsc::utils::xsc_sim_manager::addInstance("pl_eth_10g_auto_us_1", this);
|
||||||
|
|
||||||
|
// initialize module
|
||||||
|
xsc::common_cpp::properties model_param_props;
|
||||||
|
model_param_props.addLong("C_AXI_PROTOCOL", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
|
||||||
|
model_param_props.addLong("C_SUPPORTS_ID", "0");
|
||||||
|
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
|
||||||
|
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "64");
|
||||||
|
model_param_props.addLong("C_M_AXI_DATA_WIDTH", "128");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "0");
|
||||||
|
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||||
|
model_param_props.addLong("C_FIFO_MODE", "0");
|
||||||
|
model_param_props.addLong("C_S_AXI_ACLK_RATIO", "1");
|
||||||
|
model_param_props.addLong("C_M_AXI_ACLK_RATIO", "2");
|
||||||
|
model_param_props.addLong("C_AXI_IS_ACLK_ASYNC", "0");
|
||||||
|
model_param_props.addLong("C_MAX_SPLIT_BEATS", "16");
|
||||||
|
model_param_props.addLong("C_PACKING_LEVEL", "1");
|
||||||
|
model_param_props.addLong("C_SYNCHRONIZER_STAGE", "3");
|
||||||
|
model_param_props.addString("C_FAMILY", "zynquplus");
|
||||||
|
|
||||||
|
mp_impl = new axi_dwidth_converter("inst", model_param_props);
|
||||||
|
|
||||||
|
// initialize AXI sockets
|
||||||
|
target_rd_socket = mp_impl->target_rd_socket;
|
||||||
|
target_wr_socket = mp_impl->target_wr_socket;
|
||||||
|
initiator_rd_socket = mp_impl->initiator_rd_socket;
|
||||||
|
initiator_wr_socket = mp_impl->initiator_wr_socket;
|
||||||
|
}
|
||||||
|
|
||||||
|
pl_eth_10g_auto_us_1_sc::~pl_eth_10g_auto_us_1_sc()
|
||||||
|
{
|
||||||
|
xsc::utils::xsc_sim_manager::clean();
|
||||||
|
|
||||||
|
delete mp_impl;
|
||||||
|
}
|
||||||
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue