38634 lines
1.6 MiB
38634 lines
1.6 MiB
/******************************************************************************
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*
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* Copyright (C) 2010-2020 <Xilinx Inc.>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>
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*
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file psu_init_gpl.h
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*
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* This file is automatically generated
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*
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*****************************************************************************/
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#undef CRL_APB_RPLL_CFG_OFFSET
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#define CRL_APB_RPLL_CFG_OFFSET 0XFF5E0034
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#undef CRL_APB_RPLL_CTRL_OFFSET
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#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
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#undef CRL_APB_RPLL_CTRL_OFFSET
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#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
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#undef CRL_APB_RPLL_CTRL_OFFSET
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#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
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#undef CRL_APB_RPLL_CTRL_OFFSET
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#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
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#undef CRL_APB_RPLL_CTRL_OFFSET
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#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
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#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET
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#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048
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#undef CRL_APB_AMS_REF_CTRL_OFFSET
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#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108
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#undef CRL_APB_IOPLL_CFG_OFFSET
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#define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024
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#undef CRL_APB_IOPLL_CTRL_OFFSET
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#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
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#undef CRL_APB_IOPLL_CTRL_OFFSET
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#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
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#undef CRL_APB_IOPLL_CTRL_OFFSET
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#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
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#undef CRL_APB_IOPLL_CTRL_OFFSET
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#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
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#undef CRL_APB_IOPLL_CTRL_OFFSET
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#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
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#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET
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#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044
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#undef CRF_APB_APLL_CFG_OFFSET
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#define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024
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#undef CRF_APB_APLL_CTRL_OFFSET
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#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
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#undef CRF_APB_APLL_CTRL_OFFSET
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#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
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#undef CRF_APB_APLL_CTRL_OFFSET
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#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
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#undef CRF_APB_APLL_CTRL_OFFSET
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#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
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#undef CRF_APB_APLL_CTRL_OFFSET
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#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
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#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET
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#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048
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#undef CRF_APB_DPLL_CFG_OFFSET
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#define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030
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#undef CRF_APB_DPLL_CTRL_OFFSET
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#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
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#undef CRF_APB_DPLL_CTRL_OFFSET
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#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
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#undef CRF_APB_DPLL_CTRL_OFFSET
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#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
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#undef CRF_APB_DPLL_CTRL_OFFSET
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#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
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#undef CRF_APB_DPLL_CTRL_OFFSET
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#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
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#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET
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#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C
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#undef CRF_APB_VPLL_CFG_OFFSET
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#define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C
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#undef CRF_APB_VPLL_CTRL_OFFSET
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#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
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#undef CRF_APB_VPLL_CTRL_OFFSET
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#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
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#undef CRF_APB_VPLL_CTRL_OFFSET
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#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
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#undef CRF_APB_VPLL_CTRL_OFFSET
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#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
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#undef CRF_APB_VPLL_CTRL_OFFSET
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#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
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#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET
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#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050
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/*
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* PLL loop filter resistor control
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*/
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#undef CRL_APB_RPLL_CFG_RES_DEFVAL
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#undef CRL_APB_RPLL_CFG_RES_SHIFT
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#undef CRL_APB_RPLL_CFG_RES_MASK
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#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000
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#define CRL_APB_RPLL_CFG_RES_SHIFT 0
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#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU
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/*
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* PLL charge pump control
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*/
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#undef CRL_APB_RPLL_CFG_CP_DEFVAL
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#undef CRL_APB_RPLL_CFG_CP_SHIFT
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#undef CRL_APB_RPLL_CFG_CP_MASK
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#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000
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#define CRL_APB_RPLL_CFG_CP_SHIFT 5
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#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U
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/*
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* PLL loop filter high frequency capacitor control
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*/
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#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL
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#undef CRL_APB_RPLL_CFG_LFHF_SHIFT
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#undef CRL_APB_RPLL_CFG_LFHF_MASK
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#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000
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#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10
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#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U
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/*
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* Lock circuit counter setting
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*/
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#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL
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#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
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#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK
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#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
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#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13
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#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U
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/*
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* Lock circuit configuration settings for lock windowsize
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*/
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#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL
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#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
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#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK
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#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
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#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25
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#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U
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/*
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* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
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* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
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* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
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*/
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#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL
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#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
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#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK
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#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
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#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20
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#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U
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/*
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* The integer portion of the feedback divider to the PLL
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*/
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#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL
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#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT
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#undef CRL_APB_RPLL_CTRL_FBDIV_MASK
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#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09
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#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8
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#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U
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/*
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* This turns on the divide by 2 that is inside of the PLL. This does not c
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* hange the VCO frequency, just the output frequency
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*/
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#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL
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#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT
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#undef CRL_APB_RPLL_CTRL_DIV2_MASK
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#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09
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#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16
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#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U
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/*
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* Bypasses the PLL clock. The usable clock will be determined from the POS
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* T_SRC field. (This signal may only be toggled after 4 cycles of the old
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* clock and 4 cycles of the new clock. This is not usually an issue, but d
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* esigners must be aware.)
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*/
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#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
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#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
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#undef CRL_APB_RPLL_CTRL_BYPASS_MASK
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#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
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#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
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#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
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/*
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* Asserts Reset to the PLL. When asserting reset, the PLL must already be
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* in BYPASS.
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*/
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#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
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#undef CRL_APB_RPLL_CTRL_RESET_SHIFT
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#undef CRL_APB_RPLL_CTRL_RESET_MASK
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#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
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#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
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#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
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/*
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* Asserts Reset to the PLL. When asserting reset, the PLL must already be
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* in BYPASS.
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*/
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#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
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#undef CRL_APB_RPLL_CTRL_RESET_SHIFT
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#undef CRL_APB_RPLL_CTRL_RESET_MASK
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#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
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#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
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#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
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/*
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* RPLL is locked
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*/
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#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL
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#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT
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#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK
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#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018
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#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1
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#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U
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#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
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/*
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* Bypasses the PLL clock. The usable clock will be determined from the POS
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* T_SRC field. (This signal may only be toggled after 4 cycles of the old
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* clock and 4 cycles of the new clock. This is not usually an issue, but d
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* esigners must be aware.)
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*/
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#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
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#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
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#undef CRL_APB_RPLL_CTRL_BYPASS_MASK
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#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
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#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
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#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
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/*
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* Divisor value for this clock.
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*/
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#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
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#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
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#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK
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#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
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#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
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#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
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/*
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* 6 bit divider
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*/
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#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
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#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
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#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
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#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
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#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16
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#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
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/*
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* 6 bit divider
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*/
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#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
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#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
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#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
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#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
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#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8
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#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
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/*
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* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
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* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
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* usually an issue, but designers must be aware.)
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*/
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#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
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#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
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#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
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#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800
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#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0
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#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U
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/*
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* Clock active signal. Switch to 0 to disable the clock
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*/
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#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
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#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
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#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
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#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800
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#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24
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#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U
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/*
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* PLL loop filter resistor control
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*/
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#undef CRL_APB_IOPLL_CFG_RES_DEFVAL
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#undef CRL_APB_IOPLL_CFG_RES_SHIFT
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#undef CRL_APB_IOPLL_CFG_RES_MASK
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#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000
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#define CRL_APB_IOPLL_CFG_RES_SHIFT 0
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#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU
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/*
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* PLL charge pump control
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*/
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#undef CRL_APB_IOPLL_CFG_CP_DEFVAL
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#undef CRL_APB_IOPLL_CFG_CP_SHIFT
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#undef CRL_APB_IOPLL_CFG_CP_MASK
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#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000
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#define CRL_APB_IOPLL_CFG_CP_SHIFT 5
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#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U
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/*
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* PLL loop filter high frequency capacitor control
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*/
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#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL
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#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT
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#undef CRL_APB_IOPLL_CFG_LFHF_MASK
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#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000
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#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10
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#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U
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/*
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* Lock circuit counter setting
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*/
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#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL
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#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
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#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK
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#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
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#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13
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#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U
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/*
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* Lock circuit configuration settings for lock windowsize
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*/
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#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL
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#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
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#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK
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#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
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#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25
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#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U
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/*
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* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
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* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
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* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
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*/
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#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL
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#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
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#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK
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#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
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#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20
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#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U
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/*
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* The integer portion of the feedback divider to the PLL
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*/
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#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL
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#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
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#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK
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#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09
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#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8
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#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U
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/*
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* This turns on the divide by 2 that is inside of the PLL. This does not c
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* hange the VCO frequency, just the output frequency
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*/
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#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL
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#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT
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#undef CRL_APB_IOPLL_CTRL_DIV2_MASK
|
|
#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09
|
|
#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16
|
|
#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
|
|
#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
|
|
#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
|
|
#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
|
|
#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
|
|
#undef CRL_APB_IOPLL_CTRL_RESET_MASK
|
|
#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
|
|
#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
|
|
#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
|
|
#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
|
|
#undef CRL_APB_IOPLL_CTRL_RESET_MASK
|
|
#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
|
|
#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
|
|
#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* IOPLL is locked
|
|
*/
|
|
#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL
|
|
#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT
|
|
#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK
|
|
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018
|
|
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0
|
|
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U
|
|
#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
|
|
#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
|
|
#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
|
|
#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Divisor value for this clock.
|
|
*/
|
|
#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
|
|
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* PLL loop filter resistor control
|
|
*/
|
|
#undef CRF_APB_APLL_CFG_RES_DEFVAL
|
|
#undef CRF_APB_APLL_CFG_RES_SHIFT
|
|
#undef CRF_APB_APLL_CFG_RES_MASK
|
|
#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000
|
|
#define CRF_APB_APLL_CFG_RES_SHIFT 0
|
|
#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU
|
|
|
|
/*
|
|
* PLL charge pump control
|
|
*/
|
|
#undef CRF_APB_APLL_CFG_CP_DEFVAL
|
|
#undef CRF_APB_APLL_CFG_CP_SHIFT
|
|
#undef CRF_APB_APLL_CFG_CP_MASK
|
|
#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000
|
|
#define CRF_APB_APLL_CFG_CP_SHIFT 5
|
|
#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U
|
|
|
|
/*
|
|
* PLL loop filter high frequency capacitor control
|
|
*/
|
|
#undef CRF_APB_APLL_CFG_LFHF_DEFVAL
|
|
#undef CRF_APB_APLL_CFG_LFHF_SHIFT
|
|
#undef CRF_APB_APLL_CFG_LFHF_MASK
|
|
#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000
|
|
#define CRF_APB_APLL_CFG_LFHF_SHIFT 10
|
|
#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U
|
|
|
|
/*
|
|
* Lock circuit counter setting
|
|
*/
|
|
#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL
|
|
#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
|
|
#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK
|
|
#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000
|
|
#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13
|
|
#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U
|
|
|
|
/*
|
|
* Lock circuit configuration settings for lock windowsize
|
|
*/
|
|
#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL
|
|
#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
|
|
#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK
|
|
#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000
|
|
#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25
|
|
#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U
|
|
|
|
/*
|
|
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
|
|
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
|
|
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
|
|
*/
|
|
#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL
|
|
#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
|
|
#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK
|
|
#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
|
|
#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20
|
|
#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U
|
|
|
|
/*
|
|
* The integer portion of the feedback divider to the PLL
|
|
*/
|
|
#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL
|
|
#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT
|
|
#undef CRF_APB_APLL_CTRL_FBDIV_MASK
|
|
#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09
|
|
#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8
|
|
#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U
|
|
|
|
/*
|
|
* This turns on the divide by 2 that is inside of the PLL. This does not c
|
|
* hange the VCO frequency, just the output frequency
|
|
*/
|
|
#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL
|
|
#undef CRF_APB_APLL_CTRL_DIV2_SHIFT
|
|
#undef CRF_APB_APLL_CTRL_DIV2_MASK
|
|
#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09
|
|
#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16
|
|
#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
|
|
#undef CRF_APB_APLL_CTRL_BYPASS_MASK
|
|
#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
|
|
#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRF_APB_APLL_CTRL_RESET_DEFVAL
|
|
#undef CRF_APB_APLL_CTRL_RESET_SHIFT
|
|
#undef CRF_APB_APLL_CTRL_RESET_MASK
|
|
#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
|
|
#define CRF_APB_APLL_CTRL_RESET_SHIFT 0
|
|
#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRF_APB_APLL_CTRL_RESET_DEFVAL
|
|
#undef CRF_APB_APLL_CTRL_RESET_SHIFT
|
|
#undef CRF_APB_APLL_CTRL_RESET_MASK
|
|
#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
|
|
#define CRF_APB_APLL_CTRL_RESET_SHIFT 0
|
|
#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* APLL is locked
|
|
*/
|
|
#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL
|
|
#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT
|
|
#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK
|
|
#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038
|
|
#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0
|
|
#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U
|
|
#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
|
|
#undef CRF_APB_APLL_CTRL_BYPASS_MASK
|
|
#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
|
|
#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Divisor value for this clock.
|
|
*/
|
|
#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
|
|
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* PLL loop filter resistor control
|
|
*/
|
|
#undef CRF_APB_DPLL_CFG_RES_DEFVAL
|
|
#undef CRF_APB_DPLL_CFG_RES_SHIFT
|
|
#undef CRF_APB_DPLL_CFG_RES_MASK
|
|
#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000
|
|
#define CRF_APB_DPLL_CFG_RES_SHIFT 0
|
|
#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU
|
|
|
|
/*
|
|
* PLL charge pump control
|
|
*/
|
|
#undef CRF_APB_DPLL_CFG_CP_DEFVAL
|
|
#undef CRF_APB_DPLL_CFG_CP_SHIFT
|
|
#undef CRF_APB_DPLL_CFG_CP_MASK
|
|
#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000
|
|
#define CRF_APB_DPLL_CFG_CP_SHIFT 5
|
|
#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U
|
|
|
|
/*
|
|
* PLL loop filter high frequency capacitor control
|
|
*/
|
|
#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL
|
|
#undef CRF_APB_DPLL_CFG_LFHF_SHIFT
|
|
#undef CRF_APB_DPLL_CFG_LFHF_MASK
|
|
#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000
|
|
#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10
|
|
#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U
|
|
|
|
/*
|
|
* Lock circuit counter setting
|
|
*/
|
|
#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL
|
|
#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
|
|
#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK
|
|
#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
|
|
#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13
|
|
#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U
|
|
|
|
/*
|
|
* Lock circuit configuration settings for lock windowsize
|
|
*/
|
|
#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL
|
|
#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
|
|
#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK
|
|
#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
|
|
#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25
|
|
#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U
|
|
|
|
/*
|
|
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
|
|
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
|
|
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
|
|
*/
|
|
#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL
|
|
#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
|
|
#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK
|
|
#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09
|
|
#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20
|
|
#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U
|
|
|
|
/*
|
|
* The integer portion of the feedback divider to the PLL
|
|
*/
|
|
#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL
|
|
#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT
|
|
#undef CRF_APB_DPLL_CTRL_FBDIV_MASK
|
|
#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09
|
|
#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8
|
|
#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U
|
|
|
|
/*
|
|
* This turns on the divide by 2 that is inside of the PLL. This does not c
|
|
* hange the VCO frequency, just the output frequency
|
|
*/
|
|
#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL
|
|
#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT
|
|
#undef CRF_APB_DPLL_CTRL_DIV2_MASK
|
|
#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09
|
|
#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16
|
|
#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
|
|
#undef CRF_APB_DPLL_CTRL_BYPASS_MASK
|
|
#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
|
|
#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
|
|
#undef CRF_APB_DPLL_CTRL_RESET_SHIFT
|
|
#undef CRF_APB_DPLL_CTRL_RESET_MASK
|
|
#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
|
|
#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
|
|
#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
|
|
#undef CRF_APB_DPLL_CTRL_RESET_SHIFT
|
|
#undef CRF_APB_DPLL_CTRL_RESET_MASK
|
|
#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
|
|
#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
|
|
#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* DPLL is locked
|
|
*/
|
|
#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL
|
|
#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT
|
|
#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK
|
|
#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038
|
|
#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1
|
|
#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U
|
|
#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
|
|
#undef CRF_APB_DPLL_CTRL_BYPASS_MASK
|
|
#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
|
|
#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Divisor value for this clock.
|
|
*/
|
|
#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
|
|
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* PLL loop filter resistor control
|
|
*/
|
|
#undef CRF_APB_VPLL_CFG_RES_DEFVAL
|
|
#undef CRF_APB_VPLL_CFG_RES_SHIFT
|
|
#undef CRF_APB_VPLL_CFG_RES_MASK
|
|
#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000
|
|
#define CRF_APB_VPLL_CFG_RES_SHIFT 0
|
|
#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU
|
|
|
|
/*
|
|
* PLL charge pump control
|
|
*/
|
|
#undef CRF_APB_VPLL_CFG_CP_DEFVAL
|
|
#undef CRF_APB_VPLL_CFG_CP_SHIFT
|
|
#undef CRF_APB_VPLL_CFG_CP_MASK
|
|
#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000
|
|
#define CRF_APB_VPLL_CFG_CP_SHIFT 5
|
|
#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U
|
|
|
|
/*
|
|
* PLL loop filter high frequency capacitor control
|
|
*/
|
|
#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL
|
|
#undef CRF_APB_VPLL_CFG_LFHF_SHIFT
|
|
#undef CRF_APB_VPLL_CFG_LFHF_MASK
|
|
#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000
|
|
#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10
|
|
#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U
|
|
|
|
/*
|
|
* Lock circuit counter setting
|
|
*/
|
|
#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL
|
|
#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
|
|
#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK
|
|
#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
|
|
#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13
|
|
#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U
|
|
|
|
/*
|
|
* Lock circuit configuration settings for lock windowsize
|
|
*/
|
|
#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL
|
|
#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
|
|
#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK
|
|
#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
|
|
#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25
|
|
#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U
|
|
|
|
/*
|
|
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
|
|
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
|
|
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
|
|
*/
|
|
#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL
|
|
#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
|
|
#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK
|
|
#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809
|
|
#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20
|
|
#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U
|
|
|
|
/*
|
|
* The integer portion of the feedback divider to the PLL
|
|
*/
|
|
#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL
|
|
#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT
|
|
#undef CRF_APB_VPLL_CTRL_FBDIV_MASK
|
|
#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809
|
|
#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8
|
|
#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U
|
|
|
|
/*
|
|
* This turns on the divide by 2 that is inside of the PLL. This does not c
|
|
* hange the VCO frequency, just the output frequency
|
|
*/
|
|
#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL
|
|
#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT
|
|
#undef CRF_APB_VPLL_CTRL_DIV2_MASK
|
|
#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809
|
|
#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16
|
|
#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
|
|
#undef CRF_APB_VPLL_CTRL_BYPASS_MASK
|
|
#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
|
|
#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
|
|
#undef CRF_APB_VPLL_CTRL_RESET_SHIFT
|
|
#undef CRF_APB_VPLL_CTRL_RESET_MASK
|
|
#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
|
|
#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
|
|
#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
|
|
* in BYPASS.
|
|
*/
|
|
#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
|
|
#undef CRF_APB_VPLL_CTRL_RESET_SHIFT
|
|
#undef CRF_APB_VPLL_CTRL_RESET_MASK
|
|
#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
|
|
#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
|
|
#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
|
|
|
|
/*
|
|
* VPLL is locked
|
|
*/
|
|
#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL
|
|
#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT
|
|
#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK
|
|
#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038
|
|
#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2
|
|
#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U
|
|
#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
|
|
|
|
/*
|
|
* Bypasses the PLL clock. The usable clock will be determined from the POS
|
|
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
|
|
* clock and 4 cycles of the new clock. This is not usually an issue, but d
|
|
* esigners must be aware.)
|
|
*/
|
|
#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
|
|
#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
|
|
#undef CRF_APB_VPLL_CTRL_BYPASS_MASK
|
|
#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
|
|
#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
|
|
#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
|
|
|
|
/*
|
|
* Divisor value for this clock.
|
|
*/
|
|
#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
|
|
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
#undef CRL_APB_GEM3_REF_CTRL_OFFSET
|
|
#define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C
|
|
#undef CRL_APB_QSPI_REF_CTRL_OFFSET
|
|
#define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068
|
|
#undef CRL_APB_SDIO1_REF_CTRL_OFFSET
|
|
#define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070
|
|
#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
|
|
#define IOU_SLCR_SDIO_CLK_CTRL_OFFSET 0XFF18030C
|
|
#undef CRL_APB_UART0_REF_CTRL_OFFSET
|
|
#define CRL_APB_UART0_REF_CTRL_OFFSET 0XFF5E0074
|
|
#undef CRL_APB_UART1_REF_CTRL_OFFSET
|
|
#define CRL_APB_UART1_REF_CTRL_OFFSET 0XFF5E0078
|
|
#undef CRL_APB_I2C0_REF_CTRL_OFFSET
|
|
#define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120
|
|
#undef CRL_APB_I2C1_REF_CTRL_OFFSET
|
|
#define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124
|
|
#undef CRL_APB_CAN1_REF_CTRL_OFFSET
|
|
#define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088
|
|
#undef CRL_APB_CPU_R5_CTRL_OFFSET
|
|
#define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
|
|
#define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C
|
|
#undef CRL_APB_PCAP_CTRL_OFFSET
|
|
#define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
|
|
#define CRL_APB_LPD_SWITCH_CTRL_OFFSET 0XFF5E00A8
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET
|
|
#define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC
|
|
#undef CRL_APB_DBG_LPD_CTRL_OFFSET
|
|
#define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0
|
|
#undef CRL_APB_ADMA_REF_CTRL_OFFSET
|
|
#define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8
|
|
#undef CRL_APB_PL0_REF_CTRL_OFFSET
|
|
#define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0
|
|
#undef CRL_APB_PL1_REF_CTRL_OFFSET
|
|
#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4
|
|
#undef CRL_APB_AMS_REF_CTRL_OFFSET
|
|
#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108
|
|
#undef CRL_APB_DLL_REF_CTRL_OFFSET
|
|
#define CRL_APB_DLL_REF_CTRL_OFFSET 0XFF5E0104
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128
|
|
#undef CRF_APB_SATA_REF_CTRL_OFFSET
|
|
#define CRF_APB_SATA_REF_CTRL_OFFSET 0XFD1A00A0
|
|
#undef CRF_APB_PCIE_REF_CTRL_OFFSET
|
|
#define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 0XFD1A0074
|
|
#undef CRF_APB_DP_STC_REF_CTRL_OFFSET
|
|
#define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C
|
|
#undef CRF_APB_ACPU_CTRL_OFFSET
|
|
#define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060
|
|
#undef CRF_APB_DBG_FPD_CTRL_OFFSET
|
|
#define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068
|
|
#undef CRF_APB_DDR_CTRL_OFFSET
|
|
#define CRF_APB_DDR_CTRL_OFFSET 0XFD1A0080
|
|
#undef CRF_APB_GPU_REF_CTRL_OFFSET
|
|
#define CRF_APB_GPU_REF_CTRL_OFFSET 0XFD1A0084
|
|
#undef CRF_APB_GDMA_REF_CTRL_OFFSET
|
|
#define CRF_APB_GDMA_REF_CTRL_OFFSET 0XFD1A00B8
|
|
#undef CRF_APB_DPDMA_REF_CTRL_OFFSET
|
|
#define CRF_APB_DPDMA_REF_CTRL_OFFSET 0XFD1A00BC
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4
|
|
#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
|
|
#define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 0XFF180380
|
|
#undef FPD_SLCR_WDT_CLK_SEL_OFFSET
|
|
#define FPD_SLCR_WDT_CLK_SEL_OFFSET 0XFD610100
|
|
#undef IOU_SLCR_WDT_CLK_SEL_OFFSET
|
|
#define IOU_SLCR_WDT_CLK_SEL_OFFSET 0XFF180300
|
|
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
|
|
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050
|
|
|
|
/*
|
|
* Clock active for the RX channel
|
|
*/
|
|
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
|
|
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
|
|
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK
|
|
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
|
|
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26
|
|
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500
|
|
#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25
|
|
#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
|
|
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
|
|
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500
|
|
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800
|
|
#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800
|
|
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800
|
|
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800
|
|
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00
|
|
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00
|
|
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00
|
|
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00
|
|
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
|
|
* [51] 1: MIO [76]
|
|
*/
|
|
#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL
|
|
#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
|
|
#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK
|
|
#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000
|
|
#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17
|
|
#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800
|
|
#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
|
|
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
|
|
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
|
|
#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800
|
|
#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
|
|
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
|
|
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
|
|
#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500
|
|
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800
|
|
#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
|
|
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
|
|
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
|
|
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Turing this off will shut down the OCM, some parts of the APM, and preve
|
|
* nt transactions going from the FPD to the LPD and could lead to system h
|
|
* ang
|
|
*/
|
|
#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK
|
|
#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600
|
|
#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600
|
|
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600
|
|
#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK
|
|
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500
|
|
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500
|
|
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500
|
|
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_PCAP_CTRL_CLKACT_MASK
|
|
#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500
|
|
#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500
|
|
#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500
|
|
#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK
|
|
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500
|
|
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500
|
|
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500
|
|
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK
|
|
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800
|
|
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800
|
|
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800
|
|
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK
|
|
#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000
|
|
#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000
|
|
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000
|
|
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000
|
|
#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000
|
|
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000
|
|
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000
|
|
#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
|
|
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
|
|
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000
|
|
#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000
|
|
#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
|
|
#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
|
|
#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000
|
|
#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
|
|
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
|
|
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
|
|
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
|
|
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800
|
|
#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800
|
|
#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
|
|
* of the old clock and 4 cycles of the new clock. This is not usually an
|
|
* issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000
|
|
#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
|
|
* only be toggled after 4 cycles of the old clock and 4 cycles of the new
|
|
* clock. This is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
|
|
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
|
|
* is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600
|
|
#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600
|
|
#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600
|
|
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only
|
|
* be toggled after 4 cycles of the old clock and 4 cycles of the new cloc
|
|
* k. This is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500
|
|
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500
|
|
#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
|
|
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
|
|
* his signal may only be toggled after 4 cycles of the old clock and 4 cyc
|
|
* les of the new clock. This is not usually an issue, but designers must b
|
|
* e aware.)
|
|
*/
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
|
|
* his signal may only be toggled after 4 cycles of the old clock and 4 cyc
|
|
* les of the new clock. This is not usually an issue, but designers must b
|
|
* e aware.)
|
|
*/
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL
|
|
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
|
|
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK
|
|
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200
|
|
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16
|
|
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200
|
|
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
|
|
* led after 4 cycles of the old clock and 4 cycles of the new clock. This
|
|
* is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200
|
|
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200
|
|
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400
|
|
#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
|
|
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400
|
|
#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock. For the half spee
|
|
* d APU Clock
|
|
*/
|
|
#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL
|
|
#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
|
|
#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK
|
|
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400
|
|
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25
|
|
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock. For the full spee
|
|
* d ACPUX Clock. This will shut off the high speed clock to the entire APU
|
|
*/
|
|
#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL
|
|
#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
|
|
#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK
|
|
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400
|
|
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24
|
|
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500
|
|
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
|
|
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
|
|
* is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500
|
|
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK
|
|
#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500
|
|
#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500
|
|
#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
|
|
* of the old clock and 4 cycles of the new clock. This is not usually an i
|
|
* ssue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_DDR_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500
|
|
#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
|
|
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
|
|
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
|
|
* is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500
|
|
#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock, which will stop c
|
|
* lock for GPU (and both Pixel Processors).
|
|
*/
|
|
#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500
|
|
#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
|
|
* k only to this Pixel Processor
|
|
*/
|
|
#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL
|
|
#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
|
|
#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK
|
|
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500
|
|
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25
|
|
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U
|
|
|
|
/*
|
|
* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
|
|
* k only to this Pixel Processor
|
|
*/
|
|
#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL
|
|
#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
|
|
#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK
|
|
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500
|
|
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26
|
|
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
|
|
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
|
|
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
|
|
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
|
|
#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
|
|
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
|
|
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
|
|
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK
|
|
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
|
|
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
|
|
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
|
|
* usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
|
|
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
|
|
* is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* Clock active signal. Switch to 0 to disable the clock
|
|
*/
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
|
|
#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24
|
|
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U
|
|
|
|
/*
|
|
* 6 bit divider
|
|
*/
|
|
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
|
|
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
|
|
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK
|
|
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00
|
|
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8
|
|
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U
|
|
|
|
/*
|
|
* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
|
|
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
|
|
* is not usually an issue, but designers must be aware.)
|
|
*/
|
|
#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL
|
|
#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
|
|
#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK
|
|
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00
|
|
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0
|
|
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U
|
|
|
|
/*
|
|
* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
|
|
* lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
|
|
* clock for the APB interface of TTC0
|
|
*/
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U
|
|
|
|
/*
|
|
* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
|
|
* lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
|
|
* clock for the APB interface of TTC1
|
|
*/
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU
|
|
|
|
/*
|
|
* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
|
|
* lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
|
|
* clock for the APB interface of TTC2
|
|
*/
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U
|
|
|
|
/*
|
|
* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
|
|
* lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
|
|
* clock for the APB interface of TTC3
|
|
*/
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
|
|
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6
|
|
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U
|
|
|
|
/*
|
|
* System watchdog timer clock source selection: 0: Internal APB clock 1: E
|
|
* xternal (PL clock via EMIO or Pinout clock via MIO)
|
|
*/
|
|
#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
|
|
#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
|
|
#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK
|
|
#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
|
|
#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0
|
|
#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U
|
|
|
|
/*
|
|
* System watchdog timer clock source selection: 0: internal clock APB cloc
|
|
* k 1: external clock from PL via EMIO, or from pinout via MIO
|
|
*/
|
|
#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
|
|
#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
|
|
#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK
|
|
#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
|
|
#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0
|
|
#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U
|
|
|
|
/*
|
|
* System watchdog timer clock source selection: 0: internal clock APB cloc
|
|
* k 1: external clock pss_ref_clk
|
|
*/
|
|
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL
|
|
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
|
|
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK
|
|
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
|
|
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0
|
|
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U
|
|
#undef CRF_APB_RST_DDR_SS_OFFSET
|
|
#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108
|
|
#undef DDRC_MSTR_OFFSET
|
|
#define DDRC_MSTR_OFFSET 0XFD070000
|
|
#undef DDRC_MRCTRL0_OFFSET
|
|
#define DDRC_MRCTRL0_OFFSET 0XFD070010
|
|
#undef DDRC_DERATEEN_OFFSET
|
|
#define DDRC_DERATEEN_OFFSET 0XFD070020
|
|
#undef DDRC_DERATEINT_OFFSET
|
|
#define DDRC_DERATEINT_OFFSET 0XFD070024
|
|
#undef DDRC_PWRCTL_OFFSET
|
|
#define DDRC_PWRCTL_OFFSET 0XFD070030
|
|
#undef DDRC_PWRTMG_OFFSET
|
|
#define DDRC_PWRTMG_OFFSET 0XFD070034
|
|
#undef DDRC_RFSHCTL0_OFFSET
|
|
#define DDRC_RFSHCTL0_OFFSET 0XFD070050
|
|
#undef DDRC_RFSHCTL1_OFFSET
|
|
#define DDRC_RFSHCTL1_OFFSET 0XFD070054
|
|
#undef DDRC_RFSHCTL3_OFFSET
|
|
#define DDRC_RFSHCTL3_OFFSET 0XFD070060
|
|
#undef DDRC_RFSHTMG_OFFSET
|
|
#define DDRC_RFSHTMG_OFFSET 0XFD070064
|
|
#undef DDRC_ECCCFG0_OFFSET
|
|
#define DDRC_ECCCFG0_OFFSET 0XFD070070
|
|
#undef DDRC_ECCCFG1_OFFSET
|
|
#define DDRC_ECCCFG1_OFFSET 0XFD070074
|
|
#undef DDRC_CRCPARCTL1_OFFSET
|
|
#define DDRC_CRCPARCTL1_OFFSET 0XFD0700C4
|
|
#undef DDRC_CRCPARCTL2_OFFSET
|
|
#define DDRC_CRCPARCTL2_OFFSET 0XFD0700C8
|
|
#undef DDRC_INIT0_OFFSET
|
|
#define DDRC_INIT0_OFFSET 0XFD0700D0
|
|
#undef DDRC_INIT1_OFFSET
|
|
#define DDRC_INIT1_OFFSET 0XFD0700D4
|
|
#undef DDRC_INIT2_OFFSET
|
|
#define DDRC_INIT2_OFFSET 0XFD0700D8
|
|
#undef DDRC_INIT3_OFFSET
|
|
#define DDRC_INIT3_OFFSET 0XFD0700DC
|
|
#undef DDRC_INIT4_OFFSET
|
|
#define DDRC_INIT4_OFFSET 0XFD0700E0
|
|
#undef DDRC_INIT5_OFFSET
|
|
#define DDRC_INIT5_OFFSET 0XFD0700E4
|
|
#undef DDRC_INIT6_OFFSET
|
|
#define DDRC_INIT6_OFFSET 0XFD0700E8
|
|
#undef DDRC_INIT7_OFFSET
|
|
#define DDRC_INIT7_OFFSET 0XFD0700EC
|
|
#undef DDRC_DIMMCTL_OFFSET
|
|
#define DDRC_DIMMCTL_OFFSET 0XFD0700F0
|
|
#undef DDRC_RANKCTL_OFFSET
|
|
#define DDRC_RANKCTL_OFFSET 0XFD0700F4
|
|
#undef DDRC_DRAMTMG0_OFFSET
|
|
#define DDRC_DRAMTMG0_OFFSET 0XFD070100
|
|
#undef DDRC_DRAMTMG1_OFFSET
|
|
#define DDRC_DRAMTMG1_OFFSET 0XFD070104
|
|
#undef DDRC_DRAMTMG2_OFFSET
|
|
#define DDRC_DRAMTMG2_OFFSET 0XFD070108
|
|
#undef DDRC_DRAMTMG3_OFFSET
|
|
#define DDRC_DRAMTMG3_OFFSET 0XFD07010C
|
|
#undef DDRC_DRAMTMG4_OFFSET
|
|
#define DDRC_DRAMTMG4_OFFSET 0XFD070110
|
|
#undef DDRC_DRAMTMG5_OFFSET
|
|
#define DDRC_DRAMTMG5_OFFSET 0XFD070114
|
|
#undef DDRC_DRAMTMG6_OFFSET
|
|
#define DDRC_DRAMTMG6_OFFSET 0XFD070118
|
|
#undef DDRC_DRAMTMG7_OFFSET
|
|
#define DDRC_DRAMTMG7_OFFSET 0XFD07011C
|
|
#undef DDRC_DRAMTMG8_OFFSET
|
|
#define DDRC_DRAMTMG8_OFFSET 0XFD070120
|
|
#undef DDRC_DRAMTMG9_OFFSET
|
|
#define DDRC_DRAMTMG9_OFFSET 0XFD070124
|
|
#undef DDRC_DRAMTMG11_OFFSET
|
|
#define DDRC_DRAMTMG11_OFFSET 0XFD07012C
|
|
#undef DDRC_DRAMTMG12_OFFSET
|
|
#define DDRC_DRAMTMG12_OFFSET 0XFD070130
|
|
#undef DDRC_ZQCTL0_OFFSET
|
|
#define DDRC_ZQCTL0_OFFSET 0XFD070180
|
|
#undef DDRC_ZQCTL1_OFFSET
|
|
#define DDRC_ZQCTL1_OFFSET 0XFD070184
|
|
#undef DDRC_DFITMG0_OFFSET
|
|
#define DDRC_DFITMG0_OFFSET 0XFD070190
|
|
#undef DDRC_DFITMG1_OFFSET
|
|
#define DDRC_DFITMG1_OFFSET 0XFD070194
|
|
#undef DDRC_DFILPCFG0_OFFSET
|
|
#define DDRC_DFILPCFG0_OFFSET 0XFD070198
|
|
#undef DDRC_DFILPCFG1_OFFSET
|
|
#define DDRC_DFILPCFG1_OFFSET 0XFD07019C
|
|
#undef DDRC_DFIUPD0_OFFSET
|
|
#define DDRC_DFIUPD0_OFFSET 0XFD0701A0
|
|
#undef DDRC_DFIUPD1_OFFSET
|
|
#define DDRC_DFIUPD1_OFFSET 0XFD0701A4
|
|
#undef DDRC_DFIMISC_OFFSET
|
|
#define DDRC_DFIMISC_OFFSET 0XFD0701B0
|
|
#undef DDRC_DFITMG2_OFFSET
|
|
#define DDRC_DFITMG2_OFFSET 0XFD0701B4
|
|
#undef DDRC_DBICTL_OFFSET
|
|
#define DDRC_DBICTL_OFFSET 0XFD0701C0
|
|
#undef DDRC_ADDRMAP0_OFFSET
|
|
#define DDRC_ADDRMAP0_OFFSET 0XFD070200
|
|
#undef DDRC_ADDRMAP1_OFFSET
|
|
#define DDRC_ADDRMAP1_OFFSET 0XFD070204
|
|
#undef DDRC_ADDRMAP2_OFFSET
|
|
#define DDRC_ADDRMAP2_OFFSET 0XFD070208
|
|
#undef DDRC_ADDRMAP3_OFFSET
|
|
#define DDRC_ADDRMAP3_OFFSET 0XFD07020C
|
|
#undef DDRC_ADDRMAP4_OFFSET
|
|
#define DDRC_ADDRMAP4_OFFSET 0XFD070210
|
|
#undef DDRC_ADDRMAP5_OFFSET
|
|
#define DDRC_ADDRMAP5_OFFSET 0XFD070214
|
|
#undef DDRC_ADDRMAP6_OFFSET
|
|
#define DDRC_ADDRMAP6_OFFSET 0XFD070218
|
|
#undef DDRC_ADDRMAP7_OFFSET
|
|
#define DDRC_ADDRMAP7_OFFSET 0XFD07021C
|
|
#undef DDRC_ADDRMAP8_OFFSET
|
|
#define DDRC_ADDRMAP8_OFFSET 0XFD070220
|
|
#undef DDRC_ADDRMAP9_OFFSET
|
|
#define DDRC_ADDRMAP9_OFFSET 0XFD070224
|
|
#undef DDRC_ADDRMAP10_OFFSET
|
|
#define DDRC_ADDRMAP10_OFFSET 0XFD070228
|
|
#undef DDRC_ADDRMAP11_OFFSET
|
|
#define DDRC_ADDRMAP11_OFFSET 0XFD07022C
|
|
#undef DDRC_ODTCFG_OFFSET
|
|
#define DDRC_ODTCFG_OFFSET 0XFD070240
|
|
#undef DDRC_ODTMAP_OFFSET
|
|
#define DDRC_ODTMAP_OFFSET 0XFD070244
|
|
#undef DDRC_SCHED_OFFSET
|
|
#define DDRC_SCHED_OFFSET 0XFD070250
|
|
#undef DDRC_PERFLPR1_OFFSET
|
|
#define DDRC_PERFLPR1_OFFSET 0XFD070264
|
|
#undef DDRC_PERFWR1_OFFSET
|
|
#define DDRC_PERFWR1_OFFSET 0XFD07026C
|
|
#undef DDRC_DQMAP0_OFFSET
|
|
#define DDRC_DQMAP0_OFFSET 0XFD070280
|
|
#undef DDRC_DQMAP1_OFFSET
|
|
#define DDRC_DQMAP1_OFFSET 0XFD070284
|
|
#undef DDRC_DQMAP2_OFFSET
|
|
#define DDRC_DQMAP2_OFFSET 0XFD070288
|
|
#undef DDRC_DQMAP3_OFFSET
|
|
#define DDRC_DQMAP3_OFFSET 0XFD07028C
|
|
#undef DDRC_DQMAP4_OFFSET
|
|
#define DDRC_DQMAP4_OFFSET 0XFD070290
|
|
#undef DDRC_DQMAP5_OFFSET
|
|
#define DDRC_DQMAP5_OFFSET 0XFD070294
|
|
#undef DDRC_DBG0_OFFSET
|
|
#define DDRC_DBG0_OFFSET 0XFD070300
|
|
#undef DDRC_DBGCMD_OFFSET
|
|
#define DDRC_DBGCMD_OFFSET 0XFD07030C
|
|
#undef DDRC_SWCTL_OFFSET
|
|
#define DDRC_SWCTL_OFFSET 0XFD070320
|
|
#undef DDRC_PCCFG_OFFSET
|
|
#define DDRC_PCCFG_OFFSET 0XFD070400
|
|
#undef DDRC_PCFGR_0_OFFSET
|
|
#define DDRC_PCFGR_0_OFFSET 0XFD070404
|
|
#undef DDRC_PCFGW_0_OFFSET
|
|
#define DDRC_PCFGW_0_OFFSET 0XFD070408
|
|
#undef DDRC_PCTRL_0_OFFSET
|
|
#define DDRC_PCTRL_0_OFFSET 0XFD070490
|
|
#undef DDRC_PCFGQOS0_0_OFFSET
|
|
#define DDRC_PCFGQOS0_0_OFFSET 0XFD070494
|
|
#undef DDRC_PCFGQOS1_0_OFFSET
|
|
#define DDRC_PCFGQOS1_0_OFFSET 0XFD070498
|
|
#undef DDRC_PCFGR_1_OFFSET
|
|
#define DDRC_PCFGR_1_OFFSET 0XFD0704B4
|
|
#undef DDRC_PCFGW_1_OFFSET
|
|
#define DDRC_PCFGW_1_OFFSET 0XFD0704B8
|
|
#undef DDRC_PCTRL_1_OFFSET
|
|
#define DDRC_PCTRL_1_OFFSET 0XFD070540
|
|
#undef DDRC_PCFGQOS0_1_OFFSET
|
|
#define DDRC_PCFGQOS0_1_OFFSET 0XFD070544
|
|
#undef DDRC_PCFGQOS1_1_OFFSET
|
|
#define DDRC_PCFGQOS1_1_OFFSET 0XFD070548
|
|
#undef DDRC_PCFGR_2_OFFSET
|
|
#define DDRC_PCFGR_2_OFFSET 0XFD070564
|
|
#undef DDRC_PCFGW_2_OFFSET
|
|
#define DDRC_PCFGW_2_OFFSET 0XFD070568
|
|
#undef DDRC_PCTRL_2_OFFSET
|
|
#define DDRC_PCTRL_2_OFFSET 0XFD0705F0
|
|
#undef DDRC_PCFGQOS0_2_OFFSET
|
|
#define DDRC_PCFGQOS0_2_OFFSET 0XFD0705F4
|
|
#undef DDRC_PCFGQOS1_2_OFFSET
|
|
#define DDRC_PCFGQOS1_2_OFFSET 0XFD0705F8
|
|
#undef DDRC_PCFGR_3_OFFSET
|
|
#define DDRC_PCFGR_3_OFFSET 0XFD070614
|
|
#undef DDRC_PCFGW_3_OFFSET
|
|
#define DDRC_PCFGW_3_OFFSET 0XFD070618
|
|
#undef DDRC_PCTRL_3_OFFSET
|
|
#define DDRC_PCTRL_3_OFFSET 0XFD0706A0
|
|
#undef DDRC_PCFGQOS0_3_OFFSET
|
|
#define DDRC_PCFGQOS0_3_OFFSET 0XFD0706A4
|
|
#undef DDRC_PCFGQOS1_3_OFFSET
|
|
#define DDRC_PCFGQOS1_3_OFFSET 0XFD0706A8
|
|
#undef DDRC_PCFGWQOS0_3_OFFSET
|
|
#define DDRC_PCFGWQOS0_3_OFFSET 0XFD0706AC
|
|
#undef DDRC_PCFGWQOS1_3_OFFSET
|
|
#define DDRC_PCFGWQOS1_3_OFFSET 0XFD0706B0
|
|
#undef DDRC_PCFGR_4_OFFSET
|
|
#define DDRC_PCFGR_4_OFFSET 0XFD0706C4
|
|
#undef DDRC_PCFGW_4_OFFSET
|
|
#define DDRC_PCFGW_4_OFFSET 0XFD0706C8
|
|
#undef DDRC_PCTRL_4_OFFSET
|
|
#define DDRC_PCTRL_4_OFFSET 0XFD070750
|
|
#undef DDRC_PCFGQOS0_4_OFFSET
|
|
#define DDRC_PCFGQOS0_4_OFFSET 0XFD070754
|
|
#undef DDRC_PCFGQOS1_4_OFFSET
|
|
#define DDRC_PCFGQOS1_4_OFFSET 0XFD070758
|
|
#undef DDRC_PCFGWQOS0_4_OFFSET
|
|
#define DDRC_PCFGWQOS0_4_OFFSET 0XFD07075C
|
|
#undef DDRC_PCFGWQOS1_4_OFFSET
|
|
#define DDRC_PCFGWQOS1_4_OFFSET 0XFD070760
|
|
#undef DDRC_PCFGR_5_OFFSET
|
|
#define DDRC_PCFGR_5_OFFSET 0XFD070774
|
|
#undef DDRC_PCFGW_5_OFFSET
|
|
#define DDRC_PCFGW_5_OFFSET 0XFD070778
|
|
#undef DDRC_PCTRL_5_OFFSET
|
|
#define DDRC_PCTRL_5_OFFSET 0XFD070800
|
|
#undef DDRC_PCFGQOS0_5_OFFSET
|
|
#define DDRC_PCFGQOS0_5_OFFSET 0XFD070804
|
|
#undef DDRC_PCFGQOS1_5_OFFSET
|
|
#define DDRC_PCFGQOS1_5_OFFSET 0XFD070808
|
|
#undef DDRC_PCFGWQOS0_5_OFFSET
|
|
#define DDRC_PCFGWQOS0_5_OFFSET 0XFD07080C
|
|
#undef DDRC_PCFGWQOS1_5_OFFSET
|
|
#define DDRC_PCFGWQOS1_5_OFFSET 0XFD070810
|
|
#undef DDRC_SARBASE0_OFFSET
|
|
#define DDRC_SARBASE0_OFFSET 0XFD070F04
|
|
#undef DDRC_SARSIZE0_OFFSET
|
|
#define DDRC_SARSIZE0_OFFSET 0XFD070F08
|
|
#undef DDRC_SARBASE1_OFFSET
|
|
#define DDRC_SARBASE1_OFFSET 0XFD070F0C
|
|
#undef DDRC_SARSIZE1_OFFSET
|
|
#define DDRC_SARSIZE1_OFFSET 0XFD070F10
|
|
#undef DDRC_DFITMG0_SHADOW_OFFSET
|
|
#define DDRC_DFITMG0_SHADOW_OFFSET 0XFD072190
|
|
#undef CRF_APB_RST_DDR_SS_OFFSET
|
|
#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108
|
|
#undef DDR_PHY_PGCR0_OFFSET
|
|
#define DDR_PHY_PGCR0_OFFSET 0XFD080010
|
|
#undef DDR_PHY_PGCR2_OFFSET
|
|
#define DDR_PHY_PGCR2_OFFSET 0XFD080018
|
|
#undef DDR_PHY_PGCR3_OFFSET
|
|
#define DDR_PHY_PGCR3_OFFSET 0XFD08001C
|
|
#undef DDR_PHY_PGCR5_OFFSET
|
|
#define DDR_PHY_PGCR5_OFFSET 0XFD080024
|
|
#undef DDR_PHY_PTR0_OFFSET
|
|
#define DDR_PHY_PTR0_OFFSET 0XFD080040
|
|
#undef DDR_PHY_PTR1_OFFSET
|
|
#define DDR_PHY_PTR1_OFFSET 0XFD080044
|
|
#undef DDR_PHY_PLLCR0_OFFSET
|
|
#define DDR_PHY_PLLCR0_OFFSET 0XFD080068
|
|
#undef DDR_PHY_DSGCR_OFFSET
|
|
#define DDR_PHY_DSGCR_OFFSET 0XFD080090
|
|
#undef DDR_PHY_GPR0_OFFSET
|
|
#define DDR_PHY_GPR0_OFFSET 0XFD0800C0
|
|
#undef DDR_PHY_GPR1_OFFSET
|
|
#define DDR_PHY_GPR1_OFFSET 0XFD0800C4
|
|
#undef DDR_PHY_DCR_OFFSET
|
|
#define DDR_PHY_DCR_OFFSET 0XFD080100
|
|
#undef DDR_PHY_DTPR0_OFFSET
|
|
#define DDR_PHY_DTPR0_OFFSET 0XFD080110
|
|
#undef DDR_PHY_DTPR1_OFFSET
|
|
#define DDR_PHY_DTPR1_OFFSET 0XFD080114
|
|
#undef DDR_PHY_DTPR2_OFFSET
|
|
#define DDR_PHY_DTPR2_OFFSET 0XFD080118
|
|
#undef DDR_PHY_DTPR3_OFFSET
|
|
#define DDR_PHY_DTPR3_OFFSET 0XFD08011C
|
|
#undef DDR_PHY_DTPR4_OFFSET
|
|
#define DDR_PHY_DTPR4_OFFSET 0XFD080120
|
|
#undef DDR_PHY_DTPR5_OFFSET
|
|
#define DDR_PHY_DTPR5_OFFSET 0XFD080124
|
|
#undef DDR_PHY_DTPR6_OFFSET
|
|
#define DDR_PHY_DTPR6_OFFSET 0XFD080128
|
|
#undef DDR_PHY_RDIMMGCR0_OFFSET
|
|
#define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140
|
|
#undef DDR_PHY_RDIMMGCR1_OFFSET
|
|
#define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144
|
|
#undef DDR_PHY_RDIMMCR0_OFFSET
|
|
#define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150
|
|
#undef DDR_PHY_RDIMMCR1_OFFSET
|
|
#define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154
|
|
#undef DDR_PHY_MR0_OFFSET
|
|
#define DDR_PHY_MR0_OFFSET 0XFD080180
|
|
#undef DDR_PHY_MR1_OFFSET
|
|
#define DDR_PHY_MR1_OFFSET 0XFD080184
|
|
#undef DDR_PHY_MR2_OFFSET
|
|
#define DDR_PHY_MR2_OFFSET 0XFD080188
|
|
#undef DDR_PHY_MR3_OFFSET
|
|
#define DDR_PHY_MR3_OFFSET 0XFD08018C
|
|
#undef DDR_PHY_MR4_OFFSET
|
|
#define DDR_PHY_MR4_OFFSET 0XFD080190
|
|
#undef DDR_PHY_MR5_OFFSET
|
|
#define DDR_PHY_MR5_OFFSET 0XFD080194
|
|
#undef DDR_PHY_MR6_OFFSET
|
|
#define DDR_PHY_MR6_OFFSET 0XFD080198
|
|
#undef DDR_PHY_MR11_OFFSET
|
|
#define DDR_PHY_MR11_OFFSET 0XFD0801AC
|
|
#undef DDR_PHY_MR12_OFFSET
|
|
#define DDR_PHY_MR12_OFFSET 0XFD0801B0
|
|
#undef DDR_PHY_MR13_OFFSET
|
|
#define DDR_PHY_MR13_OFFSET 0XFD0801B4
|
|
#undef DDR_PHY_MR14_OFFSET
|
|
#define DDR_PHY_MR14_OFFSET 0XFD0801B8
|
|
#undef DDR_PHY_MR22_OFFSET
|
|
#define DDR_PHY_MR22_OFFSET 0XFD0801D8
|
|
#undef DDR_PHY_DTCR0_OFFSET
|
|
#define DDR_PHY_DTCR0_OFFSET 0XFD080200
|
|
#undef DDR_PHY_DTCR1_OFFSET
|
|
#define DDR_PHY_DTCR1_OFFSET 0XFD080204
|
|
#undef DDR_PHY_CATR0_OFFSET
|
|
#define DDR_PHY_CATR0_OFFSET 0XFD080240
|
|
#undef DDR_PHY_DQSDR0_OFFSET
|
|
#define DDR_PHY_DQSDR0_OFFSET 0XFD080250
|
|
#undef DDR_PHY_BISTLSR_OFFSET
|
|
#define DDR_PHY_BISTLSR_OFFSET 0XFD080414
|
|
#undef DDR_PHY_RIOCR5_OFFSET
|
|
#define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4
|
|
#undef DDR_PHY_ACIOCR0_OFFSET
|
|
#define DDR_PHY_ACIOCR0_OFFSET 0XFD080500
|
|
#undef DDR_PHY_ACIOCR2_OFFSET
|
|
#define DDR_PHY_ACIOCR2_OFFSET 0XFD080508
|
|
#undef DDR_PHY_ACIOCR3_OFFSET
|
|
#define DDR_PHY_ACIOCR3_OFFSET 0XFD08050C
|
|
#undef DDR_PHY_ACIOCR4_OFFSET
|
|
#define DDR_PHY_ACIOCR4_OFFSET 0XFD080510
|
|
#undef DDR_PHY_IOVCR0_OFFSET
|
|
#define DDR_PHY_IOVCR0_OFFSET 0XFD080520
|
|
#undef DDR_PHY_VTCR0_OFFSET
|
|
#define DDR_PHY_VTCR0_OFFSET 0XFD080528
|
|
#undef DDR_PHY_VTCR1_OFFSET
|
|
#define DDR_PHY_VTCR1_OFFSET 0XFD08052C
|
|
#undef DDR_PHY_ACBDLR1_OFFSET
|
|
#define DDR_PHY_ACBDLR1_OFFSET 0XFD080544
|
|
#undef DDR_PHY_ACBDLR2_OFFSET
|
|
#define DDR_PHY_ACBDLR2_OFFSET 0XFD080548
|
|
#undef DDR_PHY_ACBDLR6_OFFSET
|
|
#define DDR_PHY_ACBDLR6_OFFSET 0XFD080558
|
|
#undef DDR_PHY_ACBDLR7_OFFSET
|
|
#define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C
|
|
#undef DDR_PHY_ACBDLR8_OFFSET
|
|
#define DDR_PHY_ACBDLR8_OFFSET 0XFD080560
|
|
#undef DDR_PHY_ACBDLR9_OFFSET
|
|
#define DDR_PHY_ACBDLR9_OFFSET 0XFD080564
|
|
#undef DDR_PHY_ZQCR_OFFSET
|
|
#define DDR_PHY_ZQCR_OFFSET 0XFD080680
|
|
#undef DDR_PHY_ZQ0PR0_OFFSET
|
|
#define DDR_PHY_ZQ0PR0_OFFSET 0XFD080684
|
|
#undef DDR_PHY_ZQ0OR0_OFFSET
|
|
#define DDR_PHY_ZQ0OR0_OFFSET 0XFD080694
|
|
#undef DDR_PHY_ZQ0OR1_OFFSET
|
|
#define DDR_PHY_ZQ0OR1_OFFSET 0XFD080698
|
|
#undef DDR_PHY_ZQ1PR0_OFFSET
|
|
#define DDR_PHY_ZQ1PR0_OFFSET 0XFD0806A4
|
|
#undef DDR_PHY_DX0GCR0_OFFSET
|
|
#define DDR_PHY_DX0GCR0_OFFSET 0XFD080700
|
|
#undef DDR_PHY_DX0GCR1_OFFSET
|
|
#define DDR_PHY_DX0GCR1_OFFSET 0XFD080704
|
|
#undef DDR_PHY_DX0GCR3_OFFSET
|
|
#define DDR_PHY_DX0GCR3_OFFSET 0XFD08070C
|
|
#undef DDR_PHY_DX0GCR4_OFFSET
|
|
#define DDR_PHY_DX0GCR4_OFFSET 0XFD080710
|
|
#undef DDR_PHY_DX0GCR5_OFFSET
|
|
#define DDR_PHY_DX0GCR5_OFFSET 0XFD080714
|
|
#undef DDR_PHY_DX0GCR6_OFFSET
|
|
#define DDR_PHY_DX0GCR6_OFFSET 0XFD080718
|
|
#undef DDR_PHY_DX1GCR0_OFFSET
|
|
#define DDR_PHY_DX1GCR0_OFFSET 0XFD080800
|
|
#undef DDR_PHY_DX1GCR1_OFFSET
|
|
#define DDR_PHY_DX1GCR1_OFFSET 0XFD080804
|
|
#undef DDR_PHY_DX1GCR3_OFFSET
|
|
#define DDR_PHY_DX1GCR3_OFFSET 0XFD08080C
|
|
#undef DDR_PHY_DX1GCR4_OFFSET
|
|
#define DDR_PHY_DX1GCR4_OFFSET 0XFD080810
|
|
#undef DDR_PHY_DX1GCR5_OFFSET
|
|
#define DDR_PHY_DX1GCR5_OFFSET 0XFD080814
|
|
#undef DDR_PHY_DX1GCR6_OFFSET
|
|
#define DDR_PHY_DX1GCR6_OFFSET 0XFD080818
|
|
#undef DDR_PHY_DX2GCR0_OFFSET
|
|
#define DDR_PHY_DX2GCR0_OFFSET 0XFD080900
|
|
#undef DDR_PHY_DX2GCR1_OFFSET
|
|
#define DDR_PHY_DX2GCR1_OFFSET 0XFD080904
|
|
#undef DDR_PHY_DX2GCR3_OFFSET
|
|
#define DDR_PHY_DX2GCR3_OFFSET 0XFD08090C
|
|
#undef DDR_PHY_DX2GCR4_OFFSET
|
|
#define DDR_PHY_DX2GCR4_OFFSET 0XFD080910
|
|
#undef DDR_PHY_DX2GCR5_OFFSET
|
|
#define DDR_PHY_DX2GCR5_OFFSET 0XFD080914
|
|
#undef DDR_PHY_DX2GCR6_OFFSET
|
|
#define DDR_PHY_DX2GCR6_OFFSET 0XFD080918
|
|
#undef DDR_PHY_DX3GCR0_OFFSET
|
|
#define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00
|
|
#undef DDR_PHY_DX3GCR1_OFFSET
|
|
#define DDR_PHY_DX3GCR1_OFFSET 0XFD080A04
|
|
#undef DDR_PHY_DX3GCR3_OFFSET
|
|
#define DDR_PHY_DX3GCR3_OFFSET 0XFD080A0C
|
|
#undef DDR_PHY_DX3GCR4_OFFSET
|
|
#define DDR_PHY_DX3GCR4_OFFSET 0XFD080A10
|
|
#undef DDR_PHY_DX3GCR5_OFFSET
|
|
#define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14
|
|
#undef DDR_PHY_DX3GCR6_OFFSET
|
|
#define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18
|
|
#undef DDR_PHY_DX4GCR0_OFFSET
|
|
#define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00
|
|
#undef DDR_PHY_DX4GCR1_OFFSET
|
|
#define DDR_PHY_DX4GCR1_OFFSET 0XFD080B04
|
|
#undef DDR_PHY_DX4GCR2_OFFSET
|
|
#define DDR_PHY_DX4GCR2_OFFSET 0XFD080B08
|
|
#undef DDR_PHY_DX4GCR3_OFFSET
|
|
#define DDR_PHY_DX4GCR3_OFFSET 0XFD080B0C
|
|
#undef DDR_PHY_DX4GCR4_OFFSET
|
|
#define DDR_PHY_DX4GCR4_OFFSET 0XFD080B10
|
|
#undef DDR_PHY_DX4GCR5_OFFSET
|
|
#define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14
|
|
#undef DDR_PHY_DX4GCR6_OFFSET
|
|
#define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18
|
|
#undef DDR_PHY_DX5GCR0_OFFSET
|
|
#define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00
|
|
#undef DDR_PHY_DX5GCR1_OFFSET
|
|
#define DDR_PHY_DX5GCR1_OFFSET 0XFD080C04
|
|
#undef DDR_PHY_DX5GCR2_OFFSET
|
|
#define DDR_PHY_DX5GCR2_OFFSET 0XFD080C08
|
|
#undef DDR_PHY_DX5GCR3_OFFSET
|
|
#define DDR_PHY_DX5GCR3_OFFSET 0XFD080C0C
|
|
#undef DDR_PHY_DX5GCR4_OFFSET
|
|
#define DDR_PHY_DX5GCR4_OFFSET 0XFD080C10
|
|
#undef DDR_PHY_DX5GCR5_OFFSET
|
|
#define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14
|
|
#undef DDR_PHY_DX5GCR6_OFFSET
|
|
#define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18
|
|
#undef DDR_PHY_DX6GCR0_OFFSET
|
|
#define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00
|
|
#undef DDR_PHY_DX6GCR1_OFFSET
|
|
#define DDR_PHY_DX6GCR1_OFFSET 0XFD080D04
|
|
#undef DDR_PHY_DX6GCR2_OFFSET
|
|
#define DDR_PHY_DX6GCR2_OFFSET 0XFD080D08
|
|
#undef DDR_PHY_DX6GCR3_OFFSET
|
|
#define DDR_PHY_DX6GCR3_OFFSET 0XFD080D0C
|
|
#undef DDR_PHY_DX6GCR4_OFFSET
|
|
#define DDR_PHY_DX6GCR4_OFFSET 0XFD080D10
|
|
#undef DDR_PHY_DX6GCR5_OFFSET
|
|
#define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14
|
|
#undef DDR_PHY_DX6GCR6_OFFSET
|
|
#define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18
|
|
#undef DDR_PHY_DX7GCR0_OFFSET
|
|
#define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00
|
|
#undef DDR_PHY_DX7GCR1_OFFSET
|
|
#define DDR_PHY_DX7GCR1_OFFSET 0XFD080E04
|
|
#undef DDR_PHY_DX7GCR2_OFFSET
|
|
#define DDR_PHY_DX7GCR2_OFFSET 0XFD080E08
|
|
#undef DDR_PHY_DX7GCR3_OFFSET
|
|
#define DDR_PHY_DX7GCR3_OFFSET 0XFD080E0C
|
|
#undef DDR_PHY_DX7GCR4_OFFSET
|
|
#define DDR_PHY_DX7GCR4_OFFSET 0XFD080E10
|
|
#undef DDR_PHY_DX7GCR5_OFFSET
|
|
#define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14
|
|
#undef DDR_PHY_DX7GCR6_OFFSET
|
|
#define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18
|
|
#undef DDR_PHY_DX8GCR0_OFFSET
|
|
#define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00
|
|
#undef DDR_PHY_DX8GCR1_OFFSET
|
|
#define DDR_PHY_DX8GCR1_OFFSET 0XFD080F04
|
|
#undef DDR_PHY_DX8GCR2_OFFSET
|
|
#define DDR_PHY_DX8GCR2_OFFSET 0XFD080F08
|
|
#undef DDR_PHY_DX8GCR3_OFFSET
|
|
#define DDR_PHY_DX8GCR3_OFFSET 0XFD080F0C
|
|
#undef DDR_PHY_DX8GCR4_OFFSET
|
|
#define DDR_PHY_DX8GCR4_OFFSET 0XFD080F10
|
|
#undef DDR_PHY_DX8GCR5_OFFSET
|
|
#define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14
|
|
#undef DDR_PHY_DX8GCR6_OFFSET
|
|
#define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18
|
|
#undef DDR_PHY_DX8SL0OSC_OFFSET
|
|
#define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400
|
|
#undef DDR_PHY_DX8SL0PLLCR0_OFFSET
|
|
#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404
|
|
#undef DDR_PHY_DX8SL0DQSCTL_OFFSET
|
|
#define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C
|
|
#undef DDR_PHY_DX8SL0DXCTL2_OFFSET
|
|
#define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C
|
|
#undef DDR_PHY_DX8SL0IOCR_OFFSET
|
|
#define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430
|
|
#undef DDR_PHY_DX8SL1OSC_OFFSET
|
|
#define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440
|
|
#undef DDR_PHY_DX8SL1PLLCR0_OFFSET
|
|
#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444
|
|
#undef DDR_PHY_DX8SL1DQSCTL_OFFSET
|
|
#define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C
|
|
#undef DDR_PHY_DX8SL1DXCTL2_OFFSET
|
|
#define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C
|
|
#undef DDR_PHY_DX8SL1IOCR_OFFSET
|
|
#define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470
|
|
#undef DDR_PHY_DX8SL2OSC_OFFSET
|
|
#define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480
|
|
#undef DDR_PHY_DX8SL2PLLCR0_OFFSET
|
|
#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484
|
|
#undef DDR_PHY_DX8SL2DQSCTL_OFFSET
|
|
#define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C
|
|
#undef DDR_PHY_DX8SL2DXCTL2_OFFSET
|
|
#define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC
|
|
#undef DDR_PHY_DX8SL2IOCR_OFFSET
|
|
#define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0
|
|
#undef DDR_PHY_DX8SL3OSC_OFFSET
|
|
#define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0
|
|
#undef DDR_PHY_DX8SL3PLLCR0_OFFSET
|
|
#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4
|
|
#undef DDR_PHY_DX8SL3DQSCTL_OFFSET
|
|
#define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC
|
|
#undef DDR_PHY_DX8SL3DXCTL2_OFFSET
|
|
#define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC
|
|
#undef DDR_PHY_DX8SL3IOCR_OFFSET
|
|
#define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0
|
|
#undef DDR_PHY_DX8SL4OSC_OFFSET
|
|
#define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500
|
|
#undef DDR_PHY_DX8SL4PLLCR0_OFFSET
|
|
#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504
|
|
#undef DDR_PHY_DX8SL4DQSCTL_OFFSET
|
|
#define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C
|
|
#undef DDR_PHY_DX8SL4DXCTL2_OFFSET
|
|
#define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C
|
|
#undef DDR_PHY_DX8SL4IOCR_OFFSET
|
|
#define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530
|
|
#undef DDR_PHY_DX8SLBDQSCTL_OFFSET
|
|
#define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC
|
|
|
|
/*
|
|
* DDR block level reset inside of the DDR Sub System
|
|
*/
|
|
#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
|
|
#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
|
|
#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
|
|
#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F
|
|
#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3
|
|
#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U
|
|
|
|
/*
|
|
* Indicates the configuration of the device used in the system. - 00 - x4
|
|
* device - 01 - x8 device - 10 - x16 device - 11 - x32 device
|
|
*/
|
|
#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL
|
|
#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT
|
|
#undef DDRC_MSTR_DEVICE_CONFIG_MASK
|
|
#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30
|
|
#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U
|
|
|
|
/*
|
|
* Choose which registers are used. - 0 - Original registers - 1 - Shadow r
|
|
* egisters
|
|
*/
|
|
#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL
|
|
#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT
|
|
#undef DDRC_MSTR_FREQUENCY_MODE_MASK
|
|
#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29
|
|
#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U
|
|
|
|
/*
|
|
* Only present for multi-rank configurations. Each bit represents one rank
|
|
* . For two-rank configurations, only bits[25:24] are present. - 1 - popul
|
|
* ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
|
|
* ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
|
|
* Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
|
|
* k - 0011 - Two ranks - 1111 - Four ranks
|
|
*/
|
|
#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL
|
|
#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT
|
|
#undef DDRC_MSTR_ACTIVE_RANKS_MASK
|
|
#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24
|
|
#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U
|
|
|
|
/*
|
|
* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
|
|
* mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
|
|
* st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
|
|
* values are reserved. This controls the burst size used to access the SDR
|
|
* AM. This must match the burst length mode register setting in the SDRAM.
|
|
* (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
|
|
* Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
|
|
* is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
|
|
*/
|
|
#undef DDRC_MSTR_BURST_RDWR_DEFVAL
|
|
#undef DDRC_MSTR_BURST_RDWR_SHIFT
|
|
#undef DDRC_MSTR_BURST_RDWR_MASK
|
|
#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_BURST_RDWR_SHIFT 16
|
|
#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U
|
|
|
|
/*
|
|
* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
|
|
* frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
|
|
* normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
|
|
* TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
|
|
* s bit must be set to '0'.
|
|
*/
|
|
#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL
|
|
#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT
|
|
#undef DDRC_MSTR_DLL_OFF_MODE_MASK
|
|
#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15
|
|
#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U
|
|
|
|
/*
|
|
* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
|
|
* DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
|
|
* DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
|
|
* only supported when the SDRAM bus width is a multiple of 16, and quarter
|
|
* bus width mode is only supported when the SDRAM bus width is a multiple
|
|
* of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
|
|
* th refers to DQ bus width (excluding any ECC width).
|
|
*/
|
|
#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL
|
|
#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
|
|
#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK
|
|
#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12
|
|
#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U
|
|
|
|
/*
|
|
* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
|
|
* RAM in normal mode (1N). This register can be changed, only when the Con
|
|
* troller is in self-refresh mode. This signal must be set the same value
|
|
* as MR3 bit A3. Note: Geardown mode is not supported if the configuration
|
|
* parameter MEMC_CMD_RTN2IDLE is set
|
|
*/
|
|
#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL
|
|
#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT
|
|
#undef DDRC_MSTR_GEARDOWN_MODE_MASK
|
|
#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11
|
|
#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U
|
|
|
|
/*
|
|
* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
|
|
* g, all command signals (except chip select) are held for 2 clocks on the
|
|
* SDRAM bus. Chip select is asserted on the second cycle of the command N
|
|
* ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
|
|
* ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
|
|
* s set Note: 2T timing is not supported in DDR4 geardown mode.
|
|
*/
|
|
#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL
|
|
#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
|
|
#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK
|
|
#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10
|
|
#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U
|
|
|
|
/*
|
|
* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
|
|
* sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
|
|
* bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
|
|
* cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
|
|
* disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
|
|
* ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
|
|
* , and this bit must be set to '0'
|
|
*/
|
|
#undef DDRC_MSTR_BURSTCHOP_DEFVAL
|
|
#undef DDRC_MSTR_BURSTCHOP_SHIFT
|
|
#undef DDRC_MSTR_BURSTCHOP_MASK
|
|
#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_BURSTCHOP_SHIFT 9
|
|
#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U
|
|
|
|
/*
|
|
* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
|
|
* evice in use Present only in designs configured to support LPDDR4.
|
|
*/
|
|
#undef DDRC_MSTR_LPDDR4_DEFVAL
|
|
#undef DDRC_MSTR_LPDDR4_SHIFT
|
|
#undef DDRC_MSTR_LPDDR4_MASK
|
|
#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_LPDDR4_SHIFT 5
|
|
#define DDRC_MSTR_LPDDR4_MASK 0x00000020U
|
|
|
|
/*
|
|
* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
|
|
* in use Present only in designs configured to support DDR4.
|
|
*/
|
|
#undef DDRC_MSTR_DDR4_DEFVAL
|
|
#undef DDRC_MSTR_DDR4_SHIFT
|
|
#undef DDRC_MSTR_DDR4_MASK
|
|
#define DDRC_MSTR_DDR4_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_DDR4_SHIFT 4
|
|
#define DDRC_MSTR_DDR4_MASK 0x00000010U
|
|
|
|
/*
|
|
* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
|
|
* evice in use Present only in designs configured to support LPDDR3.
|
|
*/
|
|
#undef DDRC_MSTR_LPDDR3_DEFVAL
|
|
#undef DDRC_MSTR_LPDDR3_SHIFT
|
|
#undef DDRC_MSTR_LPDDR3_MASK
|
|
#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_LPDDR3_SHIFT 3
|
|
#define DDRC_MSTR_LPDDR3_MASK 0x00000008U
|
|
|
|
/*
|
|
* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
|
|
* evice in use Present only in designs configured to support LPDDR2.
|
|
*/
|
|
#undef DDRC_MSTR_LPDDR2_DEFVAL
|
|
#undef DDRC_MSTR_LPDDR2_SHIFT
|
|
#undef DDRC_MSTR_LPDDR2_MASK
|
|
#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_LPDDR2_SHIFT 2
|
|
#define DDRC_MSTR_LPDDR2_MASK 0x00000004U
|
|
|
|
/*
|
|
* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
|
|
* vice in use Only present in designs that support DDR3.
|
|
*/
|
|
#undef DDRC_MSTR_DDR3_DEFVAL
|
|
#undef DDRC_MSTR_DDR3_SHIFT
|
|
#undef DDRC_MSTR_DDR3_MASK
|
|
#define DDRC_MSTR_DDR3_DEFVAL 0x03040001
|
|
#define DDRC_MSTR_DDR3_SHIFT 0
|
|
#define DDRC_MSTR_DDR3_MASK 0x00000001U
|
|
|
|
/*
|
|
* Setting this register bit to 1 triggers a mode register read or write op
|
|
* eration. When the MR operation is complete, the uMCTL2 automatically cle
|
|
* ars this bit. The other register fields of this register must be written
|
|
* in a separate APB transaction, before setting this mr_wr bit. It is rec
|
|
* ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
|
|
* ating modes.
|
|
*/
|
|
#undef DDRC_MRCTRL0_MR_WR_DEFVAL
|
|
#undef DDRC_MRCTRL0_MR_WR_SHIFT
|
|
#undef DDRC_MRCTRL0_MR_WR_MASK
|
|
#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030
|
|
#define DDRC_MRCTRL0_MR_WR_SHIFT 31
|
|
#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U
|
|
|
|
/*
|
|
* Address of the mode register that is to be written to. - 0000 - MR0 - 00
|
|
* 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
|
|
* 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
|
|
* for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
|
|
* o used for writing to control words of RDIMMs. In that case, it correspo
|
|
* nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
|
|
* 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
|
|
* s the bit[2:0] must be set to an appropriate value which is considered b
|
|
* oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
|
|
* DIMMs.
|
|
*/
|
|
#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL
|
|
#undef DDRC_MRCTRL0_MR_ADDR_SHIFT
|
|
#undef DDRC_MRCTRL0_MR_ADDR_MASK
|
|
#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030
|
|
#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12
|
|
#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U
|
|
|
|
/*
|
|
* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
|
|
* d to access all ranks, so all bits should be set to 1. However, for mult
|
|
* i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
|
|
* ary to access ranks individually. Examples (assume uMCTL2 is configured
|
|
* for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
|
|
* 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
|
|
* ks 0, 1, 2 and 3
|
|
*/
|
|
#undef DDRC_MRCTRL0_MR_RANK_DEFVAL
|
|
#undef DDRC_MRCTRL0_MR_RANK_SHIFT
|
|
#undef DDRC_MRCTRL0_MR_RANK_MASK
|
|
#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030
|
|
#define DDRC_MRCTRL0_MR_RANK_SHIFT 4
|
|
#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U
|
|
|
|
/*
|
|
* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
|
|
* efore automatic SDRAM initialization routine or not. For DDR4, this bit
|
|
* can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
|
|
* ialization. For LPDDR4, this bit can be used to program additional mode
|
|
* registers before automatic SDRAM initialization if necessary. Note: This
|
|
* must be cleared to 0 after completing Software operation. Otherwise, SD
|
|
* RAM initialization routine will not re-start. - 0 - Software interventio
|
|
* n is not allowed - 1 - Software intervention is allowed
|
|
*/
|
|
#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL
|
|
#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT
|
|
#undef DDRC_MRCTRL0_SW_INIT_INT_MASK
|
|
#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030
|
|
#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3
|
|
#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U
|
|
|
|
/*
|
|
* Indicates whether the mode register operation is MRS in PDA mode or not
|
|
* - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
|
|
*/
|
|
#undef DDRC_MRCTRL0_PDA_EN_DEFVAL
|
|
#undef DDRC_MRCTRL0_PDA_EN_SHIFT
|
|
#undef DDRC_MRCTRL0_PDA_EN_MASK
|
|
#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030
|
|
#define DDRC_MRCTRL0_PDA_EN_SHIFT 2
|
|
#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U
|
|
|
|
/*
|
|
* Indicates whether the mode register operation is MRS or WR/RD for MPR (o
|
|
* nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
|
|
*/
|
|
#undef DDRC_MRCTRL0_MPR_EN_DEFVAL
|
|
#undef DDRC_MRCTRL0_MPR_EN_SHIFT
|
|
#undef DDRC_MRCTRL0_MPR_EN_MASK
|
|
#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030
|
|
#define DDRC_MRCTRL0_MPR_EN_SHIFT 1
|
|
#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U
|
|
|
|
/*
|
|
* Indicates whether the mode register operation is read or write. Only use
|
|
* d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
|
|
*/
|
|
#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL
|
|
#undef DDRC_MRCTRL0_MR_TYPE_SHIFT
|
|
#undef DDRC_MRCTRL0_MR_TYPE_MASK
|
|
#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030
|
|
#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0
|
|
#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U
|
|
|
|
/*
|
|
* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
|
|
* es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
|
|
* esigns configured to support LPDDR4. The required number of cycles for d
|
|
* erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
|
|
* eriod, and rounding up the next integer.
|
|
*/
|
|
#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL
|
|
#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
|
|
#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK
|
|
#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000
|
|
#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8
|
|
#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U
|
|
|
|
/*
|
|
* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
|
|
* LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
|
|
* ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
|
|
*/
|
|
#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL
|
|
#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT
|
|
#undef DDRC_DERATEEN_DERATE_BYTE_MASK
|
|
#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000
|
|
#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4
|
|
#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U
|
|
|
|
/*
|
|
* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
|
|
* y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
|
|
* LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
|
|
* ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
|
|
* 75 ns is less than a core_ddrc_core_clk period or not.
|
|
*/
|
|
#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL
|
|
#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT
|
|
#undef DDRC_DERATEEN_DERATE_VALUE_MASK
|
|
#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000
|
|
#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1
|
|
#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U
|
|
|
|
/*
|
|
* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
|
|
* g parameter derating is enabled using MR4 read value. Present only in de
|
|
* signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
|
|
* to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
|
|
*/
|
|
#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL
|
|
#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT
|
|
#undef DDRC_DERATEEN_DERATE_ENABLE_MASK
|
|
#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000
|
|
#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0
|
|
#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U
|
|
|
|
/*
|
|
* Interval between two MR4 reads, used to derate the timing parameters. Pr
|
|
* esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
|
|
* egister must not be set to zero
|
|
*/
|
|
#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
|
|
#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
|
|
#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK
|
|
#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
|
|
#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0
|
|
#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU
|
|
|
|
/*
|
|
* Self refresh state is an intermediate state to enter to Self refresh pow
|
|
* er down state or exit Self refresh power down state for LPDDR4. This reg
|
|
* ister controls transition from the Self refresh state. - 1 - Prohibit tr
|
|
* ansition from Self refresh state - 0 - Allow transition from Self refres
|
|
* h state
|
|
*/
|
|
#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL
|
|
#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
|
|
#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK
|
|
#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000
|
|
#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6
|
|
#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U
|
|
|
|
/*
|
|
* A value of 1 to this register causes system to move to Self Refresh stat
|
|
* e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
|
|
* This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
|
|
* re Entry to Self Refresh - 0 - Software Exit from Self Refresh
|
|
*/
|
|
#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL
|
|
#undef DDRC_PWRCTL_SELFREF_SW_SHIFT
|
|
#undef DDRC_PWRCTL_SELFREF_SW_MASK
|
|
#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000
|
|
#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5
|
|
#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U
|
|
|
|
/*
|
|
* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
|
|
* when the transaction store is empty. This register must be reset to '0'
|
|
* to bring uMCTL2 out of maximum power saving mode. Present only in desig
|
|
* ns configured to support DDR4. For non-DDR4, this register should not be
|
|
* set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
|
|
* the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
|
|
* equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
|
|
*/
|
|
#undef DDRC_PWRCTL_MPSM_EN_DEFVAL
|
|
#undef DDRC_PWRCTL_MPSM_EN_SHIFT
|
|
#undef DDRC_PWRCTL_MPSM_EN_MASK
|
|
#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000
|
|
#define DDRC_PWRCTL_MPSM_EN_SHIFT 4
|
|
#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U
|
|
|
|
/*
|
|
* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
|
|
* uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
|
|
* Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
|
|
* be asserted in Self Refresh. In DDR4, can be asserted in following: - i
|
|
* n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
|
|
* n be asserted in following: - in Self Refresh - in Power Down - in Deep
|
|
* Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
|
|
* rted in following: - in Self Refresh Power Down - in Power Down - during
|
|
* Normal operation (Clock Stop)
|
|
*/
|
|
#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL
|
|
#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
|
|
#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK
|
|
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000
|
|
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3
|
|
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U
|
|
|
|
/*
|
|
* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
|
|
* transaction store is empty. This register must be reset to '0' to bring
|
|
* uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
|
|
* initialization on deep power-down exit. Present only in designs configu
|
|
* red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
|
|
* DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
|
|
*/
|
|
#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL
|
|
#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
|
|
#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK
|
|
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000
|
|
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2
|
|
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U
|
|
|
|
/*
|
|
* If true then the uMCTL2 goes into power-down after a programmable number
|
|
* of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
|
|
* x32). This register bit may be re-programmed during the course of normal
|
|
* operation.
|
|
*/
|
|
#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL
|
|
#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT
|
|
#undef DDRC_PWRCTL_POWERDOWN_EN_MASK
|
|
#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000
|
|
#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1
|
|
#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U
|
|
|
|
/*
|
|
* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
|
|
* mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
|
|
* selfref_to_x32)'. This register bit may be re-programmed during the cour
|
|
* se of normal operation.
|
|
*/
|
|
#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL
|
|
#undef DDRC_PWRCTL_SELFREF_EN_SHIFT
|
|
#undef DDRC_PWRCTL_SELFREF_EN_MASK
|
|
#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000
|
|
#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0
|
|
#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U
|
|
|
|
/*
|
|
* After this many clocks of NOP or deselect the uMCTL2 automatically puts
|
|
* the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
|
|
* en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
|
|
*/
|
|
#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL
|
|
#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
|
|
#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK
|
|
#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010
|
|
#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16
|
|
#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U
|
|
|
|
/*
|
|
* Minimum deep power-down time. For mDDR, value from the JEDEC specificati
|
|
* on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
|
|
* .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
|
|
* C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
|
|
* n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
|
|
* ONLY.
|
|
*/
|
|
#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL
|
|
#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT
|
|
#undef DDRC_PWRTMG_T_DPD_X4096_MASK
|
|
#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010
|
|
#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8
|
|
#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U
|
|
|
|
/*
|
|
* After this many clocks of NOP or deselect the uMCTL2 automatically puts
|
|
* the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
|
|
* en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
|
|
*/
|
|
#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL
|
|
#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
|
|
#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK
|
|
#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010
|
|
#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0
|
|
#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU
|
|
|
|
/*
|
|
* Threshold value in number of clock cycles before the critical refresh or
|
|
* page timer expires. A critical refresh is to be issued before this thre
|
|
* shold is reached. It is recommended that this not be changed from the de
|
|
* fault value, currently shown as 0x2. It must always be less than interna
|
|
* lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
|
|
* sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
|
|
* s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
|
|
* om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
|
|
* cks.
|
|
*/
|
|
#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL
|
|
#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
|
|
#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK
|
|
#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000
|
|
#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20
|
|
#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U
|
|
|
|
/*
|
|
* If the refresh timer (tRFCnom, also known as tREFI) has expired at least
|
|
* once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
|
|
* a speculative refresh may be performed. A speculative refresh is a refr
|
|
* esh performed at a time when refresh would be useful, but before it is a
|
|
* bsolutely required. When the SDRAM bus is idle for a period of time dete
|
|
* rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
|
|
* at least once since the last refresh, then a speculative refresh is per
|
|
* formed. Speculative refreshes continues successively until there are no
|
|
* refreshes pending or until new reads or writes are issued to the uMCTL2.
|
|
* FOR PERFORMANCE ONLY.
|
|
*/
|
|
#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL
|
|
#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
|
|
#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK
|
|
#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000
|
|
#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12
|
|
#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U
|
|
|
|
/*
|
|
* The programmed value + 1 is the number of refresh timeouts that is allow
|
|
* ed to accumulate before traffic is blocked and the refreshes are forced
|
|
* to execute. Closing pages to perform a refresh is a one-time penalty tha
|
|
* t must be paid for each group of refreshes. Therefore, performing refres
|
|
* hes in a burst reduces the per-refresh penalty of these page closings. H
|
|
* igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
|
|
* lower numbers decreases the worst-case latency associated with refreshes
|
|
* . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
|
|
* For information on burst refresh feature refer to section 3.9 of DDR2 J
|
|
* EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
|
|
* r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
|
|
* I cycles using the burst refresh feature. In DDR4 mode, according to Fin
|
|
* e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
|
|
* shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
|
|
* tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
|
|
* ure that tRFCmax is not violated due to a PHY-initiated update occurring
|
|
* shortly before a refresh burst was due. In this situation, the refresh
|
|
* burst will be delayed until the PHY-initiated update is complete.
|
|
*/
|
|
#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL
|
|
#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
|
|
#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK
|
|
#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000
|
|
#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4
|
|
#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U
|
|
|
|
/*
|
|
* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
|
|
* traffic to flow to other banks. Per bank refresh is not supported by all
|
|
* LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
|
|
* esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
|
|
*/
|
|
#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL
|
|
#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
|
|
#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK
|
|
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000
|
|
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2
|
|
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U
|
|
|
|
/*
|
|
* Refresh timer start for rank 1 (only present in multi-rank configuration
|
|
* s). This is useful in staggering the refreshes to multiple ranks to help
|
|
* traffic to proceed. This is explained in Refresh Controls section of ar
|
|
* chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
|
|
*/
|
|
#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL
|
|
#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT
|
|
#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK
|
|
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000
|
|
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16
|
|
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U
|
|
|
|
/*
|
|
* Refresh timer start for rank 0 (only present in multi-rank configuration
|
|
* s). This is useful in staggering the refreshes to multiple ranks to help
|
|
* traffic to proceed. This is explained in Refresh Controls section of ar
|
|
* chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
|
|
*/
|
|
#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL
|
|
#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT
|
|
#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK
|
|
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000
|
|
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0
|
|
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU
|
|
|
|
/*
|
|
* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
|
|
* ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
|
|
* 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
|
|
* te: The on-the-fly modes is not supported in this version of the uMCTL2.
|
|
* Note: This must be set up while the Controller is in reset or while the
|
|
* Controller is in self-refresh mode. Changing this during normal operati
|
|
* on is not allowed. Making this a dynamic register will be supported in f
|
|
* uture version of the uMCTL2.
|
|
*/
|
|
#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL
|
|
#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
|
|
#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK
|
|
#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000
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#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4
|
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#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U
|
|
|
|
/*
|
|
* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
|
|
* the refresh register(s) have been updated. The value is automatically up
|
|
* dated when exiting reset, so it does not need to be toggled initially.
|
|
*/
|
|
#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL
|
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#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
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#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK
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#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000
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#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1
|
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#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U
|
|
|
|
/*
|
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* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
|
|
* h is disabled, the SoC core must generate refreshes using the registers
|
|
* reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
|
|
* nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
|
|
* , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
|
|
* CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
|
|
* isable auto-refresh is not supported, and this bit must be set to '0'. T
|
|
* his register field is changeable on the fly.
|
|
*/
|
|
#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL
|
|
#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
|
|
#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK
|
|
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000
|
|
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0
|
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#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U
|
|
|
|
/*
|
|
* tREFI: Average time interval between refreshes per rank (Specification:
|
|
* 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
|
|
* LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
|
|
* shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
|
|
* FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
|
|
* register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
|
|
* IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
|
|
* ue is different depending on the refresh mode. The user should program t
|
|
* he appropriate value from the spec based on the value programmed in the
|
|
* refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
|
|
* ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
|
|
* an 0x1. Unit: Multiples of 32 clocks.
|
|
*/
|
|
#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL
|
|
#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
|
|
#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK
|
|
#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C
|
|
#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16
|
|
#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U
|
|
|
|
/*
|
|
* Used only when LPDDR3 memory type is connected. Should only be changed w
|
|
* hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
|
|
* equired by some LPDDR3 devices which comply with earlier versions of the
|
|
* LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
|
|
* - tREFBW parameter used
|
|
*/
|
|
#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL
|
|
#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
|
|
#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK
|
|
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C
|
|
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15
|
|
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U
|
|
|
|
/*
|
|
* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
|
|
* REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
|
|
* CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
|
|
* undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
|
|
* all-bank refreshes, the tRFCmin value in the above equations is equal to
|
|
* tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
|
|
* uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
|
|
* equations is different depending on the refresh mode (fixed 1X,2X,4X) an
|
|
* d the device density. The user should program the appropriate value from
|
|
* the spec based on the 'refresh_mode' and the device density that is use
|
|
* d. Unit: Clocks.
|
|
*/
|
|
#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL
|
|
#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT
|
|
#undef DDRC_RFSHTMG_T_RFC_MIN_MASK
|
|
#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C
|
|
#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0
|
|
#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU
|
|
|
|
/*
|
|
* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
|
|
* SE_RMW is defined
|
|
*/
|
|
#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL
|
|
#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT
|
|
#undef DDRC_ECCCFG0_DIS_SCRUB_MASK
|
|
#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000
|
|
#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4
|
|
#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U
|
|
|
|
/*
|
|
* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
|
|
* er 1 beat - all other settings are reserved for future use
|
|
*/
|
|
#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL
|
|
#undef DDRC_ECCCFG0_ECC_MODE_SHIFT
|
|
#undef DDRC_ECCCFG0_ECC_MODE_MASK
|
|
#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000
|
|
#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0
|
|
#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U
|
|
|
|
/*
|
|
* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
|
|
* ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
|
|
* a_poison_en=1
|
|
*/
|
|
#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL
|
|
#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
|
|
#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK
|
|
#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000
|
|
#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1
|
|
#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U
|
|
|
|
/*
|
|
* Enable ECC data poisoning - introduces ECC errors on writes to address s
|
|
* pecified by the ECCPOISONADDR0/1 registers
|
|
*/
|
|
#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL
|
|
#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
|
|
#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK
|
|
#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000
|
|
#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0
|
|
#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U
|
|
|
|
/*
|
|
* The maximum number of DFI PHY clock cycles allowed from the assertion of
|
|
* the dfi_rddata_en signal to the assertion of each of the corresponding
|
|
* bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
|
|
* parameter tphy_rdlat. Refer to PHY specification for correct value. This
|
|
* value it only used for detecting read data timeout when DDR4 retry is e
|
|
* nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
|
|
* - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
|
|
* dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
|
|
* : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
|
|
* fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
|
|
* rdlat < 'd114 Unit: DFI Clocks
|
|
*/
|
|
#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL
|
|
#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
|
|
#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK
|
|
#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200
|
|
#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24
|
|
#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U
|
|
|
|
/*
|
|
* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
|
|
* re has an option to read the mode registers in the DRAM before the hardw
|
|
* are begins the retry process - 1: Wait for software to read/write the mo
|
|
* de registers before hardware begins the retry. After software is done wi
|
|
* th its operations, it will clear the alert interrupt register bit - 0: H
|
|
* ardware can begin the retry right away after the dfi_alert_n pulse goes
|
|
* away. The value on this register is valid only when retry is enabled (PA
|
|
* RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
|
|
* he software doesn't clear the interrupt register after handling the pari
|
|
* ty/CRC error, then the hardware will not begin the retry process and the
|
|
* system will hang. In the case of Parity/CRC error, there are two possib
|
|
* ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
|
|
* t parity' mode register bit is NOT set: the commands sent during retry a
|
|
* nd normal operation are executed without parity checking. The value in t
|
|
* he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
|
|
* parity' mode register bit is SET: Parity checking is done for commands s
|
|
* ent during retry and normal operation. If multiple errors occur before M
|
|
* R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
|
|
* t care'.
|
|
*/
|
|
#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL
|
|
#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
|
|
#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK
|
|
#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200
|
|
#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9
|
|
#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U
|
|
|
|
/*
|
|
* - 1: Enable com |