<<<
:sectnums:
==== System Configuration Information Memory (SYSINFO)

[cols="<3,<3,<4"]
[frame="topbot",grid="none"]
|=======================
| Hardware source file(s): | neorv32_sysinfo.vhd | 
| Software driver file(s): | neorv32_sysinfo.h |
| Top entity port:         | none | 
| Configuration generics:  | * | most of the top's configuration generics
| CPU interrupts:          | none | 
|=======================


**Overview**

The SYSINFO allows the application software to determine the setting of most of the <<_processor_top_entity_generics>>
that are related to processor/SoC configuration. All registers of this unit are read-only.
This device is always implemented - regardless of the actual hardware configuration. The bootloader as well
as the NEORV32 software runtime environment require information from this device (like memory layout
and default clock frequency) for correct operation.


**Register Map**

.SYSINFO register map (`struct NEORV32_SYSINFO`)
[cols="<2,<1,<7"]
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|=======================
| Address | Name [C] | Function
| `0xfffffe00` | `CLK`    | clock frequency in Hz (via top's `CLOCK_FREQUENCY` generic)
| `0xfffffe04` | `MEM[4]` | internal memory configuration (see <<_sysinfo_memory_configuration>>)
| `0xfffffe08` | `SOC`    | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
| `0xfffffe0c` | `CACHE`  | cache configuration information (see <<_sysinfo_cache_configuration>>)
|=======================


===== SYSINFO - Memory Configuration

[NOTE]
Bit fields in this register are set to all-zero if the according cache is not implemented.

.SYSINFO `MEM` Bytes
[cols="^1,<2,<7"]
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|=======================
| Byte | Name [C] | Function
| `0`  | `SYSINFO_MEM_IMEM` | _log2_(internal IMEM size in bytes), via top's `MEM_INT_IMEM_SIZE` generic
| `1`  | `SYSINFO_MEM_DMEM` | _log2_(internal DMEM size in bytes), via top's `MEM_INT_DMEM_SIZE` generic
| `2`  | -                  | _reserved_, read as zero
| `3`  | `SYSINFO_MEM_RVSG` | _log2_(reservation set size granularity in bytes), via top's `AMO_RVS_GRANULARITY` generic
|=======================


===== SYSINFO - SoC Configuration

.SYSINFO `SOC` Bits
[cols="^2,<6,<10"]
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|=======================
| Bit | Name [C] | Function
| `0`     | `SYSINFO_SOC_BOOTLOADER`     | set if the processor-internal bootloader is implemented (via top's `INT_BOOTLOADER_EN` generic)
| `1`     | `SYSINFO_SOC_MEM_EXT`        | set if the external Wishbone bus interface is implemented (via top's `MEM_EXT_EN` generic)
| `2`     | `SYSINFO_SOC_MEM_INT_IMEM`   | set if the processor-internal DMEM implemented (via top's `MEM_INT_DMEM_EN` generic)
| `3`     | `SYSINFO_SOC_MEM_INT_DMEM`   | set if the processor-internal IMEM is implemented (via top's `MEM_INT_IMEM_EN` generic)
| `4`     | `SYSINFO_SOC_MEM_EXT_ENDIAN` | set if external bus interface uses BIG-endian byte-order (via top's `MEM_EXT_BIG_ENDIAN` generic)
| `5`     | `SYSINFO_SOC_ICACHE`         | set if processor-internal instruction cache is implemented (via top's `ICACHE_EN` generic)
| `6`     | `SYSINFO_SOC_DCACHE`         | set if processor-internal data cache is implemented (via top's `DCACHE_EN` generic)
| `7`     | `SYSINFO_SOC_CLOCK_GATING`   | set if CPU clock gating is implemented (via top's `CLOCK_GATING_EN` generic)
| `11:8`  | -                            | _reserved_, read as zero
| `12`    | `SYSINFO_SOC_IO_CRC`         | set if cyclic redundancy check unit is implemented (via top's `IO_CRC_EN` generic)
| `13`    | `SYSINFO_SOC_IO_SLINK`       | set if stream link interface is implemented (via top's `IO_SLINK_EN` generic)
| `14`    | `SYSINFO_SOC_IO_DMA`         | set if direct memory access controller is implemented (via top's `IO_DMA_EN` generic)
| `15`    | `SYSINFO_SOC_IO_GPIO`        | set if the GPIO is implemented (via top's `IO_GPIO_EN` generic)
| `16`    | `SYSINFO_SOC_IO_MTIME`       | set if the MTIME is implemented (via top's `IO_MTIME_EN` generic)
| `17`    | `SYSINFO_SOC_IO_UART0`       | set if the primary UART0 is implemented (via top's `IO_UART0_EN` generic)
| `18`    | `SYSINFO_SOC_IO_SPI`         | set if the SPI is implemented (via top's `IO_SPI_EN` generic)
| `19`    | `SYSINFO_SOC_IO_TWI`         | set if the TWI is implemented (via top's `IO_TWI_EN` generic)
| `20`    | `SYSINFO_SOC_IO_PWM`         | set if the PWM is implemented (via top's `IO_PWM_NUM_CH` generic)
| `21`    | `SYSINFO_SOC_IO_WDT`         | set if the WDT is implemented (via top's `IO_WDT_EN` generic)
| `22`    | `SYSINFO_SOC_IO_CFS`         | set if the custom functions subsystem is implemented (via top's `IO_CFS_EN` generic)
| `23`    | `SYSINFO_SOC_IO_TRNG`        | set if the TRNG is implemented (via top's `IO_TRNG_EN` generic)
| `24`    | `SYSINFO_SOC_IO_SDI`         | set if the SDI is implemented (via top's `IO_SDI_EN` generic)
| `25`    | `SYSINFO_SOC_IO_UART1`       | set if the secondary UART1 is implemented (via top's `IO_UART1_EN` generic)
| `26`    | `SYSINFO_SOC_IO_NEOLED`      | set if the NEOLED is implemented (via top's `IO_NEOLED_EN` generic)
| `27`    | `SYSINFO_SOC_IO_XIRQ`        | set if the XIRQ is implemented (via top's `XIRQ_NUM_CH` generic)
| `28`    | `SYSINFO_SOC_IO_GPTMR`       | set if the GPTMR is implemented (via top's `IO_GPTMR_EN` generic)
| `29`    | `SYSINFO_SOC_XIP`            | set if the XIP module is implemented (via top's `XIP_EN` generic)
| `30`    | `SYSINFO_SOC_IO_ONEWIRE`     | set if the ONEWIRE interface is implemented (via top's `IO_ONEWIRE_EN` generic)
| `31`    | `SYSINFO_SOC_OCD`            | set if on-chip debugger is implemented (via top's `ON_CHIP_DEBUGGER_EN` generic)
|=======================


===== SYSINFO - Cache Configuration

[NOTE]
Bit fields in this register are set to all-zero if the according cache is not implemented.

.SYSINFO `CACHE` Bits
[cols="^1,<10,<10"]
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|=======================
| Bit     | Name [C] | Function
| `3:0`   | `SYSINFO_CACHE_IC_BLOCK_SIZE_3 : SYSINFO_CACHE_IC_BLOCK_SIZE_0`       | _log2_(i-cache block size in bytes), via top's `ICACHE_BLOCK_SIZE` generic
| `7:4`   | `SYSINFO_CACHE_IC_NUM_BLOCKS_3 : SYSINFO_CACHE_IC_NUM_BLOCKS_0`       | _log2_(i-cache number of cache blocks), via top's `ICACHE_NUM_BLOCKS` generic
| `11:9`  | `SYSINFO_CACHE_IC_ASSOCIATIVITY_3 : SYSINFO_CACHE_IC_ASSOCIATIVITY_0` | _log2_(i-cache associativity), via top's `ICACHE_ASSOCIATIVITY` generic
| `15:12` | `SYSINFO_CACHE_IC_REPLACEMENT_3 : SYSINFO_CACHE_IC_REPLACEMENT_0`     | i-cache replacement policy (`0001` = LRU if associativity > 0)
| `19:16` | `SYSINFO_CACHE_DC_BLOCK_SIZE_3 : SYSINFO_CACHE_DC_BLOCK_SIZE_0`       | _log2_(d-cache block size in bytes), via top's `DCACHE_BLOCK_SIZE` generic
| `23:20` | `SYSINFO_CACHE_DC_NUM_BLOCKS_3 : SYSINFO_CACHE_DC_NUM_BLOCKS_0`       | _log2_(d-cache number of cache blocks), via top's `DCACHE_NUM_BLOCKS` generic
| `27:24` | `SYSINFO_CACHE_DC_ASSOCIATIVITY_3 : SYSINFO_CACHE_DC_ASSOCIATIVITY_0` | always zero
| `31:28` | `SYSINFO_CACHE_DC_REPLACEMENT_3 : SYSINFO_CACHE_DC_REPLACEMENT_0`     | always zero
|=======================
