// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
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//  * Verilog Module Declaration Style: 2001

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// The result of translation follows.  Its copyright status should be
// considered unchanged from the original VHDL.

// #################################################################################################
// # << NEORV32 - Minimal setup without a bootloader >>                                            #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
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// #    permission.                                                                                #
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// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
// no timescale needed

module neorv32_ProcessorTop_Minimal(
input wire clk_i,
input wire rstn_i,
output wire [IO_PWM_NUM_CH - 1:0] pwm_o
);

// General --
parameter [31:0] CLOCK_FREQUENCY=0;
parameter MEM_INT_IMEM_EN=true;
parameter [31:0] MEM_INT_IMEM_SIZE=8 * 1024;
parameter MEM_INT_DMEM_EN=true;
parameter [31:0] MEM_INT_DMEM_SIZE=64 * 1024;
parameter [31:0] IO_PWM_NUM_CH=3;
// number of PWM channels to implement (0..12); 0 = disabled
// Global control --
// PWM (available if IO_PWM_NUM_CH > 0) --



// internal IO connection --
wire [11:0] con_pwm_o;

  // The core of the problem ----------------------------------------------------------------
  // -------------------------------------------------------------------------------------------
  neorv32_top #(
      // General --
    .CLOCK_FREQUENCY(CLOCK_FREQUENCY),
    // clock frequency of clk_i in Hz
    .INT_BOOTLOADER_EN(false),
    // boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
    // Internal Instruction memory --
    .MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
    // implement processor-internal instruction memory
    .MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
    // size of processor-internal instruction memory in bytes
    // Internal Data memory --
    .MEM_INT_DMEM_EN(MEM_INT_DMEM_EN),
    // implement processor-internal data memory
    .MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
    // size of processor-internal data memory in bytes
    // Processor peripherals --
    .IO_MTIME_EN(true),
    // implement machine system timer (MTIME)?
    .IO_PWM_NUM_CH(IO_PWM_NUM_CH))
  neorv32_inst(
      // Global control --
    .clk_i(clk_i),
    // global clock, rising edge
    .rstn_i(rstn_i),
    // global reset, low-active, async
    // PWM (available if IO_PWM_NUM_CH > 0) --
    .pwm_o(con_pwm_o));

  // PWM --
  assign pwm_o = con_pwm_o[IO_PWM_NUM_CH - 1:0];

endmodule
