42 lines
2.2 KiB
Plaintext
42 lines
2.2 KiB
Plaintext
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<<<
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:sectnums:
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==== Data Memory (DMEM)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_dmem.entity.vhd | entity-only definition
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| | mem/neorv32_dmem.default.vhd | default _platform-agnostic_ memory architecture
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| | mem/neorv32_dmem.legacy.vhd | alternative legacy-style memory architecture
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| Software driver file(s): | none | _implicitly used_
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| Top entity port: | none |
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| Configuration generics: | `MEM_INT_DMEM_EN` | implement processor-internal DMEM when `true`
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| | `MEM_INT_DMEM_SIZE` | DMEM size in bytes (use a power of 2)
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| CPU interrupts: | none |
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|=======================
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Implementation of the processor-internal data memory is enabled by the processor's `MEM_INT_DMEM_EN`
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generic. The total memory size in bytes is defined via the `MEM_INT_DMEM_SIZE` generic. Note that this
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size should be a power of two to optimize physical implementation. If the DMEM is implemented,
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it is mapped to base address `0x80000000` by default (see section <<_address_space>>).
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The DMEM is always implemented as true RAM.
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.Memory Size
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[IMPORTANT]
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If the configured memory size (via the `MEM_INT_IMEM_SIZE` generic) is **not** a power of two the actual memory
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size will be auto-adjusted to the next power of two (e.g. configuring a memory size of 60kB will result in a
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physical memory size of 64kB).
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.VHDL Source File
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[NOTE]
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The actual DMEM is split into two design files: a plain entity definition `neorv32_dmem.entity.vhd` and the actual
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architecture definition `mem/neorv32_dmem.default.vhd`. This **default architecture** provides a _generic_ and
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_platform independent_ memory design that infers embedded memory blocks (blockRAM). The default architecture can
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be replaced by platform-specific modules in order to use platform-specific features or to improve technology mapping
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and/or timing. A "legacy-style" memory architecture is provided in `rtl/mem` that can be used if the synthesis does
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not correctly infer blockRAMs.
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.Execute from RAM
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[TIP]
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The CPU is capable of executing code also from arbitrary data memory.
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