94 lines
5.2 KiB
Plaintext
94 lines
5.2 KiB
Plaintext
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:sectnums:
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==== General Purpose Timer (GPTMR)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_gptmr.vhd |
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| Software driver file(s): | neorv32_gptmr.c |
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| | neorv32_gptmr.h |
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| Top entity port: | `gptmr_trig_i` | timer capture input
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| Configuration generics: | `IO_GPTMR_EN` | implement general purpose timer when `true`
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| CPU interrupts: | fast IRQ channel 12 | timer interrupt (see <<_processor_interrupts>>)
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|=======================
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**Overview**
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The general purpose timer module implements a simple yet universal 32-bit timer. It is implemented if the processor's
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`IO_GPTMR_EN` top generic is set `true`. The timer provides a pre-scaled counter register that can trigger an interrupt
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when reaching a programmable threshold value. Additionally, a timer-capture feature is implemented that copies the current
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counter value to a dedicated register if a programmable edge occurs at the `gptmr_trig_i` input signal.
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Four interface registers are available: a control register (`CTRL`), a 32-bit counter register (`COUNT`), a 32-bit
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threshold register (`THRES`) and a 32-bit read-only capture register (`CAPTURE`). The timer is globally enabled by setting the
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`GPTMR_CTRL_EN` bit in the device's control register `CTRL`. When the timer is enable the `COUNT` register will start
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incrementing at a programmable rate, which scales the main processor clock. The pre-scaler value is configured via the
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three `GPTMR_CTRL_PRSCx` control register bits:
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.GPTMR prescaler configuration
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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|=======================
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| **`GPTMR_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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[NOTE]
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Disabling the timer will not clear the `COUNT` register. However, it can be manually reset at any time by
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writing zero to it.
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**Interval Timer**
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Whenever the counter register `COUNT` reaches the programmable threshold value `THRES` the counter register
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is reset to zero and the _timer-match_ flag `GPTMR_CTRL_TRIGM` gets set. This flag has to be cleared manually
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by writing zero to it. Optionally, an interrupt can be triggered if the `GPTMR_CTRL_IRQM` bit is set.
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**Timer Capture**
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In addition to the the internal timer, the GPTMR provides a timer-capture feature. Whenever an edge is detected
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at the `gptmr_trig_i` input signal the current `COUNT` value is copied to the read-only `CAPTURE` register and the
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_capture-trigger_ flag `GPTMR_CTRL_TRIGC` gets set. This flag has to be cleared manually by writing zero to it.
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Optionally, an interrupt can be triggered if the `GPTMR_CTRL_IRQC` bit is set.
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The triggering edge can be a rising-edge (if `GPTMR_CTRL_RISE` is set), a falling-edge (if `GPTMR_CTRL_FALL` is
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set) or even both. By default, the `gptmr_trig_i` is sampled two times at the processor clock for checking for
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edges. This simple edge detection is sufficient for trigger signals that are generated by (on-chip) digital logic.
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For sampling chip-external signals an optional filtering mode is available that can be enabled by the
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`GPTMR_CTRL_FILTER` bit. If this bit is set, the `gptmr_trig_i` is sampled at a reduced clock speed (1/4 of the
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processor clock) and the signal has to be stable for at lest 4 sample clock in order to be considered high or low.
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This stabilized signal is then fed to the edge detection logic.
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.Timer Interrupt
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[NOTE]
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Once triggered, the timer interrupt remains pending within the CPU until it explicitly cleared by writing zero
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to the according <<_mip>> CSR bit.
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**Register Map**
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.GPTMR register map (`struct NEORV32_GPTMR`)
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[cols="<4,<2,<4,^1,<7"]
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.10+<| `0xfffff100` .10+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag
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<|`3:1` `GPTMR_CTRL_PRSC2 : GPTMR_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
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<|`4` `GPTMR_CTRL_IRQM` ^| r/w <| Enable interrupt on timer-match
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<|`5` `GPTMR_CTRL_IRQC` ^| r/w <| Enable interrupt on capture-trigger
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<|`6` `GPTMR_CTRL_RISE` ^| r/w <| Capture on rising edge
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<|`7` `GPTMR_CTRL_FALL` ^| r/w <| Capture on falling edge
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<|`8` `GPTMR_CTRL_FILTER` ^| r/w <| Filter capture input
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<|`29:9` - ^| r/- <| _reserved_, read as zero
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<|`30` `GPTMR_CTRL_TRIGM` ^| r/c <| Timer-match has fired, cleared by writing 0
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<|`31` `GPTMR_CTRL_TRIGC` ^| r/c <| Capture-trigger has fired, cleared by writing 0
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| `0xfffff104` | `THRES` |`31:0` | r/w | Threshold value register
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| `0xfffff108` | `COUNT` |`31:0` | r/w | Counter register
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| `0xfffff10C` | `CAPTURE` |`31:0` | r/- | Capture register
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|=======================
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