141 lines
8.6 KiB
Plaintext
141 lines
8.6 KiB
Plaintext
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:sectnums:
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==== Serial Peripheral Interface Controller (SPI)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_spi.vhd |
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| Software driver file(s): | neorv32_spi.c |
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| | neorv32_spi.h |
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| Top entity port: | `spi_clk_o` | 1-bit serial clock output
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| | `spi_dat_o` | 1-bit serial data output
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| | `spi_dat_i` | 1-bit serial data input
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| | `spi_csn_o` | 8-bit dedicated chip select output (low-active)
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| Configuration generics: | `IO_SPI_EN` | implement SPI controller when `true`
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| | `IO_SPI_FIFO` | FIFO depth, has to be a power of two, min 1
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| CPU interrupts: | fast IRQ channel 6 | configurable SPI interrupt (see <<_processor_interrupts>>)
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|=======================
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**Overview**
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The NEORV32 SPI transceiver module operates on 8-bit base, supports all 4 standard clock modes
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and provides up to 8 dedicated chip select signals via the top entity's `spi_csn_o` signal.
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An receive/transmit FIFO can be configured via the `IO_SPI_FIFO` generic to support block-based
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transmissions without CPU interaction.
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The SPI module provides a single control register `CTRL` to configure the module and to check it's status
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and a single data register `DATA` for receiving/transmitting data.
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.Host-Mode Only
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[NOTE]
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The NEORV32 SPI module only supports _host mode_. Transmission are initiated only by the processor's SPI module
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and not by an external SPI module. If you are looking for a _device-mode_ serial peripheral interface (transactions
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initiated by an external host) check out the <<_serial_data_interface_controller_sdi>>.
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**Theory of Operation**
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The SPI module is enabled by setting the `SPI_CTRL_EN` bit in the `CTRL` control register. No transfer can be initiated
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and no interrupt request will be triggered if this bit is cleared. Clearing this bit will reset the module, clear
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the FIFO and terminate any transfer being in process.
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The data quantity to be transferred within a single data transmission is fixed to 8 bits. However, the
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total transmission length is left to the user: after asserting chip-select an arbitrary amount of 8-bit transmission
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can be made before de-asserting chip-select again.
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A transmission is started when writing data to the transmitter FIFO via the `DATA` register. Note that data always
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transferred MSB-first. The SPI operation is completed as soon as the `SPI_CTRL_BUSY` flag clears. Received data can
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be retrieved by reading the RX FIFO also via the `DATA` register. The control register's `SPI_CTRL_RX_AVAIL`,
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`SPI_CTRL_TX_EMPTY`, `SPI_CTRL_TX_NHALF` and `SPI_CTRL_TX_FULL` flags provide information regarding the RX/TX FIFO levels.
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The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's
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`SPI_CTRL_CS_SELx` and `SPI_CTRL_CS_EN` bits. The 3-bit `SPI_CTRL_CS_SELx` bits are used to select one out of the eight
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dedicated chip select lines. As soon as `SPI_CTRL_CS_EN` is _set_ the selected chip select line is activated (driven _low_).
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Note that disabling the SPI module via the _SPI_CTRL_EN_ bit will also deactivate any currently activated chip select line.
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**SPI Clock Configuration**
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The SPI module supports all standard SPI clock modes (0, 1, 2, 3), which are configured via the two control register bits
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`SPI_CTRL_CPHA` and `SPI_CTRL_CPOL`. The `SPI_CTRL_CPHA` bit defines the _clock phase_ and the `SPI_CTRL_CPOL`
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bit defines the _clock polarity_.
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.SPI clock modes; image from https://en.wikipedia.org/wiki/File:SPI_timing_diagram2.svg (license: (Wikimedia) https://en.wikipedia.org/wiki/Creative_Commons[Creative Commons] https://creativecommons.org/licenses/by-sa/3.0/deed.en[Attribution-Share Alike 3.0 Unported])
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image::SPI_timing_diagram2.wikimedia.png[]
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The SPI clock frequency (`spi_clk_o`) is programmed by the 3-bit `SPI_CTRL_PRSCx` clock prescaler for a coarse clock selection
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and a 4-bit clock divider `SPI_CTRL_CDIVx` for a fine clock configuration.
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The following clock prescalers (`SPI_CTRL_PRSCx`) are available:
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.SPI prescaler configuration
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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|=======================
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| **`SPI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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Based on the programmed clock configuration, the actual SPI clock frequency f~SPI~ is derived
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from the processor's main clock f~main~ according to the following equation:
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler` * (1 + `SPI_CTRL_CDIVx`))
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Hence, the maximum SPI clock is f~main~ / 4 and the lowest SPI clock is f~main~ / 131072. The SPI clock is always
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symmetric having a duty cycle of 50%.
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**High-Speed Mode**
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The SPI provides a high-speed mode to further boost the maximum SPI clock frequency. When enabled via the control
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register's `SPI_CTRL_HIGHSPEED` bit the clock prescaler configuration (`SPI_CTRL_PRSCx` bits) is overridden setting it
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to a minimal factor of 1. However, the clock speed can still be fine-tuned using the `SPI_CTRL_CDIVx` bits.
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * 1 * (1 + `SPI_CTRL_CDIVx`))
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Hence, the maximum SPI clock when in high-speed mode is f~main~ / 2.
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**SPI Interrupt**
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The SPI module provides a set of programmable interrupt conditions based on the level of the RX/TX FIFO. The different
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interrupt sources are enabled by setting the according control register's `SPI_CTRL_IRQ_*` bits. All enabled interrupt
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conditions are logically OR-ed so any enabled interrupt source will trigger the module's interrupt signal.
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Once the SPI interrupt has fired it remains pending until the actual cause of the interrupt is resolved; for
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example if just the `SPI_CTRL_IRQ_RX_AVAIL` bit is set, the interrupt will keep firing until the RX FIFO is empty again.
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Furthermore, an active SPI interrupt has to be explicitly cleared again by writing zero to the according
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<<_mip>> CSR bit.
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**Register Map**
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.SPI register map (`struct NEORV32_SPI`)
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[cols="<2,<1,<4,^1,<7"]
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.19+<| `0xfffff800` .19+<| `CTRL` <|`0` `SPI_CTRL_EN` ^| r/w <| SPI module enable
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<|`1` `SPI_CTRL_CPHA` ^| r/w <| clock phase
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<|`2` `SPI_CTRL_CPOL` ^| r/w <| clock polarity
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<|`5:3` `SPI_CTRL_CS_SEL2 : SPI_CTRL_CS_SEL0` ^| r/w <| Direct chip-select 0..7
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<|`6` `SPI_CTRL_CS_EN` ^| r/w <| Direct chip-select enable: setting `spi_csn_o(SPI_CTRL_CS_SEL)` low when set
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<|`9:7` `SPI_CTRL_PRSC2 : SPI_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
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<|`13:10` `SPI_CTRL_CDIV2 : SPI_CTRL_CDIV0` ^| r/w <| 4-bit clock divider for fine-tuning
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<|`14` `SPI_CTRL_HIGHSPEED` ^| r/w <| high-speed mode enable (overriding `SPI_CTRL_PRSC`)
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<|`15` _reserved_ ^| r/- <| reserved, read as zero
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<|`16` `SPI_CTRL_RX_AVAIL` ^| r/- <| RX FIFO data available (RX FIFO not empty)
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<|`17` `SPI_CTRL_TX_EMPTY` ^| r/- <| TX FIFO empty
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<|`18` `SPI_CTRL_TX_NHALF` ^| r/- <| TX FIFO _not_ at least half full
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<|`19` `SPI_CTRL_TX_FULL` ^| r/- <| TX FIFO full
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<|`20` `SPI_CTRL_IRQ_RX_AVAIL` ^| r/w <| Trigger IRQ if RX FIFO not empty
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<|`21` `SPI_CTRL_IRQ_TX_EMPTY` ^| r/w <| Trigger IRQ if TX FIFO empty
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<|`22` `SPI_CTRL_IRQ_TX_NHALF` ^| r/w <| Trigger IRQ if TX FIFO _not_ at least half full
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<|`26:23` `SPI_CTRL_FIFO_MSB : SPI_CTRL_FIFO_LSB` ^| r/- <| FIFO depth; log2(_IO_SPI_FIFO_)
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<|`30:27` _reserved_ ^| r/- <| reserved, read as zero
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<|`31` `SPI_CTRL_BUSY` ^| r/- <| SPI module busy when set (serial engine operation in progress and TX FIFO not empty yet)
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| `0xfffff804` | `DATA` |`7:0` | r/w | receive/transmit data (FIFO)
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|=======================
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