141 lines
7.1 KiB
Plaintext
141 lines
7.1 KiB
Plaintext
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==== Two-Wire Serial Interface Controller (TWI)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_twi.vhd |
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| Software driver file(s): | neorv32_twi.c |
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| | neorv32_twi.h |
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| Top entity port: | `twi_sda_i` | 1-bit serial data line sense input
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| | `twi_sda_o` | 1-bit serial data line output (pull low only)
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| | `twi_scl_i` | 1-bit serial clock line sense input
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| | `twi_scl_o` | 1-bit serial clock line output (pull low only)
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| Configuration generics: | `IO_TWI_EN` | implement TWI controller when `true`
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| CPU interrupts: | fast IRQ channel 7 | transmission done interrupt (see <<_processor_interrupts>>)
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|=======================
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**Overview**
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The NEORV32 TWI implements a **TWI controller**. Currently, **no multi-controller support** is available.
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Furthermore, the NEORV32 TWI unit cannot operate in peripheral mode.
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[IMPORTANT]
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The serial clock (SCL) and the serial data (SDA) lines can only be actively driven low by the
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controller. Hence, external pull-up resistors are required for these lines.
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**Tri-State Drivers**
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The TWI module requires two tri-state drivers (actually: open-drain) for the SDA and SCL lines, which have to be
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implemented in the top module of the setup. A generic VHDL example is given below (`sda` and `scl` are the actual TWI
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bus signal, which are of type `std_logic`).
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.TWI VHDL tri-state driver example
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[source,VHDL]
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----
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sda <= '0' when (twi_sda_o = '0') else 'Z'; -- drive
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scl <= '0' when (twi_scl_o = '0') else 'Z'; -- drive
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twi_sda_i <= std_ulogic(sda); -- sense
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twi_scl_i <= std_ulogic(scl); -- sense
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----
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**TWI Clock Speed**
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The TWI clock frequency is programmed by the 3-bit `TWI_CTRL_PRSCx` clock prescaler for a coarse selection
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and a 4-bit clock divider `TWI_CTRL_CDIVx` for a fine selection.
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.TWI prescaler configuration
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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|=======================
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| **`TWI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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Based on the the clock configuration, the actual TWI clock frequency f~SCL~ is derived
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from the processor's main clock f~main~ according to the following equation:
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_**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler` * (1 + TWI_CTRL_CDIV))
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Hence, the maximum TWI clock is f~main~ / 8 and the lowest TWI clock is f~main~ / 262144. The generated TWI clock is
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always symmetric having a duty cycle of exactly 50%. However, an accessed peripheral can "slow down" the bus clock
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by using **clock stretching** (= actively driving the SCL line low). The controller will pause operation in this case
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if clock stretching is enabled via the `TWI_CTRL_CSEN` bit of the unit's control register `CTRL`
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**TWI Transfers**
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The TWI is enabled via the `TWI_CTRL_EN` bit in the `CTRL` control register. The user program can start / stop a
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transmission by issuing a START or STOP condition. These conditions are generated by setting the
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according bits (`TWI_CTRL_START` or `TWI_CTRL_STOP`) in the control register.
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Data is transferred via the TWI bus by writing a byte to the `DATA` register. The written byte is send via the TWI bus
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and the received byte from the bus is also available in this register after the transmission is completed.
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The TWI operation (transmitting data or performing a START or STOP condition) is in progress as long as the
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control register's `TWI_CTRL_BUSY` bit is set.
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[TIP]
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A transmission can be terminated at any time by disabling the TWI module
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by clearing the _TWI_CTRL_EN_ control register bit. This will also reset the whole module.
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[NOTE]
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When reading data from a device, an all-one byte (`0xFF`) has to be written to TWI data register `NEORV32_TWI.DATA`
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so the accessed device can actively pull-down SDA when required.
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**TWI ACK/NACK and MACK**
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An accessed TWI peripheral has to acknowledge each transferred byte. When the `TWI_CTRL_ACK` bit is set after a
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completed transmission the accessed peripheral has send an ACKNOWLEDGE (ACK). If this bit is cleared after a completed
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transmission, the peripheral has send a_NOT-ACKNOWLEDGE (NACK).
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The NEORV32 TWI controller can also send an ACK generated by itself ("controller acknowledge / MACK") right after
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transmitting a byte by driving SDA low during the ACK time slot. Some TWI modules require this MACK to acknowledge
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certain data movement operations.
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The control register's `TWI_CTRL_MACK` bit has to be set to make the TWI module automatically generate a MACK after
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the byte transmission has been completed. If this bit is cleared, the ACK/NACK generated by the peripheral is sampled
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in this time slot instead (normal mode).
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**TWI Bus Status**
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The TWI controller can check if the TWI bus is currently claimed (SCL and SDA both low). The bus can be claimed by the
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NEORV32 TWI itself or by any other controller. Bit `TWI_CTRL_CLAIME` of the control register will be set if the bus
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is currently claimed.
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**TWI Interrupt**
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The TWI module provides a single interrupt to signal "transmission done" to the CPU. Whenever the TWI
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module completes the current transmission of one byte the interrupt is triggered. Note the the interrupt
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is **not** triggered when completing a START or STOP condition. Once triggered, the interrupt has to be
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explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
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**Register Map**
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.TWI register map (`struct NEORV32_TWI`)
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[cols="<2,<1,<4,^1,<7"]
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.10+<| `0xfffff900` .10+<| `CTRL` <|`0` `TWI_CTRL_EN` ^| r/w <| TWI enable, reset if cleared
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<|`1` `TWI_CTRL_START` ^| -/w <| generate START condition, auto-clears
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<|`2` `TWI_CTRL_STOP` ^| -/w <| generate STOP condition, auto-clears
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<|`3` `TWI_CTRL_MACK` ^| r/w <| generate controller-ACK for each transmission ("MACK")
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<|`4` `TWI_CTRL_CSEN` ^| r/w <| allow clock stretching when set
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<|`7:5` `TWI_CTRL_PRSC2 : TWI_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
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<|`11:8` `TWI_CTRL_CDIV3 : TWI_CTRL_CDIV0` ^| r/w <| 4-bit clock divider
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<|`28:12` - ^| r/- <| _reserved_, read as zero
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<|`29` `TWI_CTRL_CLAIMED` ^| r/- <| set if the TWI bus is claimed by any controller
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<|`30` `TWI_CTRL_ACK` ^| r/- <| ACK received when set, NACK received when cleared
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<|`31` `TWI_CTRL_BUSY` ^| r/- <| transfer/START/STOP in progress when set
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| `0xfffff904` | `DATA` |`7:0` | r/w | receive/transmit data
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|=======================
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