125 lines
7.2 KiB
Plaintext
125 lines
7.2 KiB
Plaintext
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<<<
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:sectnums:
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==== Processor-External Memory Interface (WISHBONE)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_wishbone.vhd |
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| Software driver file(s): | none | _implicitly used_
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| Top entity port: | `wb_tag_o` | request tag output (3-bit)
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| | `wb_adr_o` | address output (32-bit)
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| | `wb_dat_i` | data input (32-bit)
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| | `wb_dat_o` | data output (32-bit)
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| | `wb_we_o` | write enable (1-bit)
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| | `wb_sel_o` | byte enable (4-bit)
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| | `wb_stb_o` | strobe (1-bit)
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| | `wb_cyc_o` | valid cycle (1-bit)
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| | `wb_ack_i` | acknowledge (1-bit)
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| | `wb_err_i` | bus error (1-bit)
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| | `fence_o` | an executed `fence` instruction
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| | `fencei_o` | an executed `fence.i` instruction
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| Configuration generics: | `MEM_EXT_EN` | enable external memory interface when `true`
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| | `MEM_EXT_TIMEOUT` | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
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| | `MEM_EXT_PIPE_MODE` | when `false` (default): classic/standard Wishbone protocol; when `true`: pipelined Wishbone protocol
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| | `MEM_EXT_BIG_ENDIAN` | byte-order (Endianness) of external memory interface; `true`=BIG, `false`=little (default)
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| | `MEM_EXT_ASYNC_RX` | use registered RX path when `false` (default); use async/direct RX path when `true`
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| | `MEM_EXT_ASYNC_TX_` | use registered TX path when `false` (default); use async/direct TX path when `true`
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| CPU interrupts: | none |
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|=======================
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The external memory interface provides a Wishbone b4-compatible on-chip bus interface. The bus interface is
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implemented if the `MEM_EXT_EN` generic is `true`. This interface can be used to attach external memories,
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custom hardware accelerators, additional IO devices or all other kinds of IP blocks.
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The external interface is not mapped to a specific address space. Instead, all CPU memory accesses that
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do not target a specific processor-internal address region (accessing the "void"; see section <<_address_space>>)
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are redirected to the external memory interface.
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**Wishbone Bus Protocol**
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The external memory interface either uses the **standard** (also called "classic") Wishbone protocol (default) or
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**pipelined** Wishbone protocol. The protocol to be used is configured via the `MEM_EXT_PIPE_MODE` generic:
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* If `MEM_EXT_PIPE_MODE` is `false`, all bus control signals including `wb_stb_o` are active and remain stable until the
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transfer is acknowledged/terminated.
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* If `MEM_EXT_PIPE_MODE` is `true`, all bus control except `wb_stb_o` are active and remain until the transfer is
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acknowledged/terminated. In this case, `wb_stb_o` is asserted only during the very first bus clock cycle.
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.Exemplary Wishbone bus accesses using "classic" and "pipelined" protocol
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[cols="^2,^2"]
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[grid="none"]
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|=======================
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a| image::wishbone_classic_read.png[700,300]
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a| image::wishbone_pipelined_write.png[700,300]
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| **Classic** Wishbone read access | **Pipelined** Wishbone write access
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|=======================
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[WARNING]
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If the Wishbone interface is configured to operate in classic/standard mode (`MEM_EXT_PIPE_MODE` = false) a
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**sync** RX path (`MEM_EXT_ASYNC_RX` = false) is required for the inter-cycle pause. If `MEM_EXT_ASYNC_RX` is
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enabled while `MEM_EXT_PIPE_MODE` is disabled the module will automatically disable the asynchronous RX option.
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.Wishbone Specs.
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[TIP]
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A detailed description of the implemented Wishbone bus protocol and the according interface signals
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can be found in the data sheet "Wishbone B4 - WISHBONE System-on-Chip (SoC) Interconnection
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Architecture for Portable IP Cores". A copy of this document can be found in the `docs` folder of this
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project.
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**Bus Access**
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The NEORV32 Wishbone gateway does not support burst transfers yet, so there is always just a single transfer "in fly".
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Hence, the Wishbone `STALL` signal is not implemented. An accessed Wishbone device does not have to respond immediately to a bus
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request by sending an ACK. Instead, there is a _time window_ where the device has to acknowledge the transfer. This time window
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s configured by the `MEM_EXT_TIMEOUT` generic that defines the maximum time (in clock cycles) a bus access can be pending
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before it is automatically terminated with an error condition. If `MEM_EXT_TIMEOUT` is set to zero, the timeout is disabled
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and a bus access can take an arbitrary number of cycles to complete (this is not recommended!).
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When `MEM_EXT_TIMEOUT` is greater than zero, the Wishbone gateway starts an internal countdown whenever the CPU
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accesses an address via the external memory interface. If the accessed device does not acknowledge (via `wb_ack_i`)
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or terminate (via `wb_err_i`) the transfer within `MEM_EXT_TIMEOUT` clock cycles, the bus access is automatically canceled
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setting `wb_cyc_o` low again and a CPU load/store/instruction fetch bus access fault exception is raised.
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**Wishbone Tag**
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The 3-bit wishbone `wb_tag_o` signal provides additional information regarding the access type:
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* `wb_tag_o(0)`: `1` = privileged access (CPU is in machine mode); `0` = unprivileged access (CPU is not in machine mode)
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* `wb_tag_o(1)`: always zero
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* `wb_tag_o(2)`: `1` = instruction fetch access, `0` = data access
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**Endianness**
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The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
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to a big-endian memory system the external bus interface provides an Endianness configuration. The
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Endianness of the external memory interface can be configured via the `MEM_EXT_BIG_ENDIAN` generic.
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By default, the external memory interface uses little-endian byte-order.
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Application software can check the Endianness configuration of the external bus interface via the
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SYSINFO module (see section <<_system_configuration_information_memory_sysinfo>> for more information).
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**Access Latency**
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By default, the Wishbone gateway introduces two additional latency cycles: processor-outgoing (`*_o`) and
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processor-incoming (`*_i`) signals are fully registered. Thus, any access from the CPU to a processor-external devices
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via Wishbone requires 2 additional clock cycles. This can ease timing closure when using large (combinatorial) Wishbone
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interconnection networks.
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Optionally, the latency of the Wishbone gateway can be reduced by removing the input and output register stages.
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Enabling the `MEM_EXT_ASYNC_RX` option will remove the input register stage; enabling `MEM_EXT_ASYNC_TX` option will
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remove the output register stages. Each enabled option reduces access latency by 1 cycle.
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.Output Gating
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[NOTE]
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All outgoing Wishbone signals use a "gating mechanism" so they only change if there is a actual Wishbone transaction being in
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progress. This can reduce dynamic switching activity in the external bus system and also simplifies simulation-based
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inspection of the Wishbone transactions. Note that this output gating is only available if the output register buffer is not
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disabled (`MEM_EXT_ASYNC_TX` = `false`).
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