243 lines
15 KiB
VHDL
243 lines
15 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Custom Functions Subsystem (CFS) >> #
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-- # ********************************************************************************************* #
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-- # Intended for tightly-coupled, application-specific custom co-processors. This module provides #
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-- # 64x 32-bit memory-mapped interface registers, one interrupt request signal and custom IO #
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-- # conduits for processor-external or chip-external interface. #
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-- # #
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-- # NOTE: This is just an example/illustration template. Modify/replace this file to implement #
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-- # your own custom design logic. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cfs is
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generic (
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CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
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CFS_IN_SIZE : natural; -- size of CFS input conduit in bits
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CFS_OUT_SIZE : natural -- size of CFS output conduit in bits
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);
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, use as async
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t := rsp_terminate_c; -- bus response
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clkgen_en_o : out std_ulogic := '0'; -- enable clock generator
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clkgen_i : in std_ulogic_vector(7 downto 0); -- "clock" inputs
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irq_o : out std_ulogic := '0'; -- interrupt request
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cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE-1 downto 0); -- custom inputs
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cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0) := (others => '0') -- custom outputs
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);
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end neorv32_cfs;
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architecture neorv32_cfs_rtl of neorv32_cfs is
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-- default CFS interface registers --
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type cfs_regs_t is array (0 to 3) of std_ulogic_vector(31 downto 0); -- just implement 4 registers for this example
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signal cfs_reg_wr : cfs_regs_t; -- interface registers for WRITE accesses
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signal cfs_reg_rd : cfs_regs_t; -- interface registers for READ accesses
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begin
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-- CFS Generics ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- In it's default version the CFS provides three configuration generics:
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-- > CFS_IN_SIZE - configures the size (in bits) of the CFS input conduit cfs_in_i
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-- > CFS_OUT_SIZE - configures the size (in bits) of the CFS output conduit cfs_out_o
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-- > CFS_CONFIG - is a blank 32-bit generic. It is intended as a "generic conduit" to propagate
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-- custom configuration flags from the top entity down to this module.
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-- CFS IOs --------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor's top entity.
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-- These are intended as "conduits" to propagate custom signals from this module and the processor top entity.
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cfs_out_o <= (others => '0'); -- not used for this minimal example
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-- Reset System ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low.
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-- Note that rstn_i can be asserted by a processor-external reset, the on-chip debugger and also by the watchdog.
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--
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-- Most default peripheral devices of the NEORV32 do NOT use a dedicated hardware reset at all. Instead, these units are
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-- reset by writing ZERO to a specific "control register" located right at the beginning of the device's address space
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-- (so this register is cleared at first). The crt0 start-up code writes ZERO to every single address in the processor's
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-- IO space - including the CFS. Make sure that this initial clearing does not cause any unintended CFS actions.
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-- Clock System ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- The processor top unit implements a clock generator providing 8 "derived clocks".
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-- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals.
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-- clkgen_i is always synchronous to the main system clock (clk_i).
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--
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-- The following clock dividers are available:
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-- > clkgen_i(clk_div2_c) -> MAIN_CLK/2
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-- > clkgen_i(clk_div4_c) -> MAIN_CLK/4
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-- > clkgen_i(clk_div8_c) -> MAIN_CLK/8
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-- > clkgen_i(clk_div64_c) -> MAIN_CLK/64
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-- > clkgen_i(clk_div128_c) -> MAIN_CLK/128
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-- > clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
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-- > clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
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-- > clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
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--
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-- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct:
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--
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-- if (rstn_i = '0') then -- async and low-active reset (if required at all)
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-- ...
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-- elsif rising_edge(clk_i) then -- always use the main clock for all clock processes
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-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
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-- ...
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-- end if;
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-- end if;
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--
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-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example UART0) requires the clocks
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-- generated by the clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might
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-- still keep the generator activated. Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to
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-- reduce dynamic power consumption.
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clkgen_en_o <= '0'; -- not used for this minimal example
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-- Interrupt ------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1 (FIRQ1).
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-- The interrupt is triggered by a one-cycle high-level. After triggering, the interrupt appears as "pending" in the CPU's
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-- mip CSR ready to trigger execution of the according interrupt handler. It is the task of the application to programmer
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-- to enable/clear the CFS interrupt using the CPU's mie and mip registers when required.
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irq_o <= '0'; -- not used for this minimal example
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Here we are reading/writing from/to the interface registers of the module and generate the CPU access handshake (bus response).
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--
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-- The CFS provides up to 64 memory-mapped 32-bit interface registers. For instance, these could be used to provide a
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-- <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a
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-- <command register> for issuing commands and a <status register> for status information.
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--
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o
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-- signal (or even later if the module needs additional time). If no ACK is generated at all, the bus access will time out
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-- and cause a bus access fault exception. The current CPU privilege level is available via the 'priv_i' signal (0 = user mode,
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-- 1 = machine mode), which can be used to constrain access to certain registers or features to privileged software only.
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--
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-- This module also provides an optional ERROR signal to indicate a faulty access operation (for example when accessing an
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-- unused, read-only or "locked" CFS register address). This signal may only be set when the module is actually accessed
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-- and is set INSTEAD of the ACK signal. Setting the ERR signal will raise a bus access exception with a "Device Error" qualifier
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-- that can be handled by the application software. Note that the current privilege level should not be exposed to software to
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-- maintain full virtualization. Hence, CFS-based "privilege escalation" should trigger a bus access exception (e.g. by setting 'err_o').
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--
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-- Host access example: Read and write access to the interface registers + bus transfer acknowledge. This example only
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-- implements four physical r/w register (the four lowest CFS registers). The remaining addresses of the CFS are not associated
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-- with any physical registers - any access to those is simply ignored but still acknowledged. Only full-word write accesses are
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-- supported (and acknowledged) by this example. Sub-word write access will not alter any CFS register state and will cause
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-- a "bus store access" exception (with a "Device Timeout" qualifier as not ACK is generated in that case).
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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cfs_reg_wr(0) <= (others => '0');
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cfs_reg_wr(1) <= (others => '0');
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cfs_reg_wr(2) <= (others => '0');
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cfs_reg_wr(3) <= (others => '0');
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--
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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elsif rising_edge(clk_i) then -- synchronous interface for read and write accesses
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-- transfer/access acknowledge --
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bus_rsp_o.ack <= bus_req_i.stb;
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-- tie to zero if not explicitly used --
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bus_rsp_o.err <= '0';
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-- defaults --
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bus_rsp_o.data <= (others => '0'); -- the output HAS TO BE ZERO if there is no actual (read) access
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-- bus access --
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if (bus_req_i.stb = '1') then -- valid access cycle, STB is high for one cycle
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-- write access --
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if (bus_req_i.rw = '1') then
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if (bus_req_i.addr(7 downto 2) = "000000") then -- address size is fixed!
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cfs_reg_wr(0) <= bus_req_i.data;
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end if;
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if (bus_req_i.addr(7 downto 2) = "000001") then
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cfs_reg_wr(1) <= bus_req_i.data;
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end if;
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if (bus_req_i.addr(7 downto 2) = "000010") then
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cfs_reg_wr(2) <= bus_req_i.data;
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end if;
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if (bus_req_i.addr(7 downto 2) = "000011") then
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cfs_reg_wr(3) <= bus_req_i.data;
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end if;
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-- read access --
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else
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case bus_req_i.addr(7 downto 2) is -- address size is fixed!
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when "000000" => bus_rsp_o.data <= cfs_reg_rd(0);
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when "000001" => bus_rsp_o.data <= cfs_reg_rd(1);
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when "000010" => bus_rsp_o.data <= cfs_reg_rd(2);
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when "000011" => bus_rsp_o.data <= cfs_reg_rd(3);
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when others => bus_rsp_o.data <= (others => '0');
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end case;
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end if;
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end if;
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end if;
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end process bus_access;
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-- CFS Function Core ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- This is where the actual functionality can be implemented.
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-- The logic below is just a very simple example that transforms data
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-- from an input register into data in an output register.
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cfs_reg_rd(0) <= bin_to_gray_f(cfs_reg_wr(0)); -- convert binary to gray code
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cfs_reg_rd(1) <= gray_to_bin_f(cfs_reg_wr(1)); -- convert gray to binary code
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cfs_reg_rd(2) <= bit_rev_f(cfs_reg_wr(2)); -- bit reversal
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cfs_reg_rd(3) <= bswap32_f(cfs_reg_wr(3)); -- byte swap (endianness conversion)
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end neorv32_cfs_rtl;
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