79 lines
5.1 KiB
VHDL
79 lines
5.1 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Generic Clock Gating Switch >> #
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-- # ********************************************************************************************* #
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-- # This is a generic clock switch that allows to shut down the clock of certain processor #
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-- # modules in order to reduce power consumption. #
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-- # #
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-- # [NOTE] Especially for FPGA setups, it is highly recommended to replace this default module #
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-- # by a technology-/platform-specific macro or primitive (e.g. a clock mux) wrapper. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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entity neorv32_clockgate is
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port (
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clk_i : in std_ulogic; -- global clock line, always-on
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rstn_i : in std_ulogic; -- global reset line, low-active, async
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halt_i : in std_ulogic; -- shut down clock output when set
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clk_o : out std_ulogic -- switched clock output
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);
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end neorv32_clockgate;
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architecture neorv32_clockgate_rtl of neorv32_clockgate is
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signal enable : std_ulogic;
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begin
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-- Warn about Clock Gating ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert false report "[NEORV32] Clock gating enabled (using generic clock switch)." severity warning;
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-- Clock Switch ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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clock_switch: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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enable <= '1';
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elsif falling_edge(clk_i) then -- update on falling edge to avoid glitches on 'clk_o'
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enable <= not halt_i;
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end if;
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end process clock_switch;
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-- for FPGA designs better replace this by a technology-specific primitive or macro --
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clk_o <= clk_i when (enable = '1') else '0';
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end neorv32_clockgate_rtl;
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