86 lines
4.6 KiB
VHDL
86 lines
4.6 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 CPU - Co-Processor: RISC-V Conditional Operations ('Zicond') ISA Extension >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_cp_cond is
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in ctrl_bus_t; -- main control bus
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start_i : in std_ulogic; -- trigger operation
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-- data input --
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rs1_i : in std_ulogic_vector(XLEN-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(XLEN-1 downto 0); -- rf source 2
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-- result and status --
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res_o : out std_ulogic_vector(XLEN-1 downto 0); -- operation result
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valid_o : out std_ulogic -- data output valid
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);
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end neorv32_cpu_cp_cond;
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architecture neorv32_cpu_cp_cond_rtl of neorv32_cpu_cp_cond is
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signal rs2_zero, condition : std_ulogic;
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begin
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-- conditional output --
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cond_out: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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res_o <= (others => '0');
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elsif rising_edge(clk_i) then
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if (start_i = '1') and (condition = '1') then -- unit triggered and condition true
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res_o <= rs1_i;
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else
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res_o <= (others => '0');
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end if;
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end if;
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end process cond_out;
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-- condition check --
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rs2_zero <= '1' when (or_reduce_f(rs2_i) = '0') else '0';
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condition <= rs2_zero xnor ctrl_i.ir_funct3(1); -- equal zero / non equal zero
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-- processing done --
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valid_o <= start_i;
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end neorv32_cpu_cp_cond_rtl;
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