175 lines
8.5 KiB
VHDL
175 lines
8.5 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 CPU - Co-Processor: Shifter (CPU Base ISA) >> #
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-- # ********************************************************************************************* #
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-- # FAST_SHIFT_EN = false (default) : Use bit-serial shifter architecture (small but slow) #
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-- # FAST_SHIFT_EN = true : Use barrel shifter architecture (large but fast) #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_cp_shifter is
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generic (
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FAST_SHIFT_EN : boolean -- implement fast but large barrel shifter
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in ctrl_bus_t; -- main control bus
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start_i : in std_ulogic; -- trigger operation
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-- data input --
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rs1_i : in std_ulogic_vector(XLEN-1 downto 0); -- rf source 1
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shamt_i : in std_ulogic_vector(index_size_f(XLEN)-1 downto 0); -- shift amount
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-- result and status --
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res_o : out std_ulogic_vector(XLEN-1 downto 0); -- operation result
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valid_o : out std_ulogic -- data output valid
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);
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end neorv32_cpu_cp_shifter;
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architecture neorv32_cpu_cp_shifter_rtl of neorv32_cpu_cp_shifter is
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-- serial shifter --
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type shifter_t is record
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busy : std_ulogic;
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done : std_ulogic;
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done_ff : std_ulogic;
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cnt : std_ulogic_vector(index_size_f(XLEN)-1 downto 0);
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sreg : std_ulogic_vector(XLEN-1 downto 0);
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end record;
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signal shifter : shifter_t;
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-- barrel shifter --
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type bs_level_t is array (index_size_f(XLEN) downto 0) of std_ulogic_vector(XLEN-1 downto 0);
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signal bs_level : bs_level_t;
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signal bs_start : std_ulogic;
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signal bs_result : std_ulogic_vector(XLEN-1 downto 0);
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begin
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-- Serial Shifter (small but slow) --------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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serial_shifter:
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if not FAST_SHIFT_EN generate
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serial_shifter_core: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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shifter.busy <= '0';
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shifter.done_ff <= '0';
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shifter.cnt <= (others => '0');
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shifter.sreg <= (others => '0');
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elsif rising_edge(clk_i) then
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-- arbitration --
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shifter.done_ff <= shifter.busy and shifter.done;
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if (start_i = '1') then
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shifter.busy <= '1';
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elsif (shifter.done = '1') or (ctrl_i.cpu_trap = '1') then -- abort on trap
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shifter.busy <= '0';
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end if;
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-- shift register --
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if (start_i = '1') then -- trigger new operation
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shifter.cnt <= shamt_i;
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shifter.sreg <= rs1_i;
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elsif (or_reduce_f(shifter.cnt) = '1') then -- operation in progress
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
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if (ctrl_i.ir_funct3(2) = '0') then -- SLL: shift left logical
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shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
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else -- SRL: shift right logical / SRA: shift right arithmetical
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i.ir_funct12(10)) & shifter.sreg(shifter.sreg'left downto 1);
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end if;
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end if;
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end if;
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end process serial_shifter_core;
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-- shift control/output --
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shifter.done <= '1' when (or_reduce_f(shifter.cnt(shifter.cnt'left downto 1)) = '0') else '0';
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valid_o <= shifter.busy and shifter.done;
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res_o <= shifter.sreg when (shifter.done_ff = '1') else (others => '0');
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end generate; -- /serial_shifter
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-- Barrel Shifter (fast but large) --------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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barrel_shifter:
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if FAST_SHIFT_EN generate
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-- shifter core --
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barrel_shifter_core: process(rs1_i, shamt_i, ctrl_i, bs_level)
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begin
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-- input layer: convert left shifts to right shifts by bit-reversal --
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if (ctrl_i.ir_funct3(2) = '0') then -- is left shift?
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bs_level(index_size_f(XLEN)) <= bit_rev_f(rs1_i); -- reverse bit order of input operand
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else
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bs_level(index_size_f(XLEN)) <= rs1_i;
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end if;
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-- shifter array (right-shifts only) --
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for i in (index_size_f(XLEN)-1) downto 0 loop
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if (shamt_i(i) = '1') then
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bs_level(i)(XLEN-1 downto XLEN-(2**i)) <= (others => (bs_level(i+1)(XLEN-1) and ctrl_i.ir_funct12(10))); -- arithmetic/logical
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bs_level(i)((XLEN-(2**i))-1 downto 0) <= bs_level(i+1)(XLEN-1 downto 2**i);
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else
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bs_level(i) <= bs_level(i+1);
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end if;
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end loop;
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end process barrel_shifter_core;
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-- pipeline register --
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barrel_shifter_buf: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bs_start <= '0';
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bs_result <= (others => '0');
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elsif rising_edge(clk_i) then -- this register stage can be moved by the register balancing
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bs_start <= start_i;
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bs_result <= bs_level(0);
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end if;
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end process barrel_shifter_buf;
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-- output layer: output gate and re-convert original left shifts --
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res_o <= (others => '0') when (bs_start = '0') else
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bit_rev_f(bs_result) when (ctrl_i.ir_funct3(2) = '0') else
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bs_result;
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-- processing done --
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valid_o <= start_i;
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end generate; -- /barrel_shifter
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end neorv32_cpu_cp_shifter_rtl;
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