236 lines
11 KiB
VHDL
236 lines
11 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 CPU - Load/Store Unit >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_lsu is
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generic (
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AMO_LRSC_ENABLE : boolean -- enable atomic LR/SC operations
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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ctrl_i : in ctrl_bus_t; -- main control bus
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-- cpu data access interface --
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addr_i : in std_ulogic_vector(XLEN-1 downto 0); -- access address
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wdata_i : in std_ulogic_vector(XLEN-1 downto 0); -- write data
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rdata_o : out std_ulogic_vector(XLEN-1 downto 0); -- read data
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mar_o : out std_ulogic_vector(XLEN-1 downto 0); -- current memory address register
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wait_o : out std_ulogic; -- wait for access to complete
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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pmp_fault_i : in std_ulogic; -- PMP read/write access fault
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-- data bus --
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bus_req_o : out bus_req_t; -- request
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bus_rsp_i : in bus_rsp_t -- response
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);
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end neorv32_cpu_lsu;
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architecture neorv32_cpu_lsu_rtl of neorv32_cpu_lsu is
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signal mar : std_ulogic_vector(XLEN-1 downto 0); -- memory address register
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signal misaligned : std_ulogic; -- misaligned address
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signal arbiter_req : std_ulogic; -- pending bus request
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signal arbiter_err : std_ulogic; -- access error
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begin
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-- Access Address -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_addr_reg: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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mar <= (others => '0');
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misaligned <= '0';
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elsif rising_edge(clk_i) then
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if (ctrl_i.lsu_mo_we = '1') then
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mar <= addr_i; -- memory address register
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case ctrl_i.ir_funct3(1 downto 0) is -- alignment check
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when "00" => misaligned <= '0'; -- byte
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when "01" => misaligned <= addr_i(0); -- half-word
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when others => misaligned <= addr_i(1) or addr_i(0); -- word
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end case;
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end if;
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end if;
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end process mem_addr_reg;
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-- address output --
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bus_req_o.addr <= mar;
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mar_o <= mar; -- for MTVAL CSR
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-- Access Type ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_type_reg: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_req_o.rw <= '0';
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bus_req_o.priv <= '0';
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bus_req_o.rvso <= '0';
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elsif rising_edge(clk_i) then
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if (ctrl_i.lsu_mo_we = '1') then
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-- read/write --
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bus_req_o.rw <= ctrl_i.lsu_rw;
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-- privilege level --
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bus_req_o.priv <= ctrl_i.lsu_priv;
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-- reservation set operation --
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if (AMO_LRSC_ENABLE = true) and (ctrl_i.ir_opcode(2) = opcode_amo_c(2)) then
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bus_req_o.rvso <= '1';
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else
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bus_req_o.rvso <= '0';
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end if;
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end if;
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end if;
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end process mem_type_reg;
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-- source identifier --
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bus_req_o.src <= '0'; -- 0 = data access
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-- data/instruction fence(.i)
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bus_req_o.fence <= ctrl_i.lsu_fence; -- this is valid even without STB being set
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-- Data Output - Alignment and Byte Enable ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_do_reg: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_req_o.data <= (others => '0');
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bus_req_o.ben <= (others => '0');
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elsif rising_edge(clk_i) then
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if (ctrl_i.lsu_mo_we = '1') then
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case ctrl_i.ir_funct3(1 downto 0) is
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when "00" => -- byte
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bus_req_o.data(07 downto 00) <= wdata_i(7 downto 0);
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bus_req_o.data(15 downto 08) <= wdata_i(7 downto 0);
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bus_req_o.data(23 downto 16) <= wdata_i(7 downto 0);
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bus_req_o.data(31 downto 24) <= wdata_i(7 downto 0);
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bus_req_o.ben <= (others => '0');
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bus_req_o.ben(to_integer(unsigned(addr_i(1 downto 0)))) <= '1';
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when "01" => -- half-word
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bus_req_o.data(15 downto 00) <= wdata_i(15 downto 0);
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bus_req_o.data(31 downto 16) <= wdata_i(15 downto 0);
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if (addr_i(1) = '0') then
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bus_req_o.ben <= "0011"; -- low half-word
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else
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bus_req_o.ben <= "1100"; -- high half-word
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end if;
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when others => -- word
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bus_req_o.data <= wdata_i;
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bus_req_o.ben <= "1111";
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end case;
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end if;
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end if;
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end process mem_do_reg;
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-- Data Input - Alignment and Sign-Extension ----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_di_reg: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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rdata_o <= (others => '0');
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elsif rising_edge(clk_i) then
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if (arbiter_req = '1') then -- pending request
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case ctrl_i.ir_funct3(1 downto 0) is
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when "00" => -- byte
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case mar(1 downto 0) is
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when "00" => -- byte 0
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rdata_o(7 downto 0) <= bus_rsp_i.data(07 downto 00);
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rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(07))); -- sign-ext
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when "01" => -- byte 1
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rdata_o(7 downto 0) <= bus_rsp_i.data(15 downto 08);
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rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(15))); -- sign-ext
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when "10" => -- byte 2
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rdata_o(7 downto 0) <= bus_rsp_i.data(23 downto 16);
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rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(23))); -- sign-ext
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when others => -- byte 3
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rdata_o(7 downto 0) <= bus_rsp_i.data(31 downto 24);
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rdata_o(XLEN-1 downto 8) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(31))); -- sign-ext
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end case;
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when "01" => -- half-word
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if (mar(1) = '0') then -- low half-word
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rdata_o(15 downto 0) <= bus_rsp_i.data(15 downto 00);
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rdata_o(XLEN-1 downto 16) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(15))); -- sign-ext
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else -- high half-word
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rdata_o(15 downto 0) <= bus_rsp_i.data(31 downto 16);
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rdata_o(XLEN-1 downto 16) <= (others => ((not ctrl_i.ir_funct3(2)) and bus_rsp_i.data(31))); -- sign-ext
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end if;
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when others => -- word
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rdata_o(XLEN-1 downto 0) <= bus_rsp_i.data(XLEN-1 downto 0);
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end case;
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end if;
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end if;
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end process mem_di_reg;
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-- Access Arbiter -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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access_arbiter: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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arbiter_err <= '0';
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arbiter_req <= '0';
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elsif rising_edge(clk_i) then
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arbiter_err <= bus_rsp_i.err or pmp_fault_i; -- buffer stage
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if (arbiter_req = '0') then -- idle
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arbiter_req <= ctrl_i.lsu_req;
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elsif (bus_rsp_i.ack = '1') or (ctrl_i.cpu_trap = '1') then -- normal termination or start of trap handling
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arbiter_req <= '0';
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end if;
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end if;
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end process access_arbiter;
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-- wait for bus response --
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wait_o <= not bus_rsp_i.ack;
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-- output access/alignment errors to control unit --
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ma_load_o <= arbiter_req and (not ctrl_i.lsu_rw) and misaligned;
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be_load_o <= arbiter_req and (not ctrl_i.lsu_rw) and arbiter_err;
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ma_store_o <= arbiter_req and ( ctrl_i.lsu_rw) and misaligned;
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be_store_o <= arbiter_req and ( ctrl_i.lsu_rw) and arbiter_err;
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-- access request (all source signals are driven by registers) --
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bus_req_o.stb <= ctrl_i.lsu_req and (not misaligned) and (not pmp_fault_i);
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end neorv32_cpu_lsu_rtl;
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