52 lines
3.6 KiB
VHDL
52 lines
3.6 KiB
VHDL
|
-- #################################################################################################
|
||
|
|
-- # << NEORV32 - Processor-Internal Data Memory (DMEM) - Entity-Only >> #
|
||
|
|
-- # ********************************************************************************************* #
|
||
|
|
-- # BSD 3-Clause License #
|
||
|
|
-- # #
|
||
|
|
-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
|
||
|
|
-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
|
||
|
|
-- # #
|
||
|
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||
|
|
-- # permitted provided that the following conditions are met: #
|
||
|
|
-- # #
|
||
|
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||
|
|
-- # conditions and the following disclaimer. #
|
||
|
|
-- # #
|
||
|
|
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||
|
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||
|
|
-- # provided with the distribution. #
|
||
|
|
-- # #
|
||
|
|
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||
|
|
-- # endorse or promote products derived from this software without specific prior written #
|
||
|
|
-- # permission. #
|
||
|
|
-- # #
|
||
|
|
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||
|
|
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||
|
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||
|
|
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||
|
|
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||
|
|
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||
|
|
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||
|
|
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||
|
|
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||
|
|
-- #################################################################################################
|
||
|
|
|
||
|
|
library ieee;
|
||
|
|
use ieee.std_logic_1164.all;
|
||
|
|
use ieee.numeric_std.all;
|
||
|
|
|
||
|
|
library neorv32;
|
||
|
|
use neorv32.neorv32_package.all;
|
||
|
|
|
||
|
|
entity neorv32_dmem is
|
||
|
|
generic (
|
||
|
|
DMEM_SIZE : natural -- processor-internal instruction memory size in bytes, has to be a power of 2
|
||
|
|
);
|
||
|
|
port (
|
||
|
|
clk_i : in std_ulogic; -- global clock line
|
||
|
|
rstn_i : in std_ulogic; -- async reset, low-active
|
||
|
|
bus_req_i : in bus_req_t; -- bus request
|
||
|
|
bus_rsp_o : out bus_rsp_t -- bus response
|
||
|
|
);
|
||
|
|
end neorv32_dmem;
|