292 lines
13 KiB
VHDL
292 lines
13 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - General Purpose Timer (GPTMR) >> #
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-- # ********************************************************************************************* #
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-- # 32-bit timer with configurable clock prescaler, timer-threshold match and timer-capture #
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-- # features. An interrupt can be triggered if the counter reaches a programmable threshold or if #
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-- # a programmable edge is detects at the capture input. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_gptmr is
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(7 downto 0);
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irq_o : out std_ulogic; -- timer match interrupt
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capture_i : in std_ulogic -- capture input
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);
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end neorv32_gptmr;
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architecture neorv32_gptmr_rtl of neorv32_gptmr is
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-- control register --
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constant ctrl_en_c : natural := 0; -- r/w: GPTMR enable
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constant ctrl_prsc0_c : natural := 1; -- r/w: clock prescaler select bit 0
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constant ctrl_prsc1_c : natural := 2; -- r/w: clock prescaler select bit 1
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constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler select bit 2
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constant ctrl_irqm_c : natural := 4; -- r/w: enable interrupt on timer match
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constant ctrl_irqc_c : natural := 5; -- r/w: enable interrupt on capture trigger
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constant ctrl_rise_c : natural := 6; -- r/w: capture on rising edge
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constant ctrl_fall_c : natural := 7; -- r/w: capture on falling edge
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constant ctrl_filter_c : natural := 8; -- r/w: filter capture input signal
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--
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constant ctrl_trigm_c : natural := 30; -- r/c: timer-match has fired, cleared by writing 0
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constant ctrl_trigc_c : natural := 31; -- r/c: capture-trigger has fired, cleared by writing 0
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--
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signal ctrl : std_ulogic_vector(8 downto 0);
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-- trigger flags --
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signal trig_match, trig_capture : std_ulogic;
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-- timer core --
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type timer_t is record
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count : std_ulogic_vector(31 downto 0); -- counter register
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thres : std_ulogic_vector(31 downto 0); -- threshold register
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tick : std_ulogic; -- clock generator tick
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match : std_ulogic; -- count == thres
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match_ff : std_ulogic;
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trigger : std_ulogic; -- match trigger (single-shot)
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cnt_we : std_ulogic; -- write access to count register
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end record;
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signal timer : timer_t;
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-- sampling and capture logic --
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type capture_t is record
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sync : std_ulogic_vector(1 downto 0); -- synchronizer (prevent metastability)
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sreg : std_ulogic_vector(3 downto 0); -- input sampling
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state : std_ulogic_vector(1 downto 0); -- state buffer to detect edges
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count : std_ulogic_vector(31 downto 0); -- capture register
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trigger : std_ulogic; -- edge detector has been triggered
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rising : std_ulogic; -- rising-edge detector
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falling : std_ulogic; -- falling-edge detector
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end record;
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signal capture : capture_t;
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begin
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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ctrl <= (others => '0');
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trig_match <= '0';
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trig_capture <= '0';
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timer.cnt_we <= '0';
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timer.thres <= (others => '0');
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elsif rising_edge(clk_i) then
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-- defaults --
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bus_rsp_o.ack <= bus_req_i.stb;
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bus_rsp_o.err <= '0'; -- no access error possible
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bus_rsp_o.data <= (others => '0');
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timer.cnt_we <= '0';
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-- trigger flags --
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trig_match <= ctrl(ctrl_en_c) and (trig_match or timer.trigger);
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trig_capture <= ctrl(ctrl_en_c) and (trig_capture or capture.trigger);
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-- actual bus access --
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if (bus_req_i.stb = '1') then
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-- write access --
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if (bus_req_i.rw = '1') then
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if (bus_req_i.addr(3 downto 2) = "00") then -- control register
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ctrl(ctrl_en_c) <= bus_req_i.data(ctrl_en_c);
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ctrl(ctrl_prsc0_c) <= bus_req_i.data(ctrl_prsc0_c);
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ctrl(ctrl_prsc1_c) <= bus_req_i.data(ctrl_prsc1_c);
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ctrl(ctrl_prsc2_c) <= bus_req_i.data(ctrl_prsc2_c);
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ctrl(ctrl_irqm_c) <= bus_req_i.data(ctrl_irqm_c);
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ctrl(ctrl_irqc_c) <= bus_req_i.data(ctrl_irqc_c);
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ctrl(ctrl_rise_c) <= bus_req_i.data(ctrl_rise_c);
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ctrl(ctrl_fall_c) <= bus_req_i.data(ctrl_fall_c);
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ctrl(ctrl_filter_c) <= bus_req_i.data(ctrl_filter_c);
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if (bus_req_i.data(ctrl_trigm_c) = '0') then -- clear by writing zero
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trig_match <= '0';
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end if;
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if (bus_req_i.data(ctrl_trigc_c) = '0') then -- clear by writing zero
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trig_capture <= '0';
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end if;
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end if;
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if (bus_req_i.addr(3 downto 2) = "01") then -- threshold register
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timer.thres <= bus_req_i.data;
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end if;
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if (bus_req_i.addr(3 downto 2) = "10") then -- counter register
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timer.cnt_we <= '1';
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end if;
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-- read access --
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else
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case bus_req_i.addr(3 downto 2) is
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when "00" => -- control register
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bus_rsp_o.data(ctrl_en_c) <= ctrl(ctrl_en_c);
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bus_rsp_o.data(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
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bus_rsp_o.data(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
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bus_rsp_o.data(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
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bus_rsp_o.data(ctrl_irqm_c) <= ctrl(ctrl_irqm_c);
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bus_rsp_o.data(ctrl_irqc_c) <= ctrl(ctrl_irqc_c);
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bus_rsp_o.data(ctrl_rise_c) <= ctrl(ctrl_rise_c);
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bus_rsp_o.data(ctrl_fall_c) <= ctrl(ctrl_fall_c);
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bus_rsp_o.data(ctrl_filter_c) <= ctrl(ctrl_filter_c);
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--
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bus_rsp_o.data(ctrl_trigm_c) <= trig_match;
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bus_rsp_o.data(ctrl_trigc_c) <= trig_capture;
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when "01" => -- threshold register
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bus_rsp_o.data <= timer.thres;
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when "10" => -- counter register
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bus_rsp_o.data <= timer.count;
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when others => -- capture register
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bus_rsp_o.data <= capture.count;
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end case;
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end if;
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end if;
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end if;
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end process bus_access;
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-- Timer Core -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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counter_core: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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timer.count <= (others => '0');
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timer.match_ff <= '0';
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elsif rising_edge(clk_i) then
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if (timer.cnt_we = '1') then -- write access
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timer.count <= bus_req_i.data; -- data_i will remain stable for at least 1 cycle after WREN has returned to low
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elsif (ctrl(ctrl_en_c) = '1') and (timer.tick = '1') then -- enabled and clock tick
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if (timer.match = '1') then -- timer-match
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timer.count <= (others => '0');
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else
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timer.count <= std_ulogic_vector(unsigned(timer.count) + 1);
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end if;
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end if;
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timer.match_ff <= timer.match;
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end if;
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end process counter_core;
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-- counter = threshold? --
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timer.match <= '1' when (timer.count = timer.thres) else '0';
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-- match edge detector --
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timer.trigger <= '1' when (timer.match_ff = '0') and (timer.match = '1') else '0';
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-- clock select --
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clock_select: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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timer.tick <= '0';
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elsif rising_edge(clk_i) then
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timer.tick <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c))));
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end if;
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end process clock_select;
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-- clock generator enable --
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clkgen_en_o <= ctrl(ctrl_en_c);
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-- Capture Control ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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signal_capture: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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capture.sync <= (others => '0');
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capture.sreg <= (others => '0');
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capture.state <= (others => '0');
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capture.count <= (others => '0');
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elsif rising_edge(clk_i) then
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-- synchronizer - prevent metastability --
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capture.sync <= capture.sync(0) & capture_i;
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-- sample shift register, running at reduced sample rate --
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if (clkgen_i(clk_div4_c) = '1') then
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capture.sreg <= capture.sreg(2 downto 0) & capture.sync(1);
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end if;
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-- sample state buffer --
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capture.state(1) <= capture.state(0);
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if (ctrl(ctrl_filter_c) = '0') then -- no filter, use synchronized input
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capture.state(0) <= capture.sync(1);
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else -- active filter: change state only if input is stable for 4 sample clocks
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if (capture.sreg = "1111") then
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capture.state(0) <= '1';
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elsif (capture.sreg = "0000") then
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capture.state(0) <= '0';
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else
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capture.state(0) <= capture.state(0);
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end if;
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end if;
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-- timer capture --
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if (ctrl(ctrl_en_c) = '1') and (capture.trigger = '1') then
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capture.count <= timer.count;
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end if;
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end if;
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end process signal_capture;
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-- edge detectors --
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capture.rising <= '1' when (capture.state = "01") else '0';
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capture.falling <= '1' when (capture.state = "10") else '0';
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-- capture trigger --
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capture.trigger <= (ctrl(ctrl_rise_c) and capture.rising) or -- rising-edge trigger
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(ctrl(ctrl_fall_c) and capture.falling); -- falling-edge trigger
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-- Interrupt Generator --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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irq_generator: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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irq_o <= '0';
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elsif rising_edge(clk_i) then
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irq_o <= ctrl(ctrl_en_c) and
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((ctrl(ctrl_irqm_c) and timer.trigger) or -- timer-match interrupt
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(ctrl(ctrl_irqc_c) and capture.trigger)); -- capture interrupt
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end if;
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end process irq_generator;
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end neorv32_gptmr_rtl;
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