161 lines
7.9 KiB
VHDL
161 lines
7.9 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Machine System Timer (MTIME) >> #
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-- # ********************************************************************************************* #
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-- # Compatible to RISC-V spec's 64-bit MACHINE system timer including "mtime[h]" & "mtimecmp[h]". #
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-- # Note: The 64-bit counter and compare systems are de-coupled into two 32-bit systems. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_mtime is
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, async
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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time_o : out std_ulogic_vector(63 downto 0); -- current system time
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irq_o : out std_ulogic -- interrupt request
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);
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end neorv32_mtime;
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architecture neorv32_mtime_rtl of neorv32_mtime is
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-- mtime.time write access buffer --
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signal mtime_we : std_ulogic_vector(1 downto 0);
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-- accessible regs --
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signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtime_lo : std_ulogic_vector(31 downto 0);
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signal mtime_lo_nxt : std_ulogic_vector(32 downto 0);
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signal mtime_lo_cry : std_ulogic_vector(00 downto 0);
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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-- comparators --
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signal cmp_lo_ge, cmp_lo_ge_ff, cmp_hi_eq, cmp_hi_gt : std_ulogic;
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begin
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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mtimecmp_lo <= (others => '0');
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mtimecmp_hi <= (others => '0');
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mtime_we <= (others => '0');
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mtime_lo <= (others => '0');
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mtime_lo_cry <= (others => '0');
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mtime_hi <= (others => '0');
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--
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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elsif rising_edge(clk_i) then
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-- mtimecmp --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(3) = '1') then
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if (bus_req_i.addr(2) = '0') then
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mtimecmp_lo <= bus_req_i.data;
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else
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mtimecmp_hi <= bus_req_i.data;
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end if;
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end if;
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-- mtime write access buffer --
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mtime_we(0) <= bus_req_i.stb and bus_req_i.rw and (not bus_req_i.addr(3)) and (not bus_req_i.addr(2));
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mtime_we(1) <= bus_req_i.stb and bus_req_i.rw and (not bus_req_i.addr(3)) and ( bus_req_i.addr(2));
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-- mtime.low --
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if (mtime_we(0) = '1') then -- write access
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mtime_lo <= bus_req_i.data;
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else -- auto increment
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mtime_lo <= mtime_lo_nxt(31 downto 0);
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end if;
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-- low-to-high carry --
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mtime_lo_cry(0) <= mtime_lo_nxt(32);
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-- mtime.high --
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if (mtime_we(1) = '1') then -- write access
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mtime_hi <= bus_req_i.data;
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else -- auto increment (if mtime.low overflows)
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + unsigned(mtime_lo_cry));
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end if;
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-- read access --
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bus_rsp_o.ack <= bus_req_i.stb; -- bus handshake
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bus_rsp_o.err <= '0'; -- no access errors
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bus_rsp_o.data <= (others => '0'); -- default
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '0') then
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case bus_req_i.addr(3 downto 2) is
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when "00" => bus_rsp_o.data <= mtime_lo;
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when "01" => bus_rsp_o.data <= mtime_hi;
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when "10" => bus_rsp_o.data <= mtimecmp_lo;
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when others => bus_rsp_o.data <= mtimecmp_hi;
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end case;
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end if;
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end if;
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end process bus_access;
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-- mtime.time_LO increment --
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mtime_lo_nxt <= std_ulogic_vector(unsigned('0' & mtime_lo) + 1);
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-- system time output --
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time_o <= mtime_hi & mtime_lo; -- NOTE: low and high words are not synchronized here!
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-- Comparator -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_sync: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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cmp_lo_ge_ff <= '0';
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irq_o <= '0';
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elsif rising_edge(clk_i) then
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cmp_lo_ge_ff <= cmp_lo_ge; -- there is one cycle delay between low (earlier) and high (later) word
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irq_o <= cmp_hi_gt or (cmp_hi_eq and cmp_lo_ge_ff);
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end if;
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end process cmp_sync;
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-- sub-word comparators --
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cmp_lo_ge <= '1' when (unsigned(mtime_lo) >= unsigned(mtimecmp_lo)) else '0'; -- low-word: greater than or equal
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cmp_hi_eq <= '1' when (unsigned(mtime_hi) = unsigned(mtimecmp_hi)) else '0'; -- high-word: equal
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cmp_hi_gt <= '1' when (unsigned(mtime_hi) > unsigned(mtimecmp_hi)) else '0'; -- high-word: greater than
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end neorv32_mtime_rtl;
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