358 lines
17 KiB
VHDL
358 lines
17 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - 1-Wire Interface Host Controller (ONEWIRE) >> #
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-- # ********************************************************************************************* #
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-- # Single-wire bus controller, compatible to the "Dallas 1-Wire Bus System". #
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-- # Provides three basic operations: #
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-- # * generate reset pulse and check for device presence #
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-- # * transfer single bit (read-while-write) #
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-- # * transfer full byte (read-while-write) #
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-- # After completing any of the operations the interrupt signal is triggered. #
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-- # The base time for bus interactions is configured using a 2-bit clock prescaler and a 8-bit #
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-- # clock divider. All bus operations are timed using (hardwired) multiples of this base time. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_onewire is
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(7 downto 0);
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onewire_i : in std_ulogic; -- 1-wire line state
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onewire_o : out std_ulogic; -- 1-wire line pull-down
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irq_o : out std_ulogic -- transfer done IRQ
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);
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end neorv32_onewire;
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architecture neorv32_onewire_rtl of neorv32_onewire is
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-- timing configuration (absolute time in multiples of the base tick time t_base) --
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constant t_write_one_c : unsigned(6 downto 0) := to_unsigned( 1, 7); -- t0
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constant t_read_sample_c : unsigned(6 downto 0) := to_unsigned( 2, 7); -- t1
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constant t_slot_end_c : unsigned(6 downto 0) := to_unsigned( 7, 7); -- t2
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constant t_pause_end_c : unsigned(6 downto 0) := to_unsigned( 9, 7); -- t3
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constant t_reset_end_c : unsigned(6 downto 0) := to_unsigned(48, 7); -- t4
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constant t_presence_sample_c : unsigned(6 downto 0) := to_unsigned(55, 7); -- t5
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constant t_presence_end_c : unsigned(6 downto 0) := to_unsigned(96, 7); -- t6
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-- -> see data sheet for more information about the t* timing values --
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-- control register --
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constant ctrl_en_c : natural := 0; -- r/w: TWI enable
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constant ctrl_prsc0_c : natural := 1; -- r/w: prescaler select bit 0
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constant ctrl_prsc1_c : natural := 2; -- r/w: prescaler select bit 1
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constant ctrl_clkdiv0_c : natural := 3; -- r/w: clock divider bit 0
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constant ctrl_clkdiv1_c : natural := 4; -- r/w: clock divider bit 1
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constant ctrl_clkdiv2_c : natural := 5; -- r/w: clock divider bit 2
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constant ctrl_clkdiv3_c : natural := 6; -- r/w: clock divider bit 3
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constant ctrl_clkdiv4_c : natural := 7; -- r/w: clock divider bit 4
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constant ctrl_clkdiv5_c : natural := 8; -- r/w: clock divider bit 5
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constant ctrl_clkdiv6_c : natural := 9; -- r/w: clock divider bit 6
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constant ctrl_clkdiv7_c : natural := 10; -- r/w: clock divider bit 7
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constant ctrl_trig_rst_c : natural := 11; -- -/w: trigger reset pulse, auto-clears
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constant ctrl_trig_bit_c : natural := 12; -- -/w: trigger single-bit transmission, auto-clears
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constant ctrl_trig_byte_c : natural := 13; -- -/w: trigger full-byte transmission, auto-clears
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--
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constant ctrl_sense_c : natural := 29; -- r/-: current state of the bus line
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constant ctrl_presence_c : natural := 30; -- r/-: bus presence detected
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constant ctrl_busy_c : natural := 31; -- r/-: set while operation in progress
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-- control register --
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type ctrl_t is record
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enable : std_ulogic;
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clk_prsc : std_ulogic_vector(1 downto 0);
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clk_div : std_ulogic_vector(7 downto 0);
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trig_rst : std_ulogic;
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trig_bit : std_ulogic;
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trig_byte : std_ulogic;
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end record;
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signal ctrl : ctrl_t;
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-- write data --
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signal tx_data : std_ulogic_vector(7 downto 0);
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-- clock generator --
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signal clk_sel : std_ulogic_vector(3 downto 0);
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signal clk_tick : std_ulogic;
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signal clk_cnt : unsigned(7 downto 0);
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-- serial engine --
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type serial_t is record
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state : std_ulogic_vector(2 downto 0);
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busy : std_ulogic;
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bit_cnt : unsigned(2 downto 0);
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tick_cnt : unsigned(6 downto 0);
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tick : std_ulogic;
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tick_ff : std_ulogic;
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sreg : std_ulogic_vector(7 downto 0);
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done : std_ulogic;
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wire_in : std_ulogic_vector(1 downto 0);
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wire_lo : std_ulogic;
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wire_hi : std_ulogic;
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sample : std_ulogic;
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presence : std_ulogic;
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end record;
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signal serial : serial_t;
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begin
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-- Bus Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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ctrl.enable <= '0';
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ctrl.clk_prsc <= (others => '0');
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ctrl.clk_div <= (others => '0');
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ctrl.trig_rst <= '0';
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ctrl.trig_bit <= '0';
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ctrl.trig_byte <= '0';
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tx_data <= (others => '0');
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elsif rising_edge(clk_i) then
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-- bus handshake --
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bus_rsp_o.ack <= bus_req_i.stb;
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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-- write access --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
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-- control register --
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if (bus_req_i.addr(2) = '0') then
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ctrl.enable <= bus_req_i.data(ctrl_en_c);
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ctrl.clk_prsc <= bus_req_i.data(ctrl_prsc1_c downto ctrl_prsc0_c);
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ctrl.clk_div <= bus_req_i.data(ctrl_clkdiv7_c downto ctrl_clkdiv0_c);
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end if;
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-- data register --
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if (bus_req_i.addr(2) = '1') then
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tx_data <= bus_req_i.data(7 downto 0);
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end if;
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end if;
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-- operation triggers --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(2) = '0') then -- set by host
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ctrl.trig_rst <= bus_req_i.data(ctrl_trig_rst_c);
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ctrl.trig_bit <= bus_req_i.data(ctrl_trig_bit_c);
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ctrl.trig_byte <= bus_req_i.data(ctrl_trig_byte_c);
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elsif (ctrl.enable = '0') or (serial.state(1) = '1') then -- cleared when disabled or when in RTX/RESET state
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ctrl.trig_rst <= '0';
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ctrl.trig_bit <= '0';
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ctrl.trig_byte <= '0';
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end if;
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-- read access --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '0') then
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-- control register --
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if (bus_req_i.addr(2) = '0') then
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bus_rsp_o.data(ctrl_en_c) <= ctrl.enable;
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bus_rsp_o.data(ctrl_prsc1_c downto ctrl_prsc0_c) <= ctrl.clk_prsc;
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bus_rsp_o.data(ctrl_clkdiv7_c downto ctrl_clkdiv0_c) <= ctrl.clk_div;
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--
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bus_rsp_o.data(ctrl_sense_c) <= serial.wire_in(1);
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bus_rsp_o.data(ctrl_presence_c) <= serial.presence;
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bus_rsp_o.data(ctrl_busy_c) <= serial.busy;
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-- data register --
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else
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bus_rsp_o.data(7 downto 0) <= serial.sreg;
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end if;
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end if;
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end if;
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end process bus_access;
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-- Tick Generator -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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tick_generator: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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clk_tick <= '0';
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clk_cnt <= (others => '0');
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serial.tick <= '0';
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serial.tick_ff <= '0';
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elsif rising_edge(clk_i) then
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clk_tick <= clk_sel(to_integer(unsigned(ctrl.clk_prsc)));
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serial.tick <= '0'; -- default
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if (ctrl.enable = '0') then
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clk_cnt <= (others => '0');
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elsif (clk_tick = '1') then
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if (clk_cnt = unsigned(ctrl.clk_div)) then
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clk_cnt <= (others => '0');
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serial.tick <= '1'; -- signal is high for 1 clk_i cycle every 't_base'
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else
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clk_cnt <= clk_cnt + 1;
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end if;
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end if;
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serial.tick_ff <= serial.tick; -- tick delayed by one clock cycle (for precise bus state sampling)
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end if;
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end process tick_generator;
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-- enable SoC clock generator --
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clkgen_en_o <= ctrl.enable;
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-- only use the lowest 4 clocks of the system clock generator --
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clk_sel <= clkgen_i(3 downto 0);
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-- Serial Engine --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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serial_engine: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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serial.wire_in <= (others => '0');
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serial.done <= '0';
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serial.wire_lo <= '0';
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serial.wire_hi <= '0';
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serial.state <= (others => '0');
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serial.tick_cnt <= (others => '0');
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serial.bit_cnt <= (others => '0');
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serial.sreg <= (others => '0');
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serial.sample <= '0';
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onewire_o <= '0';
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elsif rising_edge(clk_i) then
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-- input synchronizer --
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serial.wire_in <= serial.wire_in(0) & to_stdulogic(to_bit(onewire_i)); -- "to_bit" to avoid hardware-vs-simulation mismatch
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-- bus control --
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if (serial.busy = '0') or (serial.wire_hi = '1') then -- disabled/idle or active tristate request
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onewire_o <= '1'; -- release bus (tristate), high (by pull-up resistor) or actively pulled low by device(s)
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elsif (serial.wire_lo = '1') then
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onewire_o <= '0'; -- pull bus actively low
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end if;
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-- defaults --
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serial.done <= '0';
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serial.wire_lo <= '0';
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serial.wire_hi <= '0';
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-- FSM --
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serial.state(2) <= ctrl.enable; -- module enabled? force reset state otherwise
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case serial.state is
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when "100" => -- enabled, but IDLE: wait for new request
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-- ------------------------------------------------------------
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serial.tick_cnt <= (others => '0');
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-- transmission size --
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if (ctrl.trig_bit = '1') then
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serial.bit_cnt <= "000"; -- single bit
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else
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serial.bit_cnt <= "111"; -- full-byte
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end if;
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-- any operation request? --
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if (ctrl.trig_rst = '1') or (ctrl.trig_bit = '1') or (ctrl.trig_byte = '1') then
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serial.state(1 downto 0) <= "01"; -- SYNC
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end if;
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when "101" => -- SYNC: start operation with next base tick
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-- ------------------------------------------------------------
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serial.sreg <= tx_data;
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if (serial.tick = '1') then -- synchronize
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serial.wire_lo <= '1'; -- force bus to low
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if (ctrl.trig_rst = '1') then
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serial.state(1 downto 0) <= "11"; -- RESET
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else
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serial.state(1 downto 0) <= "10"; -- RTX
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end if;
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end if;
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when "110" => -- RTX: read/write 'serial.bit_cnt-1' bits
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-- ------------------------------------------------------------
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-- go high to write 1 or to read OR time slot completed --
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if ((serial.tick_cnt = t_write_one_c) and (serial.sreg(0) = '1')) or (serial.tick_cnt = t_slot_end_c) then
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serial.wire_hi <= '1'; -- release bus
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end if;
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-- sample input (precisely / just once!) --
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if (serial.tick_cnt = t_read_sample_c) and (serial.tick_ff = '1') then
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serial.sample <= serial.wire_in(1);
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end if;
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-- inter-slot pause (end of bit) & iteration control --
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if (serial.tick_cnt = t_pause_end_c) then -- bit done
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serial.tick_cnt <= (others => '0');
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serial.sreg <= serial.sample & serial.sreg(7 downto 1); -- new bit; LSB first
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serial.bit_cnt <= serial.bit_cnt - 1;
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if (serial.bit_cnt = "000") then -- all done
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serial.done <= '1'; -- operation done
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serial.state(1 downto 0) <= "00"; -- go back to IDLE
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else -- next bit
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serial.wire_lo <= '1'; -- force bus to low again
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end if;
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elsif (serial.tick = '1') then
|
||
|
|
serial.tick_cnt <= serial.tick_cnt + 1;
|
||
|
|
end if;
|
||
|
|
|
||
|
|
when "111" => -- RESET: generate reset pulse and check for bus presence
|
||
|
|
-- ------------------------------------------------------------
|
||
|
|
if (serial.tick = '1') then
|
||
|
|
serial.tick_cnt <= serial.tick_cnt + 1;
|
||
|
|
end if;
|
||
|
|
-- end of reset pulse --
|
||
|
|
if (serial.tick_cnt = t_reset_end_c) then
|
||
|
|
serial.wire_hi <= '1'; -- release bus
|
||
|
|
end if;
|
||
|
|
-- sample device presence (precisely / just once!) --
|
||
|
|
if (serial.tick_cnt = t_presence_sample_c) and (serial.tick_ff = '1') then
|
||
|
|
serial.presence <= not serial.wire_in(1); -- set if bus is pulled low by any device
|
||
|
|
end if;
|
||
|
|
-- end of presence phase --
|
||
|
|
if (serial.tick_cnt = t_presence_end_c) then
|
||
|
|
serial.done <= '1'; -- operation done
|
||
|
|
serial.state(1 downto 0) <= "00"; -- go back to IDLE
|
||
|
|
end if;
|
||
|
|
|
||
|
|
when others => -- "0--" OFFLINE: deactivated, reset externally-readable signals
|
||
|
|
-- ------------------------------------------------------------
|
||
|
|
serial.sreg <= (others => '0');
|
||
|
|
serial.presence <= '0';
|
||
|
|
serial.state(1 downto 0) <= "00"; -- stay here, go to IDLE when module is enabled
|
||
|
|
|
||
|
|
end case;
|
||
|
|
end if;
|
||
|
|
end process serial_engine;
|
||
|
|
|
||
|
|
-- serial engine busy? --
|
||
|
|
serial.busy <= '0' when (serial.state(1 downto 0) = "00") else '1';
|
||
|
|
|
||
|
|
-- operation done interrupt --
|
||
|
|
irq_o <= serial.done;
|
||
|
|
|
||
|
|
|
||
|
|
end neorv32_onewire_rtl;
|