371 lines
16 KiB
VHDL
371 lines
16 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Serial Data Interface (SDI) >> #
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-- # ********************************************************************************************* #
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-- # Byte-oriented serial data interface using the SPI protocol. This device acts as *device* (not #
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-- # as a host). Hence, all data transfers are driven/clocked by an external SPI host controller. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_sdi is
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generic (
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RTX_FIFO : natural range 1 to 2**15 -- RTX fifo depth, has to be a power of two, min 1
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);
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, async
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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sdi_csn_i : in std_ulogic; -- low-active chip-select
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sdi_clk_i : in std_ulogic; -- serial clock
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sdi_dat_i : in std_ulogic; -- serial data input
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sdi_dat_o : out std_ulogic; -- serial data output
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irq_o : out std_ulogic -- CPU interrupt
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);
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end neorv32_sdi;
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architecture neorv32_sdi_rtl of neorv32_sdi is
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-- control register --
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constant ctrl_en_c : natural := 0; -- r/w: SDI enable
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constant ctrl_clr_rx_c : natural := 1; -- -/w: clear RX FIFO, auto-clears
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--constant ctrl_cpha_c : natural := 2; -- r/w: clock phase [TODO]
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--
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constant ctrl_fifo_size0_c : natural := 4; -- r/-: log2(FIFO size), bit 0 (lsb)
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constant ctrl_fifo_size1_c : natural := 5; -- r/-: log2(FIFO size), bit 1
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constant ctrl_fifo_size2_c : natural := 6; -- r/-: log2(FIFO size), bit 2
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constant ctrl_fifo_size3_c : natural := 7; -- r/-: log2(FIFO size), bit 3 (msb)
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--
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constant ctrl_irq_rx_avail_c : natural := 15; -- r/-: RX FIFO not empty
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constant ctrl_irq_rx_half_c : natural := 16; -- r/-: RX FIFO at least half full
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constant ctrl_irq_rx_full_c : natural := 17; -- r/-: RX FIFO full
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constant ctrl_irq_tx_empty_c : natural := 18; -- r/-: TX FIFO empty
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--
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constant ctrl_rx_avail_c : natural := 23; -- r/-: RX FIFO not empty
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constant ctrl_rx_half_c : natural := 24; -- r/-: RX FIFO at least half full
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constant ctrl_rx_full_c : natural := 25; -- r/-: RX FIFO full
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constant ctrl_tx_empty_c : natural := 26; -- r/-: TX FIFO empty
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constant ctrl_tx_full_c : natural := 27; -- r/-: TX FIFO full
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-- control register (see bit definitions above) --
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type ctrl_t is record
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enable : std_ulogic;
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clr_rx : std_ulogic;
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irq_rx_avail : std_ulogic;
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irq_rx_half : std_ulogic;
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irq_rx_full : std_ulogic;
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irq_tx_empty : std_ulogic;
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end record;
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signal ctrl : ctrl_t;
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-- input synchronizer --
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type sync_t is record
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sck_ff : std_ulogic_vector(2 downto 0);
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csn_ff : std_ulogic_vector(1 downto 0);
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sdi_ff : std_ulogic_vector(1 downto 0);
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sck : std_ulogic;
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csn : std_ulogic;
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sdi : std_ulogic;
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end record;
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signal sync : sync_t;
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-- serial engine --
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type serial_t is record
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state : std_ulogic_vector(2 downto 0);
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cnt : std_ulogic_vector(3 downto 0);
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sreg : std_ulogic_vector(7 downto 0);
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sdi_ff : std_ulogic;
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start : std_ulogic;
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done : std_ulogic;
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end record;
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signal serial : serial_t;
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-- RX/TX FIFO interface --
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type fifo_t is record
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we : std_ulogic; -- write enable
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re : std_ulogic; -- read enable
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clear : std_ulogic; -- sync reset, high-active
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wdata : std_ulogic_vector(7 downto 0); -- write data
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rdata : std_ulogic_vector(7 downto 0); -- read data
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avail : std_ulogic; -- data available?
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free : std_ulogic; -- free entry available?
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half : std_ulogic; -- half full
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end record;
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signal tx_fifo, rx_fifo : fifo_t;
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begin
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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ctrl.enable <= '0';
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ctrl.clr_rx <= '0';
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ctrl.irq_rx_avail <= '0';
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ctrl.irq_rx_half <= '0';
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ctrl.irq_rx_full <= '0';
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ctrl.irq_tx_empty <= '0';
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elsif rising_edge(clk_i) then
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-- bus handshake --
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bus_rsp_o.ack <= bus_req_i.stb;
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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-- defaults --
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ctrl.clr_rx <= '0';
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if (bus_req_i.stb = '1') then
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-- write access --
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if (bus_req_i.rw = '1') then
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if (bus_req_i.addr(2) = '0') then -- control register
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ctrl.enable <= bus_req_i.data(ctrl_en_c);
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ctrl.clr_rx <= bus_req_i.data(ctrl_clr_rx_c);
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--
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ctrl.irq_rx_avail <= bus_req_i.data(ctrl_irq_rx_avail_c);
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ctrl.irq_rx_half <= bus_req_i.data(ctrl_irq_rx_half_c);
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ctrl.irq_rx_full <= bus_req_i.data(ctrl_irq_rx_full_c);
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ctrl.irq_tx_empty <= bus_req_i.data(ctrl_irq_tx_empty_c);
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end if;
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-- read access --
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else
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if (bus_req_i.addr(2) = '0') then -- control register
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bus_rsp_o.data(ctrl_en_c) <= ctrl.enable;
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--
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bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(RTX_FIFO), 4));
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--
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bus_rsp_o.data(ctrl_irq_rx_avail_c) <= ctrl.irq_rx_avail;
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bus_rsp_o.data(ctrl_irq_rx_half_c) <= ctrl.irq_rx_half;
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bus_rsp_o.data(ctrl_irq_rx_full_c) <= ctrl.irq_rx_full;
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bus_rsp_o.data(ctrl_irq_tx_empty_c) <= ctrl.irq_tx_empty;
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--
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bus_rsp_o.data(ctrl_rx_avail_c) <= rx_fifo.avail;
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bus_rsp_o.data(ctrl_rx_half_c) <= rx_fifo.half;
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bus_rsp_o.data(ctrl_rx_full_c) <= not rx_fifo.free;
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bus_rsp_o.data(ctrl_tx_empty_c) <= not tx_fifo.avail;
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bus_rsp_o.data(ctrl_tx_full_c) <= not tx_fifo.free;
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else -- data register
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bus_rsp_o.data(7 downto 0) <= rx_fifo.rdata;
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end if;
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end if;
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end if;
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end if;
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end process bus_access;
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-- Data FIFO ("Ring Buffer") --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- TX --
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tx_fifo_inst: entity neorv32.neorv32_fifo
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generic map (
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FIFO_DEPTH => RTX_FIFO, -- number of fifo entries; has to be a power of two; min 1
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FIFO_WIDTH => 8, -- size of data elements in fifo (32-bit only for simulation)
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FIFO_RSYNC => true, -- sync read
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FIFO_SAFE => true, -- safe access
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FULL_RESET => false -- no HW reset, try to infer BRAM
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)
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port map (
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-- control --
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clk_i => clk_i, -- clock, rising edge
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rstn_i => rstn_i, -- async reset, low-active
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clear_i => tx_fifo.clear, -- sync reset, high-active
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half_o => tx_fifo.half, -- FIFO at least half-full
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-- write port --
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wdata_i => tx_fifo.wdata, -- write data
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we_i => tx_fifo.we, -- write enable
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free_o => tx_fifo.free, -- at least one entry is free when set
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-- read port --
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re_i => tx_fifo.re, -- read enable
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rdata_o => tx_fifo.rdata, -- read data
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avail_o => tx_fifo.avail -- data available when set
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);
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-- write access (CPU) --
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tx_fifo.clear <= not ctrl.enable;
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tx_fifo.wdata <= bus_req_i.data(7 downto 0);
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tx_fifo.we <= '1' when (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(2) = '1') else '0';
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-- read access (SDI) --
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tx_fifo.re <= serial.start;
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-- RX --
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rx_fifo_inst: entity neorv32.neorv32_fifo
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generic map (
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FIFO_DEPTH => RTX_FIFO, -- number of fifo entries; has to be a power of two; min 1
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FIFO_WIDTH => 8, -- size of data elements in fifo (32-bit only for simulation)
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FIFO_RSYNC => true, -- sync read
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FIFO_SAFE => true -- safe access
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)
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port map (
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-- control --
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clk_i => clk_i, -- clock, rising edge
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rstn_i => rstn_i, -- async reset, low-active
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clear_i => rx_fifo.clear, -- sync reset, high-active
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half_o => rx_fifo.half, -- FIFO at least half-full
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-- write port --
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wdata_i => rx_fifo.wdata, -- write data
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we_i => rx_fifo.we, -- write enable
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free_o => rx_fifo.free, -- at least one entry is free when set
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-- read port --
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re_i => rx_fifo.re, -- read enable
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rdata_o => rx_fifo.rdata, -- read data
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avail_o => rx_fifo.avail -- data available when set
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);
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-- write access (SDI) --
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rx_fifo.wdata <= serial.sreg;
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rx_fifo.we <= serial.done;
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-- read access (CPU) --
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rx_fifo.clear <= (not ctrl.enable) or ctrl.clr_rx;
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rx_fifo.re <= '1' when (bus_req_i.stb = '1') and (bus_req_i.rw = '0') and (bus_req_i.addr(2) = '1') else '0';
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-- Input Synchronizer ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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synchronizer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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sync.sck_ff <= (others => '0');
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sync.csn_ff <= (others => '0');
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sync.sdi_ff <= (others => '0');
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elsif rising_edge(clk_i) then
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sync.sck_ff <= sync.sck_ff(1 downto 0) & sdi_clk_i;
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sync.csn_ff <= sync.csn_ff(0) & sdi_csn_i;
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sync.sdi_ff <= sync.sdi_ff(0) & sdi_dat_i;
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end if;
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end process synchronizer;
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sync.sck <= sync.sck_ff(1) xor sync.sck_ff(2); -- edge detect
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sync.csn <= sync.csn_ff(1);
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sync.sdi <= sync.sdi_ff(1);
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-- Serial Engine --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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serial_engine: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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serial.start <= '0';
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serial.done <= '0';
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serial.state <= (others => '0');
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serial.cnt <= (others => '0');
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serial.sreg <= (others => '0');
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serial.sdi_ff <= '0';
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elsif rising_edge(clk_i) then
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-- defaults --
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serial.start <= '0';
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serial.done <= '0';
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-- FSM --
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serial.state(2) <= ctrl.enable;
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case serial.state is
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when "100" => -- enabled but idle, waiting for new transmission trigger
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-- ------------------------------------------------------------
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serial.cnt <= (others => '0');
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if (tx_fifo.avail = '0') then -- output zero if no RX data available
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serial.sreg <= (others => '0');
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else
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serial.sreg <= tx_fifo.rdata;
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end if;
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if (sync.csn = '0') then -- start new transmission on falling edge of chip-select
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serial.start <= '1';
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serial.state(1 downto 0) <= "10";
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end if;
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when "110" => -- bit phase A: sample
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-- ------------------------------------------------------------
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serial.sdi_ff <= sdi_dat_i;
|
||
|
|
if (sync.csn = '1') then -- transmission aborted?
|
||
|
|
serial.state(1 downto 0) <= "00";
|
||
|
|
elsif (sync.sck = '1') then
|
||
|
|
serial.cnt <= std_ulogic_vector(unsigned(serial.cnt) + 1);
|
||
|
|
serial.state(1 downto 0) <= "11";
|
||
|
|
end if;
|
||
|
|
|
||
|
|
when "111" => -- bit phase B: shift
|
||
|
|
-- ------------------------------------------------------------
|
||
|
|
if (sync.csn = '1') then -- transmission aborted?
|
||
|
|
serial.state(1 downto 0) <= "00";
|
||
|
|
elsif (sync.sck = '1') then
|
||
|
|
serial.sreg <= serial.sreg(serial.sreg'left-1 downto 0) & serial.sdi_ff;
|
||
|
|
if (serial.cnt(3) = '1') then -- done?
|
||
|
|
serial.done <= '1';
|
||
|
|
serial.state(1 downto 0) <= "00";
|
||
|
|
else
|
||
|
|
serial.state(1 downto 0) <= "10";
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
|
||
|
|
when others => -- "0--": disabled
|
||
|
|
-- ------------------------------------------------------------
|
||
|
|
serial.state(1 downto 0) <= "00";
|
||
|
|
|
||
|
|
end case;
|
||
|
|
end if;
|
||
|
|
end process serial_engine;
|
||
|
|
|
||
|
|
-- serial data output --
|
||
|
|
sdi_dat_o <= serial.sreg(serial.sreg'left);
|
||
|
|
|
||
|
|
|
||
|
|
-- Interrupt Generator --------------------------------------------------------------------
|
||
|
|
-- -------------------------------------------------------------------------------------------
|
||
|
|
irq_generator: process(rstn_i, clk_i)
|
||
|
|
begin
|
||
|
|
if (rstn_i = '0') then
|
||
|
|
irq_o <= '0';
|
||
|
|
elsif rising_edge(clk_i) then
|
||
|
|
irq_o <= ctrl.enable and (
|
||
|
|
(ctrl.irq_rx_avail and rx_fifo.avail) or -- RX FIFO not empty
|
||
|
|
(ctrl.irq_rx_half and rx_fifo.half) or -- RX FIFO at least half full
|
||
|
|
(ctrl.irq_rx_full and (not rx_fifo.free)) or -- RX FIFO full
|
||
|
|
(ctrl.irq_tx_empty and (not tx_fifo.avail))); -- TX FIFO empty
|
||
|
|
end if;
|
||
|
|
end process irq_generator;
|
||
|
|
|
||
|
|
|
||
|
|
end neorv32_sdi_rtl;
|