317 lines
15 KiB
VHDL
317 lines
15 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Stream Link Interface (SLINK) >> #
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-- # ********************************************************************************************* #
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-- # Two independent stream links for RX and TX each equipped with a configurable FIFO and #
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-- # providing programmable interrupt conditions. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_slink is
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generic (
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SLINK_RX_FIFO : natural range 1 to 2**15; -- RX fifo depth, has to be a power of two
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SLINK_TX_FIFO : natural range 1 to 2**15 -- TX fifo depth, has to be a power of two
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);
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port (
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-- Host access --
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, async
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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irq_o : out std_ulogic; -- CPU interrupt
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-- RX stream interface --
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slink_rx_data_i : in std_ulogic_vector(31 downto 0); -- input data
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slink_rx_valid_i : in std_ulogic; -- valid input
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slink_rx_last_i : in std_ulogic; -- end of stream
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slink_rx_ready_o : out std_ulogic; -- ready to receive
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-- TX stream interface --
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slink_tx_data_o : out std_ulogic_vector(31 downto 0); -- output data
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slink_tx_valid_o : out std_ulogic; -- valid output
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slink_tx_last_o : out std_ulogic; -- end of stream
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slink_tx_ready_i : in std_ulogic -- ready to send
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);
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end neorv32_slink;
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architecture neorv32_slink_rtl of neorv32_slink is
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-- memory-mapped interface registers --
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constant addr_ctrl_c : std_ulogic_vector(1 downto 0) := "00"; -- control register
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constant addr_rx_c : std_ulogic_vector(1 downto 0) := "01"; -- RX data
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constant addr_tx_c : std_ulogic_vector(1 downto 0) := "10"; -- TX data
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constant addr_tx_last_c : std_ulogic_vector(1 downto 0) := "11"; -- TY data + last-delimiter
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-- control register --
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constant ctrl_en_c : natural := 0; -- r/w: Global module enable
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constant ctrl_rx_clr_c : natural := 1; -- -/w: Clear RX FIFO, auto-clears
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constant ctrl_tx_clr_c : natural := 2; -- -/w: Clear TX FIFO, auto-clears
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--
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constant ctrl_rx_last_c : natural := 4; -- r/-: RX end-of-stream (according to prev. read RX data)
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--
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constant ctrl_rx_empty_c : natural := 8; -- r/-: RX FIFO empty
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constant ctrl_rx_half_c : natural := 9; -- r/-: RX FIFO at least half full
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constant ctrl_rx_full_c : natural := 10; -- r/-: RX FIFO full
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constant ctrl_tx_empty_c : natural := 11; -- r/-: TX FIFO empty
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constant ctrl_tx_half_c : natural := 12; -- r/-: TX FIFO at least half full
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constant ctrl_tx_full_c : natural := 13; -- r/-: TX FIFO full
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--
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constant ctrl_irq_rx_nempty_c : natural := 16; -- r/w: IRQ if RX FIFO not empty
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constant ctrl_irq_rx_half_c : natural := 17; -- r/w: IRQ if RX FIFO at least half full
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constant ctrl_irq_rx_full_c : natural := 18; -- r/w: IRQ if RX FIFO full
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constant ctrl_irq_tx_empty_c : natural := 19; -- r/w: IRQ if TX FIFO empty
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constant ctrl_irq_tx_nhalf_c : natural := 20; -- r/w: IRQ if TX FIFO not at least half full
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constant ctrl_irq_tx_nfull_c : natural := 21; -- r/w: IRQ if TX FIFO not full
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--
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constant ctrl_rx_fifo_size0_c : natural := 24; -- r/-: log2(RX fifo size), bit 0 (lsb)
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constant ctrl_rx_fifo_size1_c : natural := 25; -- r/-: log2(RX fifo size), bit 1
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constant ctrl_rx_fifo_size2_c : natural := 26; -- r/-: log2(RX fifo size), bit 2
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constant ctrl_rx_fifo_size3_c : natural := 27; -- r/-: log2(RX fifo size), bit 3 (msb)
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constant ctrl_tx_fifo_size0_c : natural := 28; -- r/-: log2(TX fifo size), bit 0 (lsb)
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constant ctrl_tx_fifo_size1_c : natural := 29; -- r/-: log2(TX fifo size), bit 1
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constant ctrl_tx_fifo_size2_c : natural := 30; -- r/-: log2(TX fifo size), bit 2
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constant ctrl_tx_fifo_size3_c : natural := 31; -- r/-: log2(TX fifo size), bit 3 (msb)
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-- control register --
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type ctrl_t is record
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enable : std_ulogic;
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rx_clr : std_ulogic;
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tx_clr : std_ulogic;
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irq_rx_nempty : std_ulogic;
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irq_rx_half : std_ulogic;
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irq_rx_full : std_ulogic;
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irq_tx_empty : std_ulogic;
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irq_tx_nhalf : std_ulogic;
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irq_tx_nfull : std_ulogic;
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end record;
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signal ctrl : ctrl_t;
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-- RX last indicator --
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signal rx_last : std_ulogic;
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-- FIFO interface --
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type fifo_t is record
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we : std_ulogic; -- write enable
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re : std_ulogic; -- read enable
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clear : std_ulogic; -- sync reset, high-active
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wdata : std_ulogic_vector(32 downto 0); -- write data + last-flag
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rdata : std_ulogic_vector(32 downto 0); -- read data + last-flag
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avail : std_ulogic; -- data available?
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free : std_ulogic; -- free entry available?
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half : std_ulogic; -- half full
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end record;
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signal tx_fifo, rx_fifo : fifo_t;
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begin
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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ctrl.enable <= '0';
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ctrl.rx_clr <= '0';
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ctrl.tx_clr <= '0';
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ctrl.irq_rx_nempty <= '0';
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ctrl.irq_rx_half <= '0';
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ctrl.irq_rx_full <= '0';
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ctrl.irq_tx_empty <= '0';
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ctrl.irq_tx_nhalf <= '0';
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ctrl.irq_tx_nfull <= '0';
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elsif rising_edge(clk_i) then
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-- bus handshake --
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bus_rsp_o.ack <= bus_req_i.stb;
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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-- defaults --
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ctrl.rx_clr <= '0'; -- auto-clear
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ctrl.tx_clr <= '0'; -- auto-clear
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if (bus_req_i.stb = '1') then
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-- write access --
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if (bus_req_i.rw = '1') then
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if (bus_req_i.addr(3 downto 2) = addr_ctrl_c) then -- control register
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ctrl.enable <= bus_req_i.data(ctrl_en_c);
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ctrl.rx_clr <= bus_req_i.data(ctrl_rx_clr_c);
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ctrl.tx_clr <= bus_req_i.data(ctrl_tx_clr_c);
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--
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ctrl.irq_rx_nempty <= bus_req_i.data(ctrl_irq_rx_nempty_c);
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ctrl.irq_rx_half <= bus_req_i.data(ctrl_irq_rx_half_c);
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ctrl.irq_rx_full <= bus_req_i.data(ctrl_irq_rx_full_c);
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ctrl.irq_tx_empty <= bus_req_i.data(ctrl_irq_tx_empty_c);
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ctrl.irq_tx_nhalf <= bus_req_i.data(ctrl_irq_tx_nhalf_c);
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ctrl.irq_tx_nfull <= bus_req_i.data(ctrl_irq_tx_nfull_c);
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end if;
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-- read access --
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else
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if (bus_req_i.addr(3 downto 2) = addr_ctrl_c) then -- control register
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bus_rsp_o.data(ctrl_en_c) <= ctrl.enable;
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--
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bus_rsp_o.data(ctrl_rx_last_c) <= rx_last;
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--
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bus_rsp_o.data(ctrl_rx_empty_c) <= not rx_fifo.avail;
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bus_rsp_o.data(ctrl_rx_half_c) <= rx_fifo.half;
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bus_rsp_o.data(ctrl_rx_full_c) <= not rx_fifo.free;
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bus_rsp_o.data(ctrl_tx_empty_c) <= not tx_fifo.avail;
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bus_rsp_o.data(ctrl_tx_half_c) <= tx_fifo.half;
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bus_rsp_o.data(ctrl_tx_full_c) <= not tx_fifo.free;
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--
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bus_rsp_o.data(ctrl_irq_rx_nempty_c) <= ctrl.irq_rx_nempty;
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bus_rsp_o.data(ctrl_irq_rx_half_c) <= ctrl.irq_rx_half;
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bus_rsp_o.data(ctrl_irq_rx_full_c) <= ctrl.irq_rx_full;
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bus_rsp_o.data(ctrl_irq_tx_empty_c) <= ctrl.irq_tx_empty;
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bus_rsp_o.data(ctrl_irq_tx_nhalf_c) <= ctrl.irq_tx_nhalf;
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bus_rsp_o.data(ctrl_irq_tx_nfull_c) <= ctrl.irq_tx_nfull;
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--
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bus_rsp_o.data(ctrl_rx_fifo_size3_c downto ctrl_rx_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_RX_FIFO), 4));
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bus_rsp_o.data(ctrl_tx_fifo_size3_c downto ctrl_tx_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_TX_FIFO), 4));
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else -- RX (TX) data register
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bus_rsp_o.data <= rx_fifo.rdata(31 downto 0);
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end if;
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end if;
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end if;
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end if;
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end process bus_access;
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-- RX Data FIFO ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rx_fifo_inst: entity neorv32.neorv32_fifo
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generic map (
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FIFO_DEPTH => SLINK_RX_FIFO,
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FIFO_WIDTH => 32+1, -- data + last-flag
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FIFO_RSYNC => false, -- "async" read - update FIFO status RIGHT after write access (for slink_rx_ready_o)
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FIFO_SAFE => true, -- safe access
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FULL_RESET => false -- no HW reset, try to infer BRAM
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)
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port map (
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-- control --
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clk_i => clk_i,
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rstn_i => rstn_i,
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clear_i => rx_fifo.clear,
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half_o => rx_fifo.half,
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-- write port --
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wdata_i => rx_fifo.wdata,
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we_i => rx_fifo.we,
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free_o => rx_fifo.free,
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-- read port --
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re_i => rx_fifo.re,
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rdata_o => rx_fifo.rdata,
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avail_o => rx_fifo.avail
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);
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rx_fifo.clear <= (not ctrl.enable) or ctrl.rx_clr;
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rx_fifo.re <= '1' when (bus_req_i.stb = '1') and (bus_req_i.rw = '0') and (bus_req_i.addr(3 downto 2) = addr_rx_c) else '0';
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rx_fifo.we <= slink_rx_valid_i;
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rx_fifo.wdata(31 downto 0) <= slink_rx_data_i;
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rx_fifo.wdata(32) <= slink_rx_last_i;
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slink_rx_ready_o <= rx_fifo.free;
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-- backup current RX last indicator for current access --
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rx_last_flag: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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rx_last <= '0';
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elsif rising_edge(clk_i) then
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if (rx_fifo.clear = '1') then
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rx_last <= '0';
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elsif (rx_fifo.re = '1') then
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rx_last <= rx_fifo.rdata(32);
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end if;
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end if;
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end process rx_last_flag;
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-- TX Data FIFO ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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tx_fifo_inst: entity neorv32.neorv32_fifo
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generic map (
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FIFO_DEPTH => SLINK_TX_FIFO,
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FIFO_WIDTH => 32+1, -- data + last-flag
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FIFO_RSYNC => false, -- "async" read - update FIFO status RIGHT after read access (for slink_tx_valid_o)
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FIFO_SAFE => true, -- safe access
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FULL_RESET => false -- no HW reset, try to infer BRAM
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)
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port map (
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-- control --
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clk_i => clk_i,
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rstn_i => rstn_i,
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clear_i => tx_fifo.clear,
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half_o => tx_fifo.half,
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-- write port --
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wdata_i => tx_fifo.wdata,
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we_i => tx_fifo.we,
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free_o => tx_fifo.free,
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-- read port --
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re_i => tx_fifo.re,
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rdata_o => tx_fifo.rdata,
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avail_o => tx_fifo.avail
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);
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tx_fifo.clear <= (not ctrl.enable) or ctrl.tx_clr;
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tx_fifo.we <= '1' when (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(3) = '1') else '0';
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tx_fifo.wdata <= bus_req_i.addr(2) & bus_req_i.data; -- last-flag is set implicitly via access address (TX/TX_LAST register)
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tx_fifo.re <= slink_tx_ready_i;
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slink_tx_data_o <= tx_fifo.rdata(31 downto 0);
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slink_tx_last_o <= tx_fifo.rdata(32) and tx_fifo.avail;
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|
|
slink_tx_valid_o <= tx_fifo.avail;
|
||
|
|
|
||
|
|
|
||
|
|
-- Interrupt Generator --------------------------------------------------------------------
|
||
|
|
-- -------------------------------------------------------------------------------------------
|
||
|
|
irq_generator: process(rstn_i, clk_i)
|
||
|
|
begin
|
||
|
|
if (rstn_i = '0') then
|
||
|
|
irq_o <= '0';
|
||
|
|
elsif rising_edge(clk_i) then
|
||
|
|
irq_o <= ctrl.enable and ( -- IRQ if enabled and ...
|
||
|
|
(ctrl.irq_tx_empty and (not tx_fifo.avail)) or -- TX FIFO is empty
|
||
|
|
(ctrl.irq_tx_nhalf and (not tx_fifo.half)) or -- TX FIFO is not at least half full
|
||
|
|
(ctrl.irq_tx_nfull and ( tx_fifo.free)) or -- TX FIFO is not full
|
||
|
|
(ctrl.irq_rx_nempty and ( rx_fifo.avail)) or -- RX FIFO is not empty
|
||
|
|
(ctrl.irq_rx_half and ( rx_fifo.half)) or -- RX FIFO is at least half full
|
||
|
|
(ctrl.irq_rx_full and (not rx_fifo.free))); -- RX FIFO is full
|
||
|
|
end if;
|
||
|
|
end process irq_generator;
|
||
|
|
|
||
|
|
|
||
|
|
end neorv32_slink_rtl;
|