191 lines
14 KiB
VHDL
191 lines
14 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - System/Processor Configuration Information Memory (SYSINFO) >> #
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-- # ********************************************************************************************* #
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-- # This unit provides information regarding the NEORV32 processor system configuration - #
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-- # mostly derived from the top's configuration generics. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_sysinfo is
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generic (
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-- General --
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CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
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CLOCK_GATING_EN : boolean; -- enable clock gating when in sleep mode
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INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- Internal instruction memory --
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MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
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-- Internal data memory --
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MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
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-- Reservation Set Granularity --
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AMO_RVS_GRANULARITY : natural; -- size in bytes, has to be a power of 2, min 4
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-- Instruction cache --
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ICACHE_EN : boolean; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2
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-- Data cache --
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DCACHE_EN : boolean; -- implement data cache
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DCACHE_NUM_BLOCKS : natural; -- d-cache: number of blocks (min 2), has to be a power of 2
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DCACHE_BLOCK_SIZE : natural; -- d-cache: block size in bytes (min 4), has to be a power of 2
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-- External memory interface --
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MEM_EXT_EN : boolean; -- implement external memory bus interface?
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MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
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-- On-chip debugger --
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ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD?
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-- Processor peripherals --
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IO_GPIO_EN : boolean; -- implement general purpose IO port (GPIO)?
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IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)?
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IO_SDI_EN : boolean; -- implement serial data interface (SDI)?
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IO_TWI_EN : boolean; -- implement two-wire interface (TWI)?
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IO_PWM_EN : boolean; -- implement pulse-width modulation controller (PWM)?
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IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
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IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
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IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_XIRQ_EN : boolean; -- implement external interrupts controller (XIRQ)?
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IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
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XIP_EN : boolean; -- implement execute in place module (XIP)?
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IO_ONEWIRE_EN : boolean; -- implement 1-wire interface (ONEWIRE)?
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IO_DMA_EN : boolean; -- implement direct memory access controller (DMA)?
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IO_SLINK_EN : boolean; -- implement stream link interface (SLINK)?
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IO_CRC_EN : boolean -- implement cyclic redundancy check unit (CRC)?
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);
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, async
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t -- bus response
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);
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end neorv32_sysinfo;
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architecture neorv32_sysinfo_rtl of neorv32_sysinfo is
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-- helpers --
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constant int_imem_en_c : boolean := MEM_INT_IMEM_EN and boolean(MEM_INT_IMEM_SIZE > 0);
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constant int_dmem_en_c : boolean := MEM_INT_DMEM_EN and boolean(MEM_INT_DMEM_SIZE > 0);
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-- system information ROM --
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type sysinfo_t is array (0 to 3) of std_ulogic_vector(31 downto 0);
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signal sysinfo : sysinfo_t;
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begin
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-- Construct Info ROM ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- SYSINFO(0): Processor Clock Frequency in Hz --
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sysinfo(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
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-- SYSINFO(1): Internal Memory Configuration (sizes)
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sysinfo(1)(07 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_IMEM_SIZE), 8)); -- log2(IMEM size)
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sysinfo(1)(15 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_DMEM_SIZE), 8)); -- log2(DMEM size)
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sysinfo(1)(23 downto 16) <= (others => '0'); -- reserved
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sysinfo(1)(31 downto 24) <= std_ulogic_vector(to_unsigned(index_size_f(AMO_RVS_GRANULARITY), 8)); -- log2(reservation set granularity)
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-- SYSINFO(2): SoC Configuration --
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sysinfo(2)(00) <= '1' when INT_BOOTLOADER_EN else '0'; -- processor-internal bootloader implemented?
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sysinfo(2)(01) <= '1' when MEM_EXT_EN else '0'; -- external memory bus interface implemented?
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sysinfo(2)(02) <= '1' when int_imem_en_c else '0'; -- processor-internal instruction memory implemented?
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sysinfo(2)(03) <= '1' when int_dmem_en_c else '0'; -- processor-internal data memory implemented?
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sysinfo(2)(04) <= '1' when MEM_EXT_BIG_ENDIAN else '0'; -- is external memory bus interface using BIG-endian byte-order?
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sysinfo(2)(05) <= '1' when ICACHE_EN else '0'; -- processor-internal instruction cache implemented?
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sysinfo(2)(06) <= '1' when DCACHE_EN else '0'; -- processor-internal data cache implemented?
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sysinfo(2)(07) <= '1' when CLOCK_GATING_EN else '0'; -- enable clock gating when in sleep mode
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sysinfo(2)(08) <= '0'; -- reserved
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sysinfo(2)(09) <= '0'; -- reserved
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sysinfo(2)(10) <= '0'; -- reserved
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sysinfo(2)(11) <= '0'; -- reserved
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sysinfo(2)(12) <= '1' when IO_CRC_EN else '0'; -- cyclic redundancy check unit (CRC) implemented?
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sysinfo(2)(13) <= '1' when IO_SLINK_EN else '0'; -- stream link interface (SLINK) implemented?
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sysinfo(2)(14) <= '1' when IO_DMA_EN else '0'; -- direct memory access controller (DMA) implemented?
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sysinfo(2)(15) <= '1' when IO_GPIO_EN else '0'; -- general purpose input/output port unit (GPIO) implemented?
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sysinfo(2)(16) <= '1' when IO_MTIME_EN else '0'; -- machine system timer (MTIME) implemented?
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sysinfo(2)(17) <= '1' when IO_UART0_EN else '0'; -- primary universal asynchronous receiver/transmitter (UART0) implemented?
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sysinfo(2)(18) <= '1' when IO_SPI_EN else '0'; -- serial peripheral interface (SPI) implemented?
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sysinfo(2)(19) <= '1' when IO_TWI_EN else '0'; -- two-wire interface (TWI) implemented?
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sysinfo(2)(20) <= '1' when IO_PWM_EN else '0'; -- pulse-width modulation unit (PWM) implemented?
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sysinfo(2)(21) <= '1' when IO_WDT_EN else '0'; -- watch dog timer (WDT) implemented?
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sysinfo(2)(22) <= '1' when IO_CFS_EN else '0'; -- custom functions subsystem (CFS) implemented?
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sysinfo(2)(23) <= '1' when IO_TRNG_EN else '0'; -- true random number generator (TRNG) implemented?
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sysinfo(2)(24) <= '1' when IO_SDI_EN else '0'; -- serial data interface (SDI) implemented?
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sysinfo(2)(25) <= '1' when IO_UART1_EN else '0'; -- secondary universal asynchronous receiver/transmitter (UART1) implemented?
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sysinfo(2)(26) <= '1' when IO_NEOLED_EN else '0'; -- NeoPixel-compatible smart LED interface (NEOLED) implemented?
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sysinfo(2)(27) <= '1' when IO_XIRQ_EN else '0'; -- external interrupt controller (XIRQ) implemented?
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sysinfo(2)(28) <= '1' when IO_GPTMR_EN else '0'; -- general purpose timer (GPTMR) implemented?
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sysinfo(2)(29) <= '1' when XIP_EN else '0'; -- execute in place module (XIP) implemented?
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sysinfo(2)(30) <= '1' when IO_ONEWIRE_EN else '0'; -- 1-wire interface (ONEWIRE) implemented?
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sysinfo(2)(31) <= '1' when ON_CHIP_DEBUGGER_EN else '0'; -- on-chip debugger implemented?
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-- SYSINFO(3): Cache Configuration --
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sysinfo(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(block_size_in_bytes)
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sysinfo(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(number_of_block)
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sysinfo(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(associativity)
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sysinfo(3)(15 downto 12) <= "0001" when (ICACHE_ASSOCIATIVITY > 1) and ICACHE_EN else (others => '0'); -- i-cache: replacement strategy (LRU only (yet))
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--
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sysinfo(3)(19 downto 16) <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_BLOCK_SIZE), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(block_size)
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sysinfo(3)(23 downto 20) <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_NUM_BLOCKS), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(num_blocks)
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sysinfo(3)(27 downto 24) <= (others => '0'); -- d-cache: log2(associativity)
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sysinfo(3)(31 downto 28) <= (others => '0'); -- d-cache: replacement strategy
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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elsif rising_edge(clk_i) then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '0') then -- read-only
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bus_rsp_o.ack <= '1';
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bus_rsp_o.data <= sysinfo(to_integer(unsigned(bus_req_i.addr(3 downto 2))));
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end if;
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end if;
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end process bus_access;
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end neorv32_sysinfo_rtl;
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