396 lines
18 KiB
VHDL
396 lines
18 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Two-Wire Interface Controller (TWI) >> #
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-- # ********************************************************************************************* #
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-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. #
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-- # Supports ACKs by the controller. 8 clock pre-scalers + 4-bit clock divider for bus clock #
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-- # configuration. No multi-controller support and no peripheral mode support yet. #
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-- # Interrupt: "transmission done" #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_twi is
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, async
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(7 downto 0);
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twi_sda_i : in std_ulogic; -- serial data line input
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twi_sda_o : out std_ulogic; -- serial data line output
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twi_scl_i : in std_ulogic; -- serial clock line input
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twi_scl_o : out std_ulogic; -- serial clock line output
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irq_o : out std_ulogic -- transfer done IRQ
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);
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end neorv32_twi;
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architecture neorv32_twi_rtl of neorv32_twi is
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-- control register --
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constant ctrl_en_c : natural := 0; -- r/w: TWI enable
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constant ctrl_start_c : natural := 1; -- -/w: Generate START condition
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constant ctrl_stop_c : natural := 2; -- -/w: Generate STOP condition
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constant ctrl_mack_c : natural := 3; -- r/w: generate ACK by controller for transmission
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constant ctrl_csen_c : natural := 4; -- r/w: allow clock stretching when set
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constant ctrl_prsc0_c : natural := 5; -- r/w: CLK prsc bit 0
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constant ctrl_prsc1_c : natural := 6; -- r/w: CLK prsc bit 1
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constant ctrl_prsc2_c : natural := 7; -- r/w: CLK prsc bit 2
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constant ctrl_cdiv0_c : natural := 8; -- r/w: clock divider bit 0
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constant ctrl_cdiv1_c : natural := 9; -- r/w: clock divider bit 1
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constant ctrl_cdiv2_c : natural := 10; -- r/w: clock divider bit 2
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constant ctrl_cdiv3_c : natural := 11; -- r/w: clock divider bit 3
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--
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constant ctrl_claimed_c : natural := 29; -- r/-: Set if bus is still claimed
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constant ctrl_ack_c : natural := 30; -- r/-: Set if ACK received
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constant ctrl_busy_c : natural := 31; -- r/-: Set if TWI unit is busy
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-- control register --
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type ctrl_t is record
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enable : std_ulogic;
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mack : std_ulogic;
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csen : std_ulogic;
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prsc : std_ulogic_vector(2 downto 0);
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cdiv : std_ulogic_vector(3 downto 0);
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end record;
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signal ctrl : ctrl_t;
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-- operation triggers --
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signal trig_start : std_ulogic;
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signal trig_stop : std_ulogic;
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signal trig_data : std_ulogic;
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-- clock generator --
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type clk_gen_t is record
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cnt : std_ulogic_vector(3 downto 0); -- clock divider
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tick : std_ulogic; -- actual TWI "clock"
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phase_gen : std_ulogic_vector(3 downto 0); -- clock phase generator
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phase_gen_ff : std_ulogic_vector(3 downto 0);
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phase : std_ulogic_vector(3 downto 0);
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halt : std_ulogic; -- active clock stretching
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end record;
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signal clk_gen : clk_gen_t;
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-- arbiter --
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type arbiter_t is record
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state : std_ulogic_vector(2 downto 0);
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state_nxt : std_ulogic_vector(1 downto 0);
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bitcnt : std_ulogic_vector(3 downto 0);
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rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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rtx_done : std_ulogic; -- transmission done
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busy : std_ulogic;
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claimed : std_ulogic; -- bus is currently claimed by _this_ controller
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end record;
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signal arbiter : arbiter_t;
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-- tri-state I/O control --
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type io_con_t is record
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sda_in_ff : std_ulogic_vector(1 downto 0); -- SDA input sync
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scl_in_ff : std_ulogic_vector(1 downto 0); -- SCL input sync
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sda_in : std_ulogic;
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scl_in : std_ulogic;
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sda_out : std_ulogic;
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scl_out : std_ulogic;
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end record;
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signal io_con : io_con_t;
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begin
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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ctrl.enable <= '0';
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ctrl.mack <= '0';
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ctrl.csen <= '0';
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ctrl.prsc <= (others => '0');
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ctrl.cdiv <= (others => '0');
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trig_start <= '0';
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trig_stop <= '0';
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trig_data <= '0';
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elsif rising_edge(clk_i) then
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-- bus handshake --
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bus_rsp_o.ack <= bus_req_i.stb;
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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-- defaults --
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trig_start <= '0';
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trig_stop <= '0';
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trig_data <= '0';
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if (bus_req_i.stb = '1') then
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-- write access --
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if (bus_req_i.rw = '1') then
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if (bus_req_i.addr(2) = '0') then -- control register
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ctrl.enable <= bus_req_i.data(ctrl_en_c);
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ctrl.mack <= bus_req_i.data(ctrl_mack_c);
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ctrl.csen <= bus_req_i.data(ctrl_csen_c);
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ctrl.prsc <= bus_req_i.data(ctrl_prsc2_c downto ctrl_prsc0_c);
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ctrl.cdiv <= bus_req_i.data(ctrl_cdiv3_c downto ctrl_cdiv0_c);
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trig_start <= bus_req_i.data(ctrl_start_c); -- issue START condition
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trig_stop <= bus_req_i.data(ctrl_stop_c); -- issue STOP condition
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else -- data register
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trig_data <= '1'; -- start data transmission
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end if;
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-- read access --
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else
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if (bus_req_i.addr(2) = '0') then -- control register
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bus_rsp_o.data(ctrl_en_c) <= ctrl.enable;
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bus_rsp_o.data(ctrl_mack_c) <= ctrl.mack;
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bus_rsp_o.data(ctrl_csen_c) <= ctrl.csen;
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bus_rsp_o.data(ctrl_prsc2_c downto ctrl_prsc0_c) <= ctrl.prsc;
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bus_rsp_o.data(ctrl_cdiv3_c downto ctrl_cdiv0_c) <= ctrl.cdiv;
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--
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bus_rsp_o.data(ctrl_claimed_c) <= arbiter.claimed;
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bus_rsp_o.data(ctrl_ack_c) <= not arbiter.rtx_sreg(0);
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bus_rsp_o.data(ctrl_busy_c) <= arbiter.busy;
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else -- data register
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bus_rsp_o.data(7 downto 0) <= arbiter.rtx_sreg(8 downto 1);
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end if;
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end if;
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end if;
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end if;
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end process bus_access;
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-- Clock Generation -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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clock_generator: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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clk_gen.tick <= '0';
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clk_gen.cnt <= (others => '0');
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elsif rising_edge(clk_i) then
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if (ctrl.enable = '0') then -- reset/disabled
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clk_gen.tick <= '0';
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clk_gen.cnt <= (others => '0');
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else
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clk_gen.tick <= '0'; -- default
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if (clkgen_i(to_integer(unsigned(ctrl.prsc))) = '1') then -- pre-scaled clock
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if (clk_gen.cnt = ctrl.cdiv) then -- clock divider for fine-tuning
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clk_gen.tick <= '1';
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clk_gen.cnt <= (others => '0');
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else
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clk_gen.cnt <= std_ulogic_vector(unsigned(clk_gen.cnt) + 1);
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end if;
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end if;
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end if;
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end if;
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end process clock_generator;
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-- clock generator enable --
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clkgen_en_o <= ctrl.enable;
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-- generate four non-overlapping clock phases --
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phase_generator: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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clk_gen.phase_gen <= (others => '0');
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clk_gen.phase_gen_ff <= (others => '0');
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elsif rising_edge(clk_i) then
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clk_gen.phase_gen_ff <= clk_gen.phase_gen;
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if (arbiter.state(2) = '0') or (arbiter.state(1 downto 0) = "00") then -- offline or idle
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clk_gen.phase_gen <= "0001"; -- make sure to start with a new phase
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else
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if (clk_gen.tick = '1') and (clk_gen.halt = '0') then -- clock tick and no clock stretching detected
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clk_gen.phase_gen <= clk_gen.phase_gen(2 downto 0) & clk_gen.phase_gen(3); -- rotate left
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end if;
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end if;
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end if;
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end process phase_generator;
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-- TWI bus signals are set/sampled using 4 clock phases --
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clk_gen.phase(0) <= clk_gen.phase_gen_ff(0) and (not clk_gen.phase_gen(0)); -- first step
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clk_gen.phase(1) <= clk_gen.phase_gen_ff(1) and (not clk_gen.phase_gen(1));
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clk_gen.phase(2) <= clk_gen.phase_gen_ff(2) and (not clk_gen.phase_gen(2));
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clk_gen.phase(3) <= clk_gen.phase_gen_ff(3) and (not clk_gen.phase_gen(3)); -- last step
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-- Clock Stretching Detector --
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-- controller wants to pull SCL high, but SCL is pulled low by peripheral --
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clk_gen.halt <= '1' when (io_con.scl_out = '1') and (io_con.scl_in_ff(1) = '0') and (ctrl.csen = '1') else '0';
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-- TWI Transceiver ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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twi_engine: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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io_con.sda_in_ff <= (others => '0');
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io_con.scl_in_ff <= (others => '0');
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io_con.sda_out <= '0';
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io_con.scl_out <= '0';
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irq_o <= '0';
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arbiter.state <= (others => '0');
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arbiter.bitcnt <= (others => '0');
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arbiter.state_nxt <= (others => '0');
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arbiter.rtx_sreg <= (others => '0');
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elsif rising_edge(clk_i) then
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-- input synchronizer --
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io_con.sda_in_ff <= io_con.sda_in_ff(0) & io_con.sda_in;
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io_con.scl_in_ff <= io_con.scl_in_ff(0) & io_con.scl_in;
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-- interrupt --
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if (arbiter.state = "111") and (arbiter.rtx_done = '1') then -- transmission done
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irq_o <= '1';
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else
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irq_o <= '0';
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end if;
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-- serial engine --
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arbiter.state(2) <= ctrl.enable; -- module enabled?
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case arbiter.state is
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when "100" => -- IDLE: waiting for operation requests
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-- ------------------------------------------------------------
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arbiter.bitcnt <= (others => '0');
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if (trig_start = '1') then -- issue START condition
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arbiter.state_nxt <= "01";
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elsif (trig_stop = '1') then -- issue STOP condition
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arbiter.state_nxt <= "10";
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elsif (trig_data = '1') then -- start a data transmission
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-- one bit extra for ACK: issued by controller if ctrl_mack_c is set,
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-- sampled from peripheral if ctrl_mack_c is cleared
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-- data_i will stay unchanged for min. 1 cycle after WREN has returned to low again
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arbiter.rtx_sreg <= bus_req_i.data(7 downto 0) & (not ctrl.mack);
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arbiter.state_nxt <= "11";
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end if;
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-- start operation on next TWI clock pulse --
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if (arbiter.state_nxt /= "00") and (clk_gen.tick = '1') then
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arbiter.state(1 downto 0) <= arbiter.state_nxt;
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end if;
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when "101" => -- START: generate (repeated) START condition
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-- ------------------------------------------------------------
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arbiter.state_nxt <= "00"; -- no operation pending anymore
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if (clk_gen.phase(0) = '1') then
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io_con.sda_out <= '1';
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elsif (clk_gen.phase(1) = '1') then
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io_con.sda_out <= '0';
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end if;
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--
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if (clk_gen.phase(0) = '1') then
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io_con.scl_out <= '1';
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elsif (clk_gen.phase(3) = '1') then
|
||
|
|
io_con.scl_out <= '0';
|
||
|
|
arbiter.state(1 downto 0) <= "00"; -- go back to IDLE
|
||
|
|
end if;
|
||
|
|
|
||
|
|
when "110" => -- STOP: generate STOP condition
|
||
|
|
-- ------------------------------------------------------------
|
||
|
|
arbiter.state_nxt <= "00"; -- no operation pending anymore
|
||
|
|
if (clk_gen.phase(0) = '1') then
|
||
|
|
io_con.sda_out <= '0';
|
||
|
|
elsif (clk_gen.phase(3) = '1') then
|
||
|
|
io_con.sda_out <= '1';
|
||
|
|
arbiter.state(1 downto 0) <= "00"; -- go back to IDLE
|
||
|
|
end if;
|
||
|
|
--
|
||
|
|
if (clk_gen.phase(0) = '1') then
|
||
|
|
io_con.scl_out <= '0';
|
||
|
|
elsif (clk_gen.phase(1) = '1') then
|
||
|
|
io_con.scl_out <= '1';
|
||
|
|
end if;
|
||
|
|
|
||
|
|
when "111" => -- TRANSMISSION: send/receive byte + ACK/NACK/MACK
|
||
|
|
-- ------------------------------------------------------------
|
||
|
|
arbiter.state_nxt <= "00"; -- no operation pending anymore
|
||
|
|
-- SCL clocking --
|
||
|
|
if (clk_gen.phase(0) = '1') or (clk_gen.phase(3) = '1') then
|
||
|
|
io_con.scl_out <= '0'; -- set SCL low after transmission to keep bus claimed
|
||
|
|
elsif (clk_gen.phase(1) = '1') then -- first half + second half of valid data strobe
|
||
|
|
io_con.scl_out <= '1';
|
||
|
|
end if;
|
||
|
|
-- SDA output --
|
||
|
|
if (arbiter.rtx_done = '1') then
|
||
|
|
io_con.sda_out <= '0'; -- set SDA low after transmission to keep bus claimed
|
||
|
|
elsif (clk_gen.phase(0) = '1') then
|
||
|
|
io_con.sda_out <= arbiter.rtx_sreg(8); -- MSB first
|
||
|
|
end if;
|
||
|
|
-- SDA input --
|
||
|
|
if (clk_gen.phase(2) = '1') then
|
||
|
|
arbiter.rtx_sreg <= arbiter.rtx_sreg(7 downto 0) & io_con.sda_in_ff(1); -- sample SDA input and shift left
|
||
|
|
end if;
|
||
|
|
-- bit counter --
|
||
|
|
if (clk_gen.phase(3) = '1') then
|
||
|
|
arbiter.bitcnt <= std_ulogic_vector(unsigned(arbiter.bitcnt) + 1);
|
||
|
|
end if;
|
||
|
|
-- transmission done --
|
||
|
|
if (arbiter.rtx_done = '1') then
|
||
|
|
arbiter.state(1 downto 0) <= "00"; -- go back to IDLE
|
||
|
|
end if;
|
||
|
|
|
||
|
|
when others => -- "0--" OFFLINE: TWI deactivated, bus unclaimed
|
||
|
|
-- ------------------------------------------------------------
|
||
|
|
io_con.scl_out <= '1'; -- SCL driven by pull-up resistor
|
||
|
|
io_con.sda_out <= '1'; -- SDA driven by pull-up resistor
|
||
|
|
arbiter.rtx_sreg <= (others => '0'); -- make DATA and ACK _defined_ after reset
|
||
|
|
arbiter.state_nxt <= "00"; -- no operation pending anymore
|
||
|
|
arbiter.state(1 downto 0) <= "00"; -- stay here, go to IDLE when activated
|
||
|
|
|
||
|
|
end case;
|
||
|
|
end if;
|
||
|
|
end process twi_engine;
|
||
|
|
|
||
|
|
-- transmit 8 data bits + 1 ACK bit and wait for another clock phase --
|
||
|
|
arbiter.rtx_done <= '1' when (arbiter.bitcnt = "1001") and (clk_gen.phase(0) = '1') else '0';
|
||
|
|
|
||
|
|
-- arbiter busy? --
|
||
|
|
arbiter.busy <= arbiter.state(1) or arbiter.state(0) or -- operation in progress
|
||
|
|
arbiter.state_nxt(1) or arbiter.state_nxt(0); -- pending operation
|
||
|
|
|
||
|
|
-- check if the TWI bus is currently claimed (by this module or any other controller) --
|
||
|
|
arbiter.claimed <= '1' when (arbiter.busy = '1') or ((io_con.sda_in_ff(1) = '0') and (io_con.scl_in_ff(1) = '0')) else '0';
|
||
|
|
|
||
|
|
|
||
|
|
-- Tri-State Driver Interface -------------------------------------------------------------
|
||
|
|
-- -------------------------------------------------------------------------------------------
|
||
|
|
twi_sda_o <= io_con.sda_out; -- NOTE: signal lines can only be actively driven low
|
||
|
|
twi_scl_o <= io_con.scl_out;
|
||
|
|
io_con.sda_in <= to_stdulogic(to_bit(twi_sda_i)); -- "to_bit" to avoid hardware-vs-simulation mismatch
|
||
|
|
io_con.scl_in <= to_stdulogic(to_bit(twi_scl_i)); -- "to_bit" to avoid hardware-vs-simulation mismatch
|
||
|
|
|
||
|
|
|
||
|
|
end neorv32_twi_rtl;
|