225 lines
12 KiB
VHDL
225 lines
12 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # ********************************************************************************************* #
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-- # Wishbone accesses can have a response latency of up to BUS_TIMEOUT - 1 cycles or an infinite #
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-- # response time if BUS_TIMEOUT = 0 (not recommended!). #
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-- # #
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-- # The Wishbone gateway registers all outgoing signals. These signals will remain stable (gated) #
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-- # if there is no active Wishbone access. By default, also the incoming signals are registered, #
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-- # too. this can be disabled by setting ASYNC_RX = false. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_wishbone is
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generic (
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-- Wishbone Interface Configuration --
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BUS_TIMEOUT : natural; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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PIPE_MODE : boolean; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
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BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
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ASYNC_RX : boolean; -- use register buffer for RX data when false
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ASYNC_TX : boolean -- use register buffer for TX data when false
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);
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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--
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wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_we_o : out std_ulogic; -- read/write
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_stb_o : out std_ulogic; -- strobe
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_err_i : in std_ulogic -- transfer error
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);
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end neorv32_wishbone;
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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-- auto-configuration --
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constant async_rx_c : boolean := ASYNC_RX and PIPE_MODE; -- classic mode requires a sync RX path for the inter-cycle pause
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-- timeout enable --
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constant timeout_en_c : boolean := boolean(BUS_TIMEOUT /= 0); -- timeout enabled if BUS_TIMEOUT > 0
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-- bus arbiter
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type ctrl_t is record
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state : std_ulogic;
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state_ff : std_ulogic;
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we : std_ulogic;
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adr : std_ulogic_vector(31 downto 0);
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wdat : std_ulogic_vector(31 downto 0);
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rdat : std_ulogic_vector(31 downto 0);
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sel : std_ulogic_vector(03 downto 0);
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ack : std_ulogic;
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err : std_ulogic;
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT) downto 0);
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src : std_ulogic;
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priv : std_ulogic;
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end record;
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signal ctrl : ctrl_t;
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signal stb_int : std_ulogic;
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signal cyc_int : std_ulogic;
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signal rdata : std_ulogic_vector(31 downto 0);
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-- endianness conversion --
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signal end_wdata : std_ulogic_vector(31 downto 0);
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signal end_byteen : std_ulogic_vector(03 downto 0);
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-- async RX gating --
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signal ack_gated : std_ulogic;
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signal err_gated : std_ulogic;
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signal rdata_gated : std_ulogic_vector(31 downto 0);
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begin
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-- Configuration Info ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert false report
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"[NEORV32] Ext. Bus Interface (WISHBONE) - " &
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cond_sel_string_f(PIPE_MODE, "PIPELINED", "CLASSIC/STANDARD") & " Wishbone protocol, " &
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cond_sel_string_f(boolean(BUS_TIMEOUT /= 0), "auto-timeout, ", "NO auto-timeout, ") &
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cond_sel_string_f(BIG_ENDIAN, "BIG", "LITTLE") & "-endian byte order, " &
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cond_sel_string_f(async_rx_c, "ASYNC ", "registered ") & "RX, " &
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cond_sel_string_f(ASYNC_TX, "ASYNC ", "registered ") & "TX"
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severity note;
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-- async RX override warning --
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assert not ((ASYNC_RX = true) and (async_rx_c = false)) report
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"[NEORV32] Ext. Bus Interface - Non-pipelined/standard mode requires sync RX (auto-disabling async RX)." severity warning;
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-- zero timeout warning --
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assert not (BUS_TIMEOUT = 0) report
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"[NEORV32] Ext. Bus Interface - NO auto-timeout defined; can cause permanent CPU stall!" severity warning;
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_arbiter: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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ctrl.state <= '0';
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ctrl.state_ff <= '0';
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ctrl.we <= '0';
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ctrl.adr <= (others => '0');
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ctrl.wdat <= (others => '0');
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ctrl.rdat <= (others => '0');
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ctrl.sel <= (others => '0');
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ctrl.timeout <= (others => '0');
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ctrl.ack <= '0';
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ctrl.err <= '0';
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ctrl.src <= '0';
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ctrl.priv <= '0';
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elsif rising_edge(clk_i) then
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-- defaults --
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ctrl.state_ff <= ctrl.state;
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ctrl.rdat <= (others => '0'); -- required for internal output gating
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ctrl.ack <= '0';
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ctrl.err <= '0';
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ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)+1));
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-- state machine --
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if (ctrl.state = '0') then -- IDLE, waiting for host request
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-- ------------------------------------------------------------
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if (bus_req_i.stb = '1') then -- request
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-- buffer (and gate) all outgoing signals --
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ctrl.we <= bus_req_i.rw;
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ctrl.adr <= bus_req_i.addr;
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ctrl.src <= bus_req_i.src;
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ctrl.priv <= bus_req_i.priv;
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ctrl.wdat <= end_wdata;
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ctrl.sel <= end_byteen;
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ctrl.state <= '1';
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end if;
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else -- BUSY, transfer in progress
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-- ------------------------------------------------------------
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if (ctrl.we = '0') then -- sync output gate (keep output zero if write access)
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ctrl.rdat <= wb_dat_i;
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end if;
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if (wb_ack_i = '1') then -- normal bus termination
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ctrl.ack <= '1';
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ctrl.state <= '0';
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elsif (wb_err_i = '1') or ((timeout_en_c = true) and (or_reduce_f(ctrl.timeout) = '0')) then -- bus error or timeout
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ctrl.err <= '1';
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ctrl.state <= '0';
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end if;
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-- timeout counter --
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if (timeout_en_c = true) then
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ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
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end if;
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end if;
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end if;
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end process bus_arbiter;
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-- endianness conversion --
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end_wdata <= bswap32_f(bus_req_i.data) when (BIG_ENDIAN = true) else bus_req_i.data;
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end_byteen <= bit_rev_f(bus_req_i.ben) when (BIG_ENDIAN = true) else bus_req_i.ben;
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-- host access --
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ack_gated <= wb_ack_i when (ctrl.state = '1') else '0'; -- CPU ACK gate for "async" RX
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err_gated <= wb_err_i when (ctrl.state = '1') else '0'; -- CPU ERR gate for "async" RX
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rdata_gated <= wb_dat_i when (ctrl.state = '1') and (ctrl.we = '0') else (others => '0'); -- async output gate
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rdata <= ctrl.rdat when (async_rx_c = false) else rdata_gated;
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bus_rsp_o.data <= rdata when (BIG_ENDIAN = false) else bswap32_f(rdata); -- endianness conversion
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bus_rsp_o.ack <= ctrl.ack when (async_rx_c = false) else ack_gated;
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bus_rsp_o.err <= ctrl.err when (async_rx_c = false) else err_gated;
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-- wishbone interface --
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wb_tag_o(0) <= bus_req_i.priv when (ASYNC_TX = true) else ctrl.priv; -- 0 = unprivileged (U-mode), 1 = privileged (M-mode)
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wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
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wb_tag_o(2) <= bus_req_i.src when (ASYNC_TX = true) else ctrl.src; -- 0 = data access, 1 = instruction access
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stb_int <= bus_req_i.stb when (ASYNC_TX = true) else (ctrl.state and (not ctrl.state_ff));
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cyc_int <= (bus_req_i.stb or ctrl.state) when (ASYNC_TX = true) else ctrl.state;
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wb_adr_o <= bus_req_i.addr when (ASYNC_TX = true) else ctrl.adr;
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wb_dat_o <= bus_req_i.data when (ASYNC_TX = true) else ctrl.wdat;
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wb_we_o <= bus_req_i.rw when (ASYNC_TX = true) else ctrl.we;
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wb_sel_o <= end_byteen when (ASYNC_TX = true) else ctrl.sel;
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wb_stb_o <= stb_int when (PIPE_MODE = true) else cyc_int;
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wb_cyc_o <= cyc_int;
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end neorv32_wishbone_rtl;
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