117 lines
7.0 KiB
VHDL
117 lines
7.0 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Minimal setup with the bootloader enabled >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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entity neorv32_ProcessorTop_MinimalBoot is
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generic (
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 64*1024; -- size of processor-internal instruction memory in bytes
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-- Internal Data memory --
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 64*1024; -- size of processor-internal data memory in bytes
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-- Processor peripherals --
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IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64)
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IO_PWM_NUM_CH : natural := 3 -- number of PWM channels to implement (0..12); 0 = disabled
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);
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port (
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-- Global control --
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clk_i : in std_logic;
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rstn_i : in std_logic;
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-- GPIO (available if IO_GPIO_EN = true) --
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gpio_o : out std_ulogic_vector(3 downto 0);
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart_txd_o : out std_ulogic; -- UART0 send data
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uart_rxd_i : in std_ulogic := '0'; -- UART0 receive data
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0)
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);
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end entity;
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architecture neorv32_ProcessorTop_MinimalBoot_rtl of neorv32_ProcessorTop_MinimalBoot is
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-- internal IO connection --
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signal con_gpio_o : std_ulogic_vector(63 downto 0);
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signal con_pwm_o : std_ulogic_vector(11 downto 0);
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begin
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-- The core of the problem ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_inst: entity neorv32.neorv32_top
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generic map (
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-- General --
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CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
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INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
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-- Internal Data memory --
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MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
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-- Processor peripherals --
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IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64)
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_PWM_NUM_CH => IO_PWM_NUM_CH -- number of PWM channels to implement (0..12); 0 = disabled
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)
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port map (
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-- Global control --
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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-- GPIO (available if IO_GPIO_NUM > 0) --
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gpio_o => con_gpio_o, -- parallel output
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gpio_i => (others => '0'), -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o => uart_txd_o, -- UART0 send data
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uart0_rxd_i => uart_rxd_i, -- UART0 receive data
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o => con_pwm_o -- pwm channels
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);
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-- GPIO --
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gpio_o <= con_gpio_o(3 downto 0);
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-- PWM --
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pwm_o <= con_pwm_o(IO_PWM_NUM_CH-1 downto 0);
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end architecture;
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