418 lines
21 KiB
VHDL
418 lines
21 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Processor Top Entity with AvalonMM Compatible Host Interface >> #
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-- # ********************************************************************************************* #
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-- # (c) "AvalonMM", "Qsys", "MegaWizard" and "Platform Designer" are trademarks of Intel corp. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_top_avalonmm is
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generic (
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-- General --
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CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
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VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
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INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
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CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16)
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PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
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-- Internal Instruction memory (IMEM) --
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MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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-- Internal Cache memory (iCACHE) --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- Internal Data Cache (dCACHE) --
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DCACHE_EN : boolean := false; -- implement data cache
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DCACHE_NUM_BLOCKS : natural := 4; -- d-cache: number of blocks (min 1), has to be a power of 2
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DCACHE_BLOCK_SIZE : natural := 64; -- d-cache: block size in bytes (min 4), has to be a power of 2
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-- Execute in-place module (XIP) --
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XIP_EN : boolean := false; -- implement execute in place module (XIP)?
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XIP_CACHE_EN : boolean := false; -- implement XIP cache?
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XIP_CACHE_NUM_BLOCKS : natural range 1 to 256 := 8; -- number of blocks (min 1), has to be a power of 2
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XIP_CACHE_BLOCK_SIZE : natural range 1 to 2**16 := 256; -- block size in bytes (min 4), has to be a power of 2
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-- External Interrupts Controller (XIRQ) --
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XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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-- Processor peripherals --
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IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64)
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IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_SPI_FIFO : natural := 1; -- SPI RTX fifo depth, has to be a power of two, min 1
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..12); 0 = disabled
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_FIFO : natural := 1; -- TRNG fifo depth, has to be a power of two, min 1
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
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IO_ONEWIRE_EN : boolean := false -- implement 1-wire interface (ONEWIRE)?
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);
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port (
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-- Global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional)
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jtag_tck_i : in std_ulogic := 'U'; -- serial clock
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jtag_tdi_i : in std_ulogic := 'U'; -- serial data input
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jtag_tdo_o : out std_ulogic; -- serial data output
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jtag_tms_i : in std_ulogic := 'U'; -- mode select
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-- AvalonMM interface
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read_o : out std_logic;
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write_o : out std_logic;
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waitrequest_i : in std_logic := '0';
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byteenable_o : out std_logic_vector(3 downto 0);
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address_o : out std_logic_vector(31 downto 0);
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writedata_o : out std_logic_vector(31 downto 0);
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readdata_i : in std_logic_vector(31 downto 0) := (others => '0');
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-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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xip_csn_o : out std_ulogic; -- chip-select, low-active
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xip_clk_o : out std_ulogic; -- serial clock
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xip_dat_i : in std_ulogic := 'L'; -- device data input
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xip_dat_o : out std_ulogic; -- controller data output
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-- GPIO (available if IO_GPIO_EN = true) --
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gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
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gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data
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uart0_rts_o : out std_ulogic; -- HW flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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uart0_cts_i : in std_ulogic := 'L'; -- HW flow control: UART0.TX allowed to transmit, low-active, optional
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-- secondary UART1 (available if IO_UART1_EN = true) --
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uart1_txd_o : out std_ulogic; -- UART1 send data
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uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data
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uart1_rts_o : out std_ulogic; -- HW flow control: UART1.RX ready to receive ("RTR"), low-active, optional
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uart1_cts_i : in std_ulogic := 'L'; -- HW flow control: UART1.TX allowed to transmit, low-active, optional
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-- SPI (available if IO_SPI_EN = true) --
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spi_clk_o : out std_ulogic; -- SPI serial clock
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spi_dat_o : out std_ulogic; -- controller data out, peripheral data in
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spi_dat_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
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-- TWI (available if IO_TWI_EN = true) --
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twi_sda_i : in std_ulogic := 'H'; -- serial data line sense input
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twi_sda_o : out std_ulogic; -- serial data line output (pull low only)
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twi_scl_i : in std_ulogic := 'H'; -- serial clock line sense input
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twi_scl_o : out std_ulogic; -- serial clock line output (pull low only)
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-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
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onewire_i : in std_ulogic := 'H'; -- 1-wire bus sense input
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onewire_o : out std_ulogic; -- 1-wire bus output (pull low only)
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o : out std_ulogic_vector(11 downto 0); -- pwm channels
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
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cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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neoled_o : out std_ulogic; -- async serial data line
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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xirq_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels
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-- CPU interrupts --
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mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
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msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
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mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
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);
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end neorv32_top_avalonmm;
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architecture neorv32_top_avalonmm_rtl of neorv32_top_avalonmm is
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-- Wishbone bus interface (available if MEM_EXT_EN = true) --
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signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag
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signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address
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signal wb_dat_i : std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data
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signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data
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signal wb_we_o : std_ulogic; -- read/write
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signal wb_sel_o : std_ulogic_vector(03 downto 0); -- byte enable
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signal wb_stb_o : std_ulogic; -- strobe
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signal wb_cyc_o : std_ulogic; -- valid cycle
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signal wb_ack_i : std_ulogic := 'L'; -- transfer acknowledge
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signal wb_err_i : std_ulogic := 'L'; -- transfer error
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begin
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neorv32_top_map : neorv32_top
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generic map (
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-- General --
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CLOCK_FREQUENCY => CLOCK_FREQUENCY,
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HART_ID => HART_ID,
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VENDOR_ID => VENDOR_ID,
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN,
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B,
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C,
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E,
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
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CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,
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CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm,
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul,
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CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu,
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-- Extension Options --
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FAST_MUL_EN => FAST_MUL_EN,
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FAST_SHIFT_EN => FAST_SHIFT_EN,
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS => PMP_NUM_REGIONS,
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => HPM_NUM_CNTS,
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HPM_CNT_WIDTH => HPM_CNT_WIDTH,
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-- Internal Instruction memory (IMEM) --
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MEM_INT_IMEM_EN => MEM_INT_IMEM_EN,
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MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE,
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN => MEM_INT_IMEM_EN,
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MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE,
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-- Internal Cache memory (iCACHE) --
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ICACHE_EN => ICACHE_EN,
|
||
|
|
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS,
|
||
|
|
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE,
|
||
|
|
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY,
|
||
|
|
|
||
|
|
-- Internal Data Cache (dCACHE) --
|
||
|
|
DCACHE_EN => DCACHE_EN,
|
||
|
|
DCACHE_NUM_BLOCKS => DCACHE_NUM_BLOCKS,
|
||
|
|
DCACHE_BLOCK_SIZE => DCACHE_BLOCK_SIZE,
|
||
|
|
|
||
|
|
-- External memory interface (WISHBONE) --
|
||
|
|
MEM_EXT_EN => true,
|
||
|
|
MEM_EXT_TIMEOUT => 0,
|
||
|
|
MEM_EXT_PIPE_MODE => false,
|
||
|
|
MEM_EXT_BIG_ENDIAN => false,
|
||
|
|
MEM_EXT_ASYNC_RX => false,
|
||
|
|
MEM_EXT_ASYNC_TX => false,
|
||
|
|
|
||
|
|
-- Execute in-place module (XIP) --
|
||
|
|
XIP_EN => XIP_EN,
|
||
|
|
XIP_CACHE_EN => XIP_CACHE_EN,
|
||
|
|
XIP_CACHE_NUM_BLOCKS => XIP_CACHE_NUM_BLOCKS,
|
||
|
|
XIP_CACHE_BLOCK_SIZE => XIP_CACHE_BLOCK_SIZE,
|
||
|
|
|
||
|
|
-- External Interrupts Controller (XIRQ) --
|
||
|
|
XIRQ_NUM_CH => XIRQ_NUM_CH,
|
||
|
|
XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE,
|
||
|
|
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY,
|
||
|
|
|
||
|
|
-- Processor peripherals --
|
||
|
|
IO_GPIO_NUM => IO_GPIO_NUM,
|
||
|
|
IO_MTIME_EN => IO_MTIME_EN,
|
||
|
|
IO_UART0_EN => IO_UART0_EN,
|
||
|
|
IO_UART0_RX_FIFO => IO_UART0_RX_FIFO,
|
||
|
|
IO_UART0_TX_FIFO => IO_UART0_TX_FIFO,
|
||
|
|
IO_UART1_EN => IO_UART1_EN,
|
||
|
|
IO_UART1_RX_FIFO => IO_UART1_RX_FIFO,
|
||
|
|
IO_UART1_TX_FIFO => IO_UART1_TX_FIFO,
|
||
|
|
IO_SPI_EN => IO_SPI_EN,
|
||
|
|
IO_SPI_FIFO => IO_SPI_FIFO,
|
||
|
|
IO_TWI_EN => IO_TWI_EN,
|
||
|
|
IO_PWM_NUM_CH => IO_PWM_NUM_CH,
|
||
|
|
IO_WDT_EN => IO_WDT_EN,
|
||
|
|
IO_TRNG_EN => IO_TRNG_EN,
|
||
|
|
IO_TRNG_FIFO => IO_TRNG_FIFO,
|
||
|
|
IO_CFS_EN => IO_CFS_EN,
|
||
|
|
IO_CFS_CONFIG => IO_CFS_CONFIG,
|
||
|
|
IO_CFS_IN_SIZE => IO_CFS_IN_SIZE,
|
||
|
|
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE,
|
||
|
|
IO_NEOLED_EN => IO_NEOLED_EN,
|
||
|
|
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO,
|
||
|
|
IO_GPTMR_EN => IO_GPTMR_EN,
|
||
|
|
IO_ONEWIRE_EN => IO_ONEWIRE_EN
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
-- Global control --
|
||
|
|
clk_i => clk_i,
|
||
|
|
rstn_i => rstn_i,
|
||
|
|
|
||
|
|
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
|
||
|
|
jtag_trst_i => jtag_trst_i,
|
||
|
|
jtag_tck_i => jtag_tck_i,
|
||
|
|
jtag_tdi_i => jtag_tdi_i,
|
||
|
|
jtag_tdo_o => jtag_tdo_o,
|
||
|
|
jtag_tms_i => jtag_tms_i,
|
||
|
|
|
||
|
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
||
|
|
wb_tag_o => wb_tag_o,
|
||
|
|
wb_adr_o => wb_adr_o,
|
||
|
|
wb_dat_i => wb_dat_i,
|
||
|
|
wb_dat_o => wb_dat_o,
|
||
|
|
wb_we_o => wb_we_o,
|
||
|
|
wb_sel_o => wb_sel_o,
|
||
|
|
wb_stb_o => wb_stb_o,
|
||
|
|
wb_cyc_o => wb_cyc_o,
|
||
|
|
wb_ack_i => wb_ack_i,
|
||
|
|
wb_err_i => wb_err_i,
|
||
|
|
|
||
|
|
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
|
||
|
|
xip_csn_o => xip_csn_o,
|
||
|
|
xip_clk_o => xip_clk_o,
|
||
|
|
xip_dat_i => xip_dat_i,
|
||
|
|
xip_dat_o => xip_dat_o,
|
||
|
|
|
||
|
|
-- GPIO (available if IO_GPIO_EN = true) --
|
||
|
|
gpio_o => gpio_o,
|
||
|
|
gpio_i => gpio_i,
|
||
|
|
|
||
|
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
||
|
|
uart0_txd_o => uart0_txd_o,
|
||
|
|
uart0_rxd_i => uart0_rxd_i,
|
||
|
|
uart0_rts_o => uart0_rts_o,
|
||
|
|
uart0_cts_i => uart0_cts_i,
|
||
|
|
|
||
|
|
-- secondary UART1 (available if IO_UART1_EN = true) --
|
||
|
|
uart1_txd_o => uart1_txd_o,
|
||
|
|
uart1_rxd_i => uart1_rxd_i,
|
||
|
|
uart1_rts_o => uart1_rts_o,
|
||
|
|
uart1_cts_i => uart1_cts_i,
|
||
|
|
|
||
|
|
-- SPI (available if IO_SPI_EN = true) --
|
||
|
|
spi_clk_o => spi_clk_o,
|
||
|
|
spi_dat_o => spi_dat_o,
|
||
|
|
spi_dat_i => spi_dat_i,
|
||
|
|
spi_csn_o => spi_csn_o,
|
||
|
|
|
||
|
|
-- TWI (available if IO_TWI_EN = true) --
|
||
|
|
twi_sda_i => twi_sda_i,
|
||
|
|
twi_sda_o => twi_sda_o,
|
||
|
|
twi_scl_i => twi_scl_i,
|
||
|
|
twi_scl_o => twi_scl_o,
|
||
|
|
|
||
|
|
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
|
||
|
|
onewire_i => onewire_i,
|
||
|
|
onewire_o => onewire_o,
|
||
|
|
|
||
|
|
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
||
|
|
pwm_o => pwm_o,
|
||
|
|
|
||
|
|
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
||
|
|
cfs_in_i => cfs_in_i,
|
||
|
|
cfs_out_o => cfs_out_o,
|
||
|
|
|
||
|
|
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
||
|
|
neoled_o => neoled_o,
|
||
|
|
|
||
|
|
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
||
|
|
xirq_i => xirq_i,
|
||
|
|
|
||
|
|
-- CPU interrupts --
|
||
|
|
mtime_irq_i => mtime_irq_i,
|
||
|
|
msw_irq_i => msw_irq_i,
|
||
|
|
mext_irq_i => mext_irq_i
|
||
|
|
);
|
||
|
|
|
||
|
|
-- Wishbone to AvalonMM bridge
|
||
|
|
read_o <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0';
|
||
|
|
write_o <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0';
|
||
|
|
address_o <= std_logic_vector(wb_adr_o);
|
||
|
|
writedata_o <= std_logic_vector(wb_dat_o);
|
||
|
|
byteenable_o <= std_logic_vector(wb_sel_o);
|
||
|
|
|
||
|
|
wb_dat_i <= std_ulogic_vector(readdata_i);
|
||
|
|
wb_ack_i <= not(waitrequest_i);
|
||
|
|
wb_err_i <= '0';
|
||
|
|
|
||
|
|
end neorv32_top_avalonmm_rtl;
|