241 lines
10 KiB
ArmAsm
241 lines
10 KiB
ArmAsm
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/* ################################################################################################# */
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/* # << NEORV32 - crt0.S Start-Up Code >> # */
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/* # ********************************************************************************************* # */
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/* # BSD 3-Clause License # */
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/* # # */
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/* # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 # */
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/* # Copyright (c) 2024, Stephan Nolting. All rights reserved. # */
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/* # # */
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/* # Redistribution and use in source and binary forms, with or without modification, are # */
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/* # permitted provided that the following conditions are met: # */
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/* # # */
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/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */
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/* # conditions and the following disclaimer. # */
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/* # # */
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/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */
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/* # conditions and the following disclaimer in the documentation and/or other materials # */
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/* # provided with the distribution. # */
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/* # # */
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/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */
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/* # endorse or promote products derived from this software without specific prior written # */
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/* # permission. # */
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/* # # */
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/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */
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/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */
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/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */
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/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */
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/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
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/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */
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/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */
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/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */
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/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */
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/* ################################################################################################# */
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.file "crt0.S"
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.section .text.crt0
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.balign 4
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.option norvc // only 32-bit instructions
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.global _start
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.global __crt0_entry
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.global __crt0_main_exit
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_start:
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__crt0_entry:
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.cfi_startproc
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.cfi_undefined ra
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// ************************************************************************************************
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// Setup CPU core CSRs
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// ************************************************************************************************
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__crt0_cpu_csr_init:
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li x1, 0x00001800 // mstatus.mpp = machine-mode
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csrw mstatus, x1
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la x1, __crt0_trap_handler // configure early-boot trap handler
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csrw mtvec, x1
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csrw mie, zero // disable all interrupt sources
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// ************************************************************************************************
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// Initialize integer register file
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// ************************************************************************************************
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__crt0_pointer_init:
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.option push
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.option norelax
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// setup pointers using linker script symbols
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la x4, __crt0_stack_end // stack pointer
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andi sp, x4, 0xfffffffc // word-aligned
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la x5, __global_pointer$ // global pointer
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andi gp, x5, 0xfffffffc // word-aligned
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.option pop
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__crt0_reg_file_init:
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//addi x0, x0, 0 // hardwired to zero
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//addi x1, x0, 0 // implicitly initialized within crt0
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//addi x2, x0, 0 // stack pointer sp
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//addi x3, x0, 0 // global pointer gp
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//addi x4, x0, 0 // implicitly initialized within crt0
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//addi x5, x0, 0 // implicitly initialized within crt0
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addi x6, x0, 0
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addi x7, x0, 0
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addi x8, x0, 0
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addi x9, x0, 0
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//addi x10, x0, 0 // implicitly initialized within crt0
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//addi x11, x0, 0 // implicitly initialized within crt0
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//addi x12, x0, 0 // implicitly initialized within crt0
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//addi x13, x0, 0 // implicitly initialized within crt0
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//addi x14, x0, 0 // implicitly initialized within crt0
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//addi x15, x0, 0 // implicitly initialized within crt0
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#ifndef __riscv_32e // initialize upper half (if E extension is not implemented)
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addi x16, x0, 0
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addi x17, x0, 0
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addi x18, x0, 0
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addi x19, x0, 0
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addi x20, x0, 0
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addi x21, x0, 0
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addi x22, x0, 0
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addi x23, x0, 0
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addi x24, x0, 0
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addi x25, x0, 0
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addi x26, x0, 0
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addi x27, x0, 0
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addi x28, x0, 0
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addi x29, x0, 0
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addi x30, x0, 0
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addi x31, x0, 0
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#endif
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// ************************************************************************************************
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// Copy initialized .data section from ROM to RAM (word-wise, section begins and ends on word boundary)
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// ************************************************************************************************
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__crt0_copy_data:
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la x11, __crt0_copy_data_src_begin // start of data area (copy source)
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la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)
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la x13, __crt0_copy_data_dst_end // last address of destination data area
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beq x11, x12, __crt0_copy_data_loop_end // nothing to do if source and destination address are the same
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__crt0_copy_data_loop:
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bge x12, x13, __crt0_copy_data_loop_end
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lw x14, 0(x11)
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sw x14, 0(x12)
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addi x11, x11, 4
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addi x12, x12, 4
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j __crt0_copy_data_loop
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__crt0_copy_data_loop_end:
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// ************************************************************************************************
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// Clear .bss section (word-wise, section begins and ends on word boundary)
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// ************************************************************************************************
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__crt0_clear_bss:
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la x14, __crt0_bss_start
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la x15, __crt0_bss_end
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__crt0_clear_bss_loop:
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bge x14, x15, __crt0_clear_bss_loop_end
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sw zero, 0(x14)
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addi x14, x14, 4
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j __crt0_clear_bss_loop
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__crt0_clear_bss_loop_end:
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// ************************************************************************************************
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// Call constructors
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// ************************************************************************************************
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#ifndef make_bootloader // constructors are not supported for bootloader
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__crt0_call_constructors:
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la x8, __init_array_start
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la x9, __init_array_end
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__crt0_call_constructors_loop:
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bge x8, x9, __crt0_call_constructors_loop_end
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lw x1, 0(x8)
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jalr x1, 0(x1)
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addi x8, x8, 4
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j __crt0_call_constructors_loop
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__crt0_call_constructors_loop_end:
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#endif
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// ************************************************************************************************
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// Setup arguments and call main function
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// ************************************************************************************************
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__crt0_main_entry:
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addi x10, zero, 0 // x10 = a0 = argc = 0
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addi x11, zero, 0 // x11 = a1 = argv = 0
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jal x1, main // call actual app's main function
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__crt0_main_exit: // main's "return" and "exit" will arrive here
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csrw mie, zero // disable all interrupt sources
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csrw mscratch, a0 // backup main's return code to mscratch (for debugger)
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// ************************************************************************************************
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// Call destructors
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// ************************************************************************************************
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#ifndef make_bootloader // destructors are not supported for bootloader
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__crt0_call_destructors:
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la x8, __fini_array_start
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la x9, __fini_array_end
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__crt0_call_destructors_loop:
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bge x8, x9, __crt0_call_destructors_loop_end
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lw x1, 0(x8)
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jalr x1, 0(x1)
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addi x8, x8, 4
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j __crt0_call_destructors_loop
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__crt0_call_destructors_loop_end:
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#endif
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// ************************************************************************************************
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// Go to endless sleep mode
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// ************************************************************************************************
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__crt0_shutdown:
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wfi
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j __crt0_shutdown
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// ************************************************************************************************
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// Early-boot trap handler - does nothing but trying to move on to the next linear instruction
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// ************************************************************************************************
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.balign 4 // the trap handler has to be 32-bit aligned
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__crt0_trap_handler:
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// backup x8 in mscratch - no need to use the stack
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csrw mscratch, x8
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// exit if interrupt
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csrr x8, mcause
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srli x8, x8, 31 // isolate MSB (set for interrupts)
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bnez x8, __crt0_trap_handler_end
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// mepc = mepc + 4 (for UNCOMPRESSED instruction)
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csrr x8, mepc
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addi x8, x8, +4
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csrw mepc, x8
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// exit if exception-causing instruction is uncompressed
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csrr x8, mtinst // get transformed exception-causing instruction
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andi x8, x8, 3 // isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
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addi x8, x8, -3 // x8 is zero after this if uncompressed instruction
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beqz x8, __crt0_trap_handler_end
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// mepc = mepc - 2 (making mepc_new = mepc_old + 2 for COMPRESSED instruction)
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csrr x8, mepc
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addi x8, x8, -2
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csrw mepc, x8
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// restore x8
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__crt0_trap_handler_end:
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csrr x8, mscratch
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mret
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.cfi_endproc
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.end
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