182 lines
11 KiB
C
182 lines
11 KiB
C
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// #################################################################################################
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// # << NEORV32 - Hardware Performance Monitors (HPMs) Demo Program >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file demo_hpm/main.c
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* @author Stephan Nolting
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* @brief Hardware performance monitor (HPM) example program.
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**************************************************************************/
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#include <neorv32.h>
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/**********************************************************************//**
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* @name User configuration
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**************************************************************************/
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/**@{*/
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/** UART BAUD rate */
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#define BAUD_RATE 19200
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/**@}*/
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/**********************************************************************//**
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* Main function
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*
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* @note This program requires the CPU Zihpm extension (with at least 2 regions) and UART0.
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*
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* @return 0 if execution was successful
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**************************************************************************/
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int main() {
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// initialize NEORV32 run-time environment
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neorv32_rte_setup();
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// setup UART at default baud rate, no interrupts
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neorv32_uart0_setup(BAUD_RATE, 0);
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// check if UART0 is implemented
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if (neorv32_uart0_available() == 0) {
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return 1; // UART0 not available, exit
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}
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// check if Zihpm is implemented at all
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if ((neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_ZIHPM)) == 0) {
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neorv32_uart0_printf("ERROR! Zihpm CPU extension not implemented!\n");
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return 1;
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}
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// check if at least one HPM counter is implemented
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if (neorv32_cpu_hpm_get_num_counters() == 0) {
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neorv32_uart0_printf("ERROR! No HPM counters implemented!\n");
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return 1;
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}
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// intro
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neorv32_uart0_printf("\n<<< NEORV32 Hardware Performance Monitors (HPMs) Example Program >>>\n\n");
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neorv32_uart0_printf("[NOTE] This program will use up to 9 HPM counters (if available).\n\n");
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// show HPM hardware configuration
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uint32_t hpm_num = neorv32_cpu_hpm_get_num_counters();
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uint32_t hpm_width = neorv32_cpu_hpm_get_size();
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neorv32_uart0_printf("%u HPM counters detected, each %u bits wide\n", hpm_num, hpm_width);
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// stop all CPU counters including HPMs
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neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1);
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// clear HPM counters (low and high word);
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// there will be NO exception if we access a HPM counter register that has not been implemented
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// as long as Zihpm is implemented
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if (hpm_num > 0) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER3H, 0); }
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if (hpm_num > 1) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER4H, 0); }
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if (hpm_num > 2) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER5H, 0); }
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if (hpm_num > 3) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER6H, 0); }
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if (hpm_num > 4) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER7H, 0); }
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if (hpm_num > 5) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER8H, 0); }
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if (hpm_num > 6) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER9H, 0); }
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if (hpm_num > 7) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER10H, 0); }
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if (hpm_num > 8) { neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMCOUNTER11H, 0); }
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// NOTE regarding HPMs 0..2, which are not "actual" HPMs
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// - HPM 0 is the machine cycle counter
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// - HPM 1 is the machine system timer
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// - HPM 2 is the machine instret counter
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// these counters have fixed event configurations; however, these according events can also be used for any other "real" HPM
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// setup base counters if available
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if ((neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_ZICNTR))) {
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neorv32_cpu_csr_write(CSR_MCYCLE, 0); neorv32_cpu_csr_write(CSR_MCYCLEH, 0);
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neorv32_cpu_csr_write(CSR_MINSTRET, 0); neorv32_cpu_csr_write(CSR_MINSTRETH, 0);
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}
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// configure events - one event per counter;
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// we can also configure more than one event; the HPM will increment if _any_ event triggers (logical OR);
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// there will be NO exception if we access a HPM event register that has not been implemented
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// as long as Zihpm is implemented
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if (hpm_num > 0) { neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_COMPR); } // executed compressed instruction
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if (hpm_num > 1) { neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_DIS); } // instruction dispatch wait cycle
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if (hpm_num > 2) { neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_WAIT_ALU); } // multi-cycle ALU co-processor wait cycle
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if (hpm_num > 3) { neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_BRANCH); } // executed branch instruction
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if (hpm_num > 4) { neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_BRANCHED); } // control flow transfer
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if (hpm_num > 5) { neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_LOAD); } // executed load operation
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if (hpm_num > 6) { neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_STORE); } // executed store operation
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if (hpm_num > 7) { neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_WAIT_LSU); } // load-store unit memory wait cycle
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if (hpm_num > 8) { neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TRAP); } // entered trap
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// enable all CPU counters including HPMs
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neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0);
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// this is the part of the the program that is going to be "benchmarked" using the HPMs
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// here we are just doing some pointless stuff that will trigger the configured HPM events;
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// note that ALL code being executed will be benchmarked - including traps
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{
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neorv32_uart0_printf("\n > Doing dummy operations...\n");
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neorv32_uart0_printf(" > Print some number: %u\n", 52983740);
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neorv32_uart0_printf(" > An exception (environment call) handled by the RTE: ");
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asm volatile ("ecall"); // environment call
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neorv32_uart0_printf(" > An invalid instruction handled by the RTE: ");
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asm volatile ("csrwi marchid, 1"); // illegal instruction (writing to read-only CSR)
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}
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// stop all CPU counters including HPMs
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neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1);
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// print HPM counter values (low word only)
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neorv32_uart0_printf("\nHPM results (low-words only):\n");
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if ((neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_ZICNTR))) {
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neorv32_uart0_printf(" cycle (active clock cycles) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MCYCLE));
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neorv32_uart0_printf(" instret (retired instructions) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MINSTRET));
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}
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if (hpm_num > 0) { neorv32_uart0_printf(" HPM03 (compressed instructions) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); }
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if (hpm_num > 1) { neorv32_uart0_printf(" HPM04 (instr. dispatch wait cycles) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); }
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if (hpm_num > 2) { neorv32_uart0_printf(" HPM05 (ALU wait cycles) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); }
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if (hpm_num > 3) { neorv32_uart0_printf(" HPM06 (branch instructions) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); }
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if (hpm_num > 4) { neorv32_uart0_printf(" HPM07 (control flow transfers) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); }
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if (hpm_num > 5) { neorv32_uart0_printf(" HPM08 (load instructions) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); }
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if (hpm_num > 6) { neorv32_uart0_printf(" HPM09 (store instructions) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); }
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if (hpm_num > 7) { neorv32_uart0_printf(" HPM10 (load/store wait cycles) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); }
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if (hpm_num > 8) { neorv32_uart0_printf(" HPM11 (entered traps) : %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); }
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neorv32_uart0_printf("\nProgram completed.\n");
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return 0;
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}
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