180 lines
8.3 KiB
C
180 lines
8.3 KiB
C
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// #################################################################################################
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// # << NEORV32: neorv32_dma.c - Direct Memory Access Controller (DMA) HW Driver >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_wdt.c
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* @brief Direct Memory Access Controller (DMA) HW driver source file.
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*
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* @note These functions should only be used if the DMA controller was synthesized (IO_DMA_EN = true).
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_dma.h"
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/**********************************************************************//**
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* Check if DMA controller was synthesized.
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*
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* @return 0 if DMA was not synthesized, 1 if DMA is available.
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**************************************************************************/
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int neorv32_dma_available(void) {
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if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_IO_DMA)) {
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return 1;
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}
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else {
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return 0;
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}
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}
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/**********************************************************************//**
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* Enable DMA.
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**************************************************************************/
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void neorv32_dma_enable(void) {
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NEORV32_DMA->CTRL |= (uint32_t)(1 << DMA_CTRL_EN);
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}
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/**********************************************************************//**
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* Disable DMA. This will reset the DMA and will also terminate the current transfer.
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**************************************************************************/
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void neorv32_dma_disable(void) {
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NEORV32_DMA->CTRL &= ~((uint32_t)(1 << DMA_CTRL_EN));
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}
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/**********************************************************************//**
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* Enable memory barrier (fence): issue a FENCE operation when DMA transfer
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* completes without errors.
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**************************************************************************/
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void neorv32_dma_fence_enable(void) {
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NEORV32_DMA->CTRL |= (uint32_t)(1 << DMA_CTRL_FENCE);
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}
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/**********************************************************************//**
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* Disable memory barrier (fence).
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**************************************************************************/
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void neorv32_dma_fence_disable(void) {
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NEORV32_DMA->CTRL &= ~((uint32_t)(1 << DMA_CTRL_FENCE));
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}
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/**********************************************************************//**
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* Trigger manual DMA transfer.
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*
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* @param[in] base_src Source base address (has to be aligned to source data type!).
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* @param[in] base_dst Destination base address (has to be aligned to destination data type!).
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* @param[in] num Number of elements to transfer (24-bit).
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* @param[in] config Transfer type configuration/commands.
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**************************************************************************/
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void neorv32_dma_transfer(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config) {
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NEORV32_DMA->CTRL &= ~((uint32_t)(1 << DMA_CTRL_AUTO)); // manual transfer trigger
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NEORV32_DMA->SRC_BASE = base_src;
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NEORV32_DMA->DST_BASE = base_dst;
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NEORV32_DMA->TTYPE = (num & 0x00ffffffUL) | (config & 0xff000000UL); // trigger transfer
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}
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/**********************************************************************//**
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* Configure automatic DMA transfer (triggered by CPU FIRQ).
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*
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* @param[in] base_src Source base address (has to be aligned to source data type!).
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* @param[in] base_dst Destination base address (has to be aligned to destination data type!).
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* @param[in] num Number of elements to transfer (24-bit).
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* @param[in] config Transfer type configuration/commands.
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* @param[in] firq_mask FIRQ trigger mask (#NEORV32_CSR_MIP_enum).
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**************************************************************************/
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void neorv32_dma_transfer_auto(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config, uint32_t firq_mask) {
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uint32_t tmp = NEORV32_DMA->CTRL;
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tmp |= (uint32_t)(1 << DMA_CTRL_AUTO); // automatic transfer trigger
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tmp &= 0x0000ffffUL; // clear current FIRQ mask
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tmp |= firq_mask & 0xffff0000UL; // set new FIRQ mask
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NEORV32_DMA->CTRL = tmp;
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NEORV32_DMA->SRC_BASE = base_src;
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NEORV32_DMA->DST_BASE = base_dst;
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NEORV32_DMA->TTYPE = (num & 0x00ffffffUL) | (config & 0xff000000UL);
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}
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/**********************************************************************//**
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* Get DMA status.
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*
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* @return Current DMA status (#NEORV32_DMA_STATUS_enum)
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**************************************************************************/
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int neorv32_dma_status(void) {
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uint32_t tmp = NEORV32_DMA->CTRL;
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if (tmp & (1 << DMA_CTRL_ERROR_WR)) {
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return DMA_STATUS_ERR_WR; // error during write access
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}
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else if (tmp & (1 << DMA_CTRL_ERROR_RD)) {
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return DMA_STATUS_ERR_RD; // error during read access
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}
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else if (tmp & (1 << DMA_CTRL_BUSY)) {
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return DMA_STATUS_BUSY; // transfer in progress
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}
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else {
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return DMA_STATUS_IDLE; // idle
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}
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}
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/**********************************************************************//**
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* Check if a transfer has actually been executed.
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*
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* @return 0 if no transfer was executed, 1 if a transfer has actually been executed.
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* Use neorv32_dma_status(void) to check if there was an error during that transfer.
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**************************************************************************/
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int neorv32_dma_done(void) {
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if (NEORV32_DMA->CTRL & (1 << DMA_CTRL_DONE)) {
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return 1; // there was a transfer
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}
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else {
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return 0; // no transfer executed
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}
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}
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