124 lines
4.0 KiB
Markdown
124 lines
4.0 KiB
Markdown
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# NEORV32 `Zfinx` Floating-Point Extension
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The NEORV32 floating-point unit (FPU) implements the `Zfinx` RISC-V extension. The extension can be
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enabled via the `CPU_EXTENSION_RISCV_Zfinx` top configuration generic.
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The RISC-V `Zfinx` single-precision floating-point extensions uses the integer register file `x` instead
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of a dedicated floating-point `f` register file (which is defined by the RISC-V `F` single-precision
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floating-point extension). Hence, the standard data transfer instructions from the `F` extension are
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**not** available in `Zfinx`:
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* floating-point load/store operations (`FLW`, `FSW`) and their compressed versions
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* integer register file `x` <-> floating point register file `f` move operations (`FMV.W.X`, `FMV.X.W`)
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:information_source: See the according section of the NEORV32 data sheet for more information.
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## Intrinsic Library
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The NEORV32 `Zfinx` floating-point extension can still be used using the provided **intrinsic library**. This
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library uses "custom" inline assembly instructions wrapped within normal C-language functions. Each original
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instruction of the extension can be utilized using an according intrinsic function.
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For example, the floating-point addition instruction `FADD.S` can be invoked using the according intrinsic function:
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```c
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float riscv_intrinsic_fadds(float rs1, float rs2)
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```
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The pure-software emulation instruction, which uses the standard built-in functions to execute all
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floating-point operations, is available via wrapper function. The emulation function for the `FADD.S` instruction is:
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```c
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float riscv_emulate_fadds(float rs1, float rs2)
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```
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The emulation functions as well as the available intrinsics for the `Zfinx` extension are located in
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`neorv32_zfinx_extension_intrinsics.h`. The provided test program `main.c` verifies all currently implemented
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`Zfinx` instructions by checking the functionality against the pure software-based emulation model (GCC soft-float library).
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## Exemplary Test Output
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```
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<<< Zfinx extension test >>>
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SILENT_MODE enabled (only showing actual errors)
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Test cases per instruction: 1000000
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NOTE: The NEORV32 FPU does not support subnormal numbers yet. Subnormal numbers are flushed to zero.
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#0: FCVT.S.WU (unsigned integer to float)...
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Errors: 0/1000000 [ok]
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#1: FCVT.S.W (signed integer to float)...
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Errors: 0/1000000 [ok]
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#2: FCVT.WU.S (float to unsigned integer)...
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Errors: 0/1000000 [ok]
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#3: FCVT.W.S (float to signed integer)...
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Errors: 0/1000000 [ok]
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#4: FADD.S (addition)...
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Errors: 0/1000000 [ok]
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#5: FSUB.S (subtraction)...
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Errors: 0/1000000 [ok]
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#6: FMUL.S (multiplication)...
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Errors: 0/1000000 [ok]
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#7: FMIN.S (select minimum)...
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Errors: 0/1000000 [ok]
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#8: FMAX.S (select maximum)...
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Errors: 0/1000000 [ok]
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#9: FEQ.S (compare if equal)...
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Errors: 0/1000000 [ok]
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#10: FLT.S (compare if less-than)...
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Errors: 0/1000000 [ok]
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#11: FLE.S (compare if less-than-or-equal)...
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Errors: 0/1000000 [ok]
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#12: FSGNJ.S (sign-injection)...
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Errors: 0/1000000 [ok]
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#13: FSGNJN.S (sign-injection NOT)...
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Errors: 0/1000000 [ok]
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#14: FSGNJX.S (sign-injection XOR)...
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Errors: 0/1000000 [ok]
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#15: FCLASS.S (classify)...
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Errors: 0/1000000 [ok]
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# unsupported FDIV.S (division) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x000006A8, INST=0x18A484D3 </RTE>
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[ok]
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# unsupported FSQRT.S (square root) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x000006E0, INST=0x580484D3 </RTE>
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[ok]
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# unsupported FMADD.S (fused multiply-add) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x0000071E, INST=0x1EA484C3 </RTE>
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[ok]
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# unsupported FMSUB.S (fused multiply-sub) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x0000075C, INST=0x1EA484C7 </RTE>
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[ok]
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# unsupported FNMSUB.S (fused negated multiply-sub) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x0000079A, INST=0x1EA484CF </RTE>
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[ok]
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# unsupported FNMADD.S (fused negated multiply-add) [illegal instruction]...
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<RTE> Illegal instruction @ PC=0x000007D8, INST=0x1EA484CF </RTE>
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[ok]
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[Zfinx extension verification successful!]
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```
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