341 lines
18 KiB
C
341 lines
18 KiB
C
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// #################################################################################################
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// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_intrinsics.h
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* @brief Helper functions and macros for custom "intrinsics" / instructions.
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**************************************************************************/
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#ifndef neorv32_intrinsics_h
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#define neorv32_intrinsics_h
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// ****************************************************************************************************************************
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// Custom Instruction Intrinsics
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// Derived from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
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// Original license header:
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//
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// From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
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//
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// Copyright (c) 2019 SaxonSoc contributors
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//
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// MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
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//
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// LICENSE:
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// MIT License
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//
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// Copyright (c) 2019 SaxonSoc contributors
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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// ****************************************************************************************************************************
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/**********************************************************************//**
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* @name Custom Instruction Intrinsics
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* @note Copied from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
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* Original license header:
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* // From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
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* //
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* // Copyright (c) 2019 SaxonSoc contributors
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* //
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* // MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
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**************************************************************************/
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/**@{*/
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asm(".set regnum_x0 , 0");
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asm(".set regnum_x1 , 1");
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asm(".set regnum_x2 , 2");
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asm(".set regnum_x3 , 3");
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asm(".set regnum_x4 , 4");
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asm(".set regnum_x5 , 5");
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asm(".set regnum_x6 , 6");
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asm(".set regnum_x7 , 7");
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asm(".set regnum_x8 , 8");
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asm(".set regnum_x9 , 9");
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asm(".set regnum_x10 , 10");
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asm(".set regnum_x11 , 11");
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asm(".set regnum_x12 , 12");
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asm(".set regnum_x13 , 13");
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asm(".set regnum_x14 , 14");
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asm(".set regnum_x15 , 15");
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asm(".set regnum_x16 , 16");
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asm(".set regnum_x17 , 17");
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asm(".set regnum_x18 , 18");
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asm(".set regnum_x19 , 19");
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asm(".set regnum_x20 , 20");
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asm(".set regnum_x21 , 21");
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asm(".set regnum_x22 , 22");
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asm(".set regnum_x23 , 23");
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asm(".set regnum_x24 , 24");
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asm(".set regnum_x25 , 25");
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asm(".set regnum_x26 , 26");
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asm(".set regnum_x27 , 27");
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asm(".set regnum_x28 , 28");
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asm(".set regnum_x29 , 29");
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asm(".set regnum_x30 , 30");
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asm(".set regnum_x31 , 31");
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asm(".set regnum_zero, 0");
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asm(".set regnum_ra , 1");
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asm(".set regnum_sp , 2");
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asm(".set regnum_gp , 3");
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asm(".set regnum_tp , 4");
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asm(".set regnum_t0 , 5");
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asm(".set regnum_t1 , 6");
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asm(".set regnum_t2 , 7");
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asm(".set regnum_s0 , 8");
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asm(".set regnum_s1 , 9");
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asm(".set regnum_a0 , 10");
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asm(".set regnum_a1 , 11");
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asm(".set regnum_a2 , 12");
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asm(".set regnum_a3 , 13");
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asm(".set regnum_a4 , 14");
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asm(".set regnum_a5 , 15");
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asm(".set regnum_a6 , 16");
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asm(".set regnum_a7 , 17");
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asm(".set regnum_s2 , 18");
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asm(".set regnum_s3 , 19");
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asm(".set regnum_s4 , 20");
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asm(".set regnum_s5 , 21");
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asm(".set regnum_s6 , 22");
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asm(".set regnum_s7 , 23");
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asm(".set regnum_s8 , 24");
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asm(".set regnum_s9 , 25");
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asm(".set regnum_s10 , 26");
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asm(".set regnum_s11 , 27");
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asm(".set regnum_t3 , 28");
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asm(".set regnum_t4 , 29");
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asm(".set regnum_t5 , 30");
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asm(".set regnum_t6 , 31");
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/** Official RISC-V opcodes for custom ISA extensions */
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asm(".set RISCV_OPCODE_CUSTOM0 , 0b0001011");
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asm(".set RISCV_OPCODE_CUSTOM1 , 0b0101011");
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asm(".set RISCV_OPCODE_CUSTOM2 , 0b1011011");
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asm(".set RISCV_OPCODE_CUSTOM3 , 0b1111011");
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/**@}*/
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/**********************************************************************//**
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* @name R2-type instruction format, RISC-V-standard
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**************************************************************************/
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#define CUSTOM_INSTR_R2_TYPE(funct7, funct5, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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"" \
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: [output] "=r" (__return) \
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: [input_i] "r" (rs1) \
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); \
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asm volatile( \
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".word ( \
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(((" #funct7 ") & 0x7f) << 25) | \
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(((" #funct5 ") & 0x1f) << 20) | \
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((( regnum_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( regnum_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1) \
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); \
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__return; \
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})
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/**********************************************************************//**
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* @name R3-type instruction format, RISC-V-standard
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**************************************************************************/
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#define CUSTOM_INSTR_R3_TYPE(funct7, rs2, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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"" \
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: [output] "=r" (__return) \
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: [input_i] "r" (rs1), \
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[input_j] "r" (rs2) \
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); \
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asm volatile ( \
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".word ( \
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(((" #funct7 ") & 0x7f) << 25) | \
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((( regnum_%2 ) & 0x1f) << 20) | \
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((( regnum_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( regnum_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1), \
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"r" (rs2) \
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); \
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__return; \
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})
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/**********************************************************************//**
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* @name R4-type instruction format, RISC-V-standard
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**************************************************************************/
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#define CUSTOM_INSTR_R4_TYPE(rs3, rs2, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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"" \
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: [output] "=r" (__return) \
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: [input_i] "r" (rs1), \
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[input_j] "r" (rs2), \
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[input_k] "r" (rs3) \
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); \
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asm volatile ( \
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".word ( \
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((( regnum_%3 ) & 0x1f) << 27) | \
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((( regnum_%2 ) & 0x1f) << 20) | \
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((( regnum_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( regnum_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1), \
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"r" (rs2), \
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"r" (rs3) \
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); \
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__return; \
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})
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/**********************************************************************//**
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* @name R5-type instruction format
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* @warning NOT RISC-V-standard, NEORV32-specific!
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**************************************************************************/
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#define CUSTOM_INSTR_R5_TYPE(rs4, rs3, rs2, rs1, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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"" \
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: [output] "=r" (__return) \
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: [input_i] "r" (rs1), \
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[input_j] "r" (rs2), \
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[input_k] "r" (rs3), \
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[input_l] "r" (rs4) \
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); \
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asm volatile ( \
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".word ( \
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((( regnum_%3 ) & 0x1f) << 27) | \
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(((( regnum_%4 ) >> 3) & 0x03) << 25) | \
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((( regnum_%2 ) & 0x1f) << 20) | \
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((( regnum_%1 ) & 0x1f) << 15) | \
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((( regnum_%4 ) & 0x07) << 12) | \
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((( regnum_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1), \
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"r" (rs2), \
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"r" (rs3), \
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"r" (rs4) \
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); \
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__return; \
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})
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/**********************************************************************//**
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* @name I-type instruction format, RISC-V-standard
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**************************************************************************/
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#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \
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({ \
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uint32_t __return; \
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asm volatile ( \
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"" \
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: [output] "=r" (__return) \
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: [input_i] "r" (rs1) \
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); \
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asm volatile ( \
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".word ( \
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(((" #imm12 ") & 0xfff) << 20) | \
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((( regnum_%1 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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((( regnum_%0 ) & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: [rd] "=r" (__return) \
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: "r" (rs1) \
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); \
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__return; \
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})
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/**********************************************************************//**
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* @name S-type instruction format, RISC-V-standard
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**************************************************************************/
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#define CUSTOM_INSTR_S_TYPE(imm12, rs2, rs1, funct3, opcode) \
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({ \
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asm volatile ( \
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"" \
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: \
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: [input_i] "r" (rs1), \
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[input_j] "r" (rs2) \
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); \
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asm volatile ( \
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".word ( \
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((((" #imm12 ") >> 5) & 0x7f) << 25) | \
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((( regnum_%1 ) & 0x1f) << 20) | \
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((( regnum_%0 ) & 0x1f) << 15) | \
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(((" #funct3 ") & 0x07) << 12) | \
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(((" #imm12 ") & 0x1f) << 7) | \
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(((" #opcode ") & 0x7f) << 0) \
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);" \
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: \
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: "r" (rs1), \
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"r" (rs2) \
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); \
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})
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||
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#endif // neorv32_intrinsics_h
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