218 lines
10 KiB
VHDL
218 lines
10 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 CPU - General Purpose Data Register File >> #
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-- # ********************************************************************************************* #
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-- # Data register file. 32 entries (= 1024 bit) for RV32I ISA (default), 16 entries (= 512 bit) #
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-- # for RV32E ISA (when RISC-V "E" extension is enabled via "RVE_EN"). #
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-- # #
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-- # By default the register file is coded to infer block RAM (for FPGAs), that do no provide a #
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-- # dedicated hardware reset. For ASIC implementation or setup requiring a dedicated hardware #
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-- # reset a single-register-based architecture can be enabled via "RST_EN". #
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-- # #
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-- # A third and a fourth read port can be optionally enabled ("RS3_EN", "RS4_EN"). #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_regfile is
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generic (
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RST_EN : boolean; -- enable dedicated hardware reset ("ASIC style")
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RVE_EN : boolean; -- implement embedded RF extension
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RS3_EN : boolean; -- enable 3rd read port
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RS4_EN : boolean -- enable 4th read port
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in ctrl_bus_t; -- main control bus
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-- data input --
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alu_i : in std_ulogic_vector(XLEN-1 downto 0); -- ALU result
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mem_i : in std_ulogic_vector(XLEN-1 downto 0); -- memory read data
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csr_i : in std_ulogic_vector(XLEN-1 downto 0); -- CSR read data
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ret_i : in std_ulogic_vector(XLEN-1 downto 0); -- link PC
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-- data output --
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rs1_o : out std_ulogic_vector(XLEN-1 downto 0); -- rs1
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rs2_o : out std_ulogic_vector(XLEN-1 downto 0); -- rs2
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rs3_o : out std_ulogic_vector(XLEN-1 downto 0); -- rs3
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rs4_o : out std_ulogic_vector(XLEN-1 downto 0) -- rs4
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);
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end neorv32_cpu_regfile;
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architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
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-- auto-configuration --
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constant addr_bits_c : natural := cond_sel_natural_f(RVE_EN, 4, 5); -- address width
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-- register file --
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type reg_file_t is array ((2**addr_bits_c)-1 downto 0) of std_ulogic_vector(XLEN-1 downto 0);
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signal reg_file : reg_file_t;
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-- access --
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signal rf_wdata : std_ulogic_vector(XLEN-1 downto 0); -- write-back data
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signal rf_we : std_ulogic; -- write enable
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signal rf_we_sel : std_ulogic_vector((2**addr_bits_c)-1 downto 0); -- one-hot write enable
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signal rd_zero : std_ulogic; -- writing to x0?
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/rd address
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signal rs4_addr : std_ulogic_vector(4 downto 0); -- rs4 address
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begin
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-- Data Write-Back Select -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wb_select: process(ctrl_i, alu_i, mem_i, csr_i, ret_i)
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begin
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case ctrl_i.rf_mux is
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when rf_mux_alu_c => rf_wdata <= alu_i; -- ALU result
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when rf_mux_mem_c => rf_wdata <= mem_i; -- memory read data
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when rf_mux_csr_c => rf_wdata <= csr_i; -- CSR read data
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when rf_mux_ret_c => rf_wdata <= ret_i; -- link PC (return address)
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when others => rf_wdata <= alu_i; -- don't care
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end case;
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end process wb_select;
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-- FPGA Register File (no hardware reset) -------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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register_file_fpga:
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if not RST_EN generate
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-- Register zero (x0) is a "normal" physical register that is set to zero by the CPU control
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-- hardware. The register file uses synchronous read accesses and a *single* multiplexed
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-- address port for writing and reading rd/rs1 and a single read-only port for rs2. Therefore,
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-- the whole register file can be mapped to a single true-dual-port block RAM.
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rd_zero <= '1' when (ctrl_i.rf_rd = "00000") else '0';
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rf_we <= (ctrl_i.rf_wb_en and (not rd_zero)) or ctrl_i.rf_zero_we; -- never write to x0 unless explicitly forced
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opa_addr <= "00000" when (ctrl_i.rf_zero_we = '1') else -- force rd = zero
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ctrl_i.rf_rd when (ctrl_i.rf_wb_en = '1') else -- rd
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ctrl_i.rf_rs1; -- rs1
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register_file: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (rf_we = '1') then
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reg_file(to_integer(unsigned(opa_addr(addr_bits_c-1 downto 0)))) <= rf_wdata;
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end if;
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rs1_o <= reg_file(to_integer(unsigned(opa_addr(addr_bits_c-1 downto 0))));
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rs2_o <= reg_file(to_integer(unsigned(ctrl_i.rf_rs2(addr_bits_c-1 downto 0))));
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end if;
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end process register_file;
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end generate;
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-- ASIC Register File (full hardware reset) -----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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register_file_asic:
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if RST_EN generate
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-- write enable decoder --
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we_decode: process(ctrl_i)
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begin
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rf_we_sel <= (others => '0');
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if (ctrl_i.rf_wb_en = '1') then
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rf_we_sel(to_integer(unsigned(ctrl_i.rf_rd(addr_bits_c-1 downto 0)))) <= '1';
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end if;
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end process we_decode;
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-- individual registers --
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reg_gen:
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for i in 1 to (2**addr_bits_c)-1 generate
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register_file: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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reg_file(i) <= (others => '0');
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elsif rising_edge(clk_i) then
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if (rf_we_sel(i) = '1') then
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reg_file(i) <= rf_wdata;
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end if;
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end if;
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end process register_file;
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end generate;
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reg_file(0) <= (others => '0'); -- x0 is hardwired to zero
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rf_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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rs1_o <= reg_file(to_integer(unsigned(ctrl_i.rf_rs1(addr_bits_c-1 downto 0))));
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rs2_o <= reg_file(to_integer(unsigned(ctrl_i.rf_rs2(addr_bits_c-1 downto 0))));
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end if;
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end process rf_read;
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end generate;
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-- Optional 3rd Read Port (rs3) -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rs3_enable:
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if RS3_EN generate
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rs3_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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rs3_o <= reg_file(to_integer(unsigned(ctrl_i.rf_rs3(addr_bits_c-1 downto 0))));
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end if;
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end process rs3_read;
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end generate;
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rs3_disable:
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if not RS3_EN generate
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rs3_o <= (others => '0');
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end generate;
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-- Optional 4th Read Port (rs4) -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rs4_enable:
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if RS4_EN generate
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rs4_read: process(clk_i)
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begin
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if rising_edge(clk_i) then
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rs4_o <= reg_file(to_integer(unsigned(rs4_addr(addr_bits_c-1 downto 0))));
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end if;
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end process rs4_read;
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rs4_addr <= ctrl_i.ir_funct12(6 downto 5) & ctrl_i.ir_funct3; -- rs4 = [26:25] & [14:12]; not RISC-V-standard!
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end generate;
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rs4_disable:
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if not RS4_EN generate
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rs4_o <= (others => '0');
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end generate;
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end neorv32_cpu_regfile_rtl;
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