161 lines
7.9 KiB
VHDL
161 lines
7.9 KiB
VHDL
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-- #################################################################################################
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-- # << NEORV32 - Cyclic Redundancy Check Unit (CRC) >> #
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-- # ********************************************************************************************* #
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-- # Bit-serial / iterative CRC computation module with programmable polynomial and operating mode #
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-- # (CRC8, CRC16, CRC32). The write access ACK signal is DELAYED to ensure that the current CRC #
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-- # has completed before new data can be written. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_crc is
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t -- bus response
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);
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end neorv32_crc;
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architecture neorv32_crc_rtl of neorv32_crc is
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-- interface register addresses --
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constant mode_addr_c : std_ulogic_vector(1 downto 0) := "00"; -- r/w: mode register
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constant poly_addr_c : std_ulogic_vector(1 downto 0) := "01"; -- r/w: polynomial register
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constant data_addr_c : std_ulogic_vector(1 downto 0) := "10"; -- -/w: data register
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constant sreg_addr_c : std_ulogic_vector(1 downto 0) := "11"; -- r/w: CRC shift register
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-- CRC core --
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type crc_t is record
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mode : std_ulogic_vector(01 downto 0);
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poly : std_ulogic_vector(31 downto 0);
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data : std_ulogic_vector(07 downto 0);
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sreg : std_ulogic_vector(31 downto 0);
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--
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cnt : std_ulogic_vector(03 downto 0);
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msb : std_ulogic;
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end record;
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signal crc : crc_t;
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-- delayed ACK on write access --
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signal we_ack : std_ulogic_vector(5 downto 0); -- to wait for serial CRC processing
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begin
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-- Bus Access- ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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crc.mode <= (others => '0');
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crc.poly <= (others => '0');
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crc.data <= (others => '0');
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we_ack <= (others => '0');
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elsif rising_edge(clk_i) then
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-- bus handshake --
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bus_rsp_o.data <= (others => '0');
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bus_rsp_o.err <= '0';
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bus_rsp_o.ack <= we_ack(we_ack'left) or (bus_req_i.stb and (not bus_req_i.rw));
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-- write access --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
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if (bus_req_i.addr(3 downto 2) = mode_addr_c) then -- mode select
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crc.mode <= bus_req_i.data(01 downto 0);
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end if;
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if (bus_req_i.addr(3 downto 2) = poly_addr_c) then -- polynomial
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crc.poly <= bus_req_i.data(31 downto 0);
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end if;
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if (bus_req_i.addr(3 downto 2) = data_addr_c) then -- data
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crc.data <= bus_req_i.data(07 downto 0);
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end if;
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end if;
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-- delayed write ACK --
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we_ack <= we_ack(we_ack'left-1 downto 0) & (bus_req_i.stb and bus_req_i.rw);
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-- read access --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '0') then
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case bus_req_i.addr(3 downto 2) is
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when mode_addr_c => bus_rsp_o.data(01 downto 0) <= crc.mode; -- mode select
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when poly_addr_c => bus_rsp_o.data(31 downto 0) <= crc.poly; -- polynomial
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when others => bus_rsp_o.data(31 downto 0) <= crc.sreg; -- CRC result
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end case;
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end if;
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end if;
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end process bus_access;
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-- Bit-Serial CRC Core --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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crc_core: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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crc.cnt <= (others => '1');
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crc.sreg <= (others => '0');
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elsif rising_edge(clk_i) then
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-- arbitration --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(3 downto 2) = data_addr_c) then -- writing new data
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crc.cnt <= "0111"; -- start with MSB
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elsif (crc.cnt(3) = '0') then -- not done yet?
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crc.cnt <= std_ulogic_vector(unsigned(crc.cnt) - 1);
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end if;
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-- computation --
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') and (bus_req_i.addr(3 downto 2) = sreg_addr_c) then -- set start value
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crc.sreg <= bus_req_i.data;
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elsif (crc.cnt(3) = '0') then
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if (crc.msb = crc.data(to_integer(unsigned(crc.cnt(2 downto 0))))) then
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crc.sreg <= (crc.sreg(30 downto 0) & '0');
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else
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crc.sreg <= (crc.sreg(30 downto 0) & '0') xor crc.poly;
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end if;
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end if;
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end if;
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end process crc_core;
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-- operation mode --
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with crc.mode select crc.msb <=
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crc.sreg(07) when "00", -- crc8
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crc.sreg(15) when "01", -- crc16
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crc.sreg(31) when others; -- crc32
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end neorv32_crc_rtl;
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