293 lines
13 KiB
C
293 lines
13 KiB
C
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// #################################################################################################
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// # << NEORV32 - DMA Demo Program >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file demo_dma/main.c
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* @author Stephan Nolting
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* @brief DMA demo program.
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**************************************************************************/
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#include <neorv32.h>
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/**********************************************************************//**
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* @name User configuration
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**************************************************************************/
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/**@{*/
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/** UART BAUD rate */
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#define BAUD_RATE 19200
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/**@}*/
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// arrays for DMA data
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volatile uint32_t dma_src[4], dma_dst[4];
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// prototypes
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void show_arrays(void);
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void dma_firq_handler(void);
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/**********************************************************************//**
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* Simple demo program to showcase the NEORV32 DMA controller.
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*
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* @note This program requires UART0 and the DMA controller to be synthesized.
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*
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* @return Irrelevant.
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**************************************************************************/
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int main() {
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uint32_t cmd;
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int rc;
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// setup NEORV32 runtime environment
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neorv32_rte_setup();
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// setup UART at default baud rate, no interrupts
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neorv32_uart0_setup(BAUD_RATE, 0);
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// intro
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neorv32_uart0_printf("\n<<< DMA Controller Demo Program >>>\n\n");
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// check if DMA controller is implemented at all
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if (neorv32_dma_available() == 0) {
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neorv32_uart0_printf("ERROR! DMA controller not implemented!\n");
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return 1;
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}
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// show base address of test data arrays
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neorv32_uart0_printf("Source test data: %u bytes @ 0x%x\n", (uint32_t)(sizeof(dma_src)), (uint32_t)(&dma_src[0]));
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neorv32_uart0_printf("Destination test data: %u bytes @ 0x%x\n", (uint32_t)(sizeof(dma_src)), (uint32_t)(&dma_dst[0]));
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// install DMA interrupt handler
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neorv32_rte_handler_install(DMA_RTE_ID, dma_firq_handler);
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// enable DMA
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neorv32_dma_enable();
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// issue a FENCE operation when the DMA transfer completes (without errors); this
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// will re-sync /flush and reload) all downstream caches
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neorv32_dma_fence_enable();
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// initialize and data arrays
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dma_src[0] = 0x66778899UL;
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dma_src[1] = 0x22334455UL;
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dma_src[2] = 0xaabbccddUL;
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dma_src[3] = 0x0011eeffUL;
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dma_dst[0] = 0;
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dma_dst[1] = 0;
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dma_dst[2] = 0;
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dma_dst[3] = 0;
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asm volatile ("fence"); // re-sync caches
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// ----------------------------------------------------------
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// example 1
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// ----------------------------------------------------------
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neorv32_uart0_printf("\nExample 1: Manual byte-to-byte block transfer with Endianness conversion using busy wait.\n");
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// configure transfer type
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cmd = DMA_CMD_B2B | // read source in byte quantities, write destination in byte quantities
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DMA_CMD_SRC_INC | // auto-increment source address
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DMA_CMD_DST_INC | // auto-increment destination address
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DMA_CMD_ENDIAN; // change Endianness
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// trigger manual DMA transfer
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neorv32_dma_transfer((uint32_t)(&dma_src[0]), // source array base address - byte-aligned!
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(uint32_t)(&dma_dst[0]), // destination array base address - byte-aligned!
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16, // number of elements to transfer: 16
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cmd); // transfer type configuration
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// wait for transfer to complete using polling
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neorv32_uart0_printf("Waiting for DMA... ");
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while (1) {
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rc = neorv32_dma_status();
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if (rc == DMA_STATUS_IDLE) {
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neorv32_uart0_printf("Transfer done.\n");
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break;
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}
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else if ((rc == DMA_STATUS_ERR_RD) || (rc == DMA_STATUS_ERR_WR)) {
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neorv32_uart0_printf("Transfer failed!\n");
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break;
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}
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}
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show_arrays();
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// ----------------------------------------------------------
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// example 2
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// ----------------------------------------------------------
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neorv32_uart0_printf("\nExample 2: Manual word-to-word one-to-many transfer using busy wait.\n");
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// configure transfer type
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cmd = DMA_CMD_W2W | // read source in word quantities, write destination in word quantities
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DMA_CMD_SRC_CONST | // constant source address
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DMA_CMD_DST_INC; // auto-increment destination address
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// trigger manual DMA transfer
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neorv32_dma_transfer((uint32_t)(&dma_src[0]), // source array base address - word-aligned!
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(uint32_t)(&dma_dst[0]), // destination array base address - word-aligned!
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4, // number of elements to transfer: 4
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cmd); // transfer type configuration
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// wait for transfer to complete using polling
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neorv32_uart0_printf("Waiting for DMA... ");
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while (1) {
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rc = neorv32_dma_status();
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if (rc == DMA_STATUS_IDLE) {
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neorv32_uart0_printf("Transfer done.\n");
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break;
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}
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else if ((rc == DMA_STATUS_ERR_RD) || (rc == DMA_STATUS_ERR_WR)) {
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neorv32_uart0_printf("Transfer failed!\n");
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break;
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}
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}
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show_arrays();
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// ----------------------------------------------------------
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// example 3
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// ----------------------------------------------------------
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neorv32_uart0_printf("\nExample 3: Manual byte-to-signed-word block transfer using transfer-done interrupt.\n");
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// configure DMA interrupt
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neorv32_cpu_csr_clr(CSR_MIP, 1 << DMA_FIRQ_PENDING); // clear any pending DMA FIRQ
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neorv32_cpu_csr_set(CSR_MIE, 1 << DMA_FIRQ_ENABLE); // enable DMA interrupt source
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neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE); // enable machine-mode interrupts
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// configure transfer type
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cmd = DMA_CMD_B2SW | // read source in byte quantities, write destination in sign-extended word quantities
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DMA_CMD_SRC_INC | // auto-increment source address
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DMA_CMD_DST_INC; // auto-increment destination address
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// trigger manual DMA transfer
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neorv32_dma_transfer((uint32_t)(&dma_src[0]), // source array base address - byte-aligned!
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(uint32_t)(&dma_dst[0]), // destination array base address - word-aligned!
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4, // number of elements to transfer: 4
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cmd); // transfer type configuration
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// go to sleep mode, wakeup on DMA transfer-done interrupt
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neorv32_cpu_sleep();
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// check if transfer was successful
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if (neorv32_dma_status() != DMA_STATUS_IDLE) {
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neorv32_uart0_printf("Transfer failed!\n");
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}
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show_arrays();
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// ----------------------------------------------------------
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// example 4
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// ----------------------------------------------------------
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neorv32_uart0_printf("\nExample 4: Automatic byte-to-byte one-to-many transfer using transfer-done interrupt.\n");
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neorv32_uart0_printf( " The GPTMR FIRQ channel is used to trigger the DMA.\n");
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if (neorv32_gptmr_available()) { // only execute if GPTMR is available
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// configure DMA interrupt
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neorv32_cpu_csr_clr(CSR_MIP, 1 << DMA_FIRQ_PENDING); // clear any pending DMA FIRQ
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neorv32_cpu_csr_set(CSR_MIE, 1 << DMA_FIRQ_ENABLE); // enable DMA interrupt source
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neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE); // enable machine-mode interrupts
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// configure GPTMR
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neorv32_gptmr_setup(CLK_PRSC_2, // GPTM clock = 1/2 main clock
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4096, // counter threshold for triggering IRQ
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1); // enable timer-match interrupt
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// configure transfer type
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cmd = DMA_CMD_B2B | // read source in byte quantities, write destination in byte quantities
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DMA_CMD_SRC_CONST | // constant source address
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DMA_CMD_DST_INC; // auto-increment destination address
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// configure automatic DMA transfer
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neorv32_dma_transfer_auto((uint32_t)(&dma_src[3]), // source array base address (data = 0xff)
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(uint32_t)(&dma_dst[0]), // destination array base address
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16, // number of elements to transfer: 16
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cmd, // transfer type configuration
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1 << GPTMR_FIRQ_PENDING); // trigger transfer on pending GPTMR interrupt
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// sleep until interrupt (from DMA)
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neorv32_cpu_sleep();
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// transfer successful (and actually executed)?
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if ((neorv32_dma_done() == 0) || // check if the DMA has actually completed a transfer
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(neorv32_dma_status() != DMA_STATUS_IDLE)) { // DMA is in idle mode without errors
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neorv32_uart0_printf("Transfer failed!\n");
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}
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show_arrays();
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}
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else {
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neorv32_uart0_printf("Example skipped as GPTMR is not implemented.\n");
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}
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neorv32_uart0_printf("\nProgram completed.\n");
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return 0;
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}
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/**********************************************************************//**
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* Print test data arrays
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**************************************************************************/
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void show_arrays(void) {
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asm volatile ("fence"); // re-sync caches
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neorv32_uart0_printf("---------------------------\n");
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neorv32_uart0_printf(" SRC DST\n");
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neorv32_uart0_printf("[0] 0x%x 0x%x\n", dma_src[0], dma_dst[0]);
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neorv32_uart0_printf("[1] 0x%x 0x%x\n", dma_src[1], dma_dst[1]);
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neorv32_uart0_printf("[2] 0x%x 0x%x\n", dma_src[2], dma_dst[2]);
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neorv32_uart0_printf("[3] 0x%x 0x%x\n", dma_src[3], dma_dst[3]);
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neorv32_uart0_printf("---------------------------\n");
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}
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/**********************************************************************//**
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* DMA FIRQ handler.
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*
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* @warning This function has to be of type "void xyz(void)" and must not use any interrupt attributes!
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**************************************************************************/
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void dma_firq_handler(void) {
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neorv32_cpu_csr_clr(CSR_MIP, 1 << DMA_FIRQ_PENDING); // clear/ack pending FIRQ
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neorv32_gptmr_disable(); // disable GPTMR
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neorv32_uart0_printf("<<DMA interrupt>>\n");
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}
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