71 lines
3.8 KiB
Markdown
71 lines
3.8 KiB
Markdown
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# Test Setups
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This folder contains very simple test setups that are intended for project beginners
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to setup a minimal NEORV32 SoC. These setups are used in the :books:
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[NEORV32 User Guide](https://stnolting.github.io/neorv32/ug/).
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Note that these setups provides a minimalistic configuration to keep
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things at a simple level at first. Additional CPU ISA extensions, performance options and
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optional peripheral modules can be enabled by specifying the according :book:
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[configuration generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics).
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### Setup Top Entities
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#### Clocking and Reset
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All test setups require an external clock (via `clk_i` signal) and an external
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low-active reset (via `rstn_i` signal).
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#### Configuration Generics
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Each setup provides three elementary generics that can/should be adapted to fit
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your FPGA/board.
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* The clock speed in Hz **has to be specified** via the `CLOCK_SPEED` generic to fit your clock source.
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* The processor-internal instruction memory (IMEM) size _can be modified_ via the `MEM_INT_IMEM_SIZE` generic.
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* The processor-internal data memory (DMEM) size _can be modified_ via the `MEM_INT_DMEM_SIZE` generic.
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:warning: Modifying the memory sizes might require adaption of the NEORV32 linker script.
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### [`neorv32_test_setup_approm.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_approm.vhd)
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This setup configures a `rv32imc_Zicsr_Zicntr` CPU with 16kB IMEM (as pre-initialized ROM),
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8kB DMEM and includes the **GPIO** module to drive 8 external signals (`gpio_o`)
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and the **MTIME** module for generating timer interrupts.
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The setup uses the ["direct boot"](https://stnolting.github.io/neorv32/#_direct_boot)
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configuration, so software applications are "installed" directly into the
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processor-internal IMEM (via the bitstream) during synthesis.
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:books: See User Guide section
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[Installing an Executable Directly Into Memory](https://stnolting.github.io/neorv32/ug/#_installing_an_executable_directly_into_memory).
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### [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_bootloader.vhd)
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This setup configures a `rv32imc_Zicsr_Zicntr` CPU with 16kB IMEM (as RAM), 8kB DMEM
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and includes the **GPIO** module to drive 8 external signals (`gpio_o`), the **MTIME**
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module for generating timer interrupts and **UART0** to interface with the bootloader or application
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(via `uart0_txd_o` and `uart0_rxd_i`) via a serial terminal.
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The setup uses the ["indirect boot"](https://stnolting.github.io/neorv32/#_indirect_boot)
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configuration, so software applications can be uploaded and run at any timer via the bootloader
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and a serial terminal.
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:books: See User Guide section
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[Uploading and Starting of a Binary Executable Image via UART](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart).
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### [`neorv32_test_setup_on_chip_debugger.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd)
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This setup configures a `rv32imc_Zicsr_Zicntr_Zifencei` CPU with 16kB IMEM (as RAM), 8kB DMEM
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and includes the **GPIO** module to drive 8 external signals (`gpio_o`), the **MTIME**
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module for generating timer interrupts, **UART0** to interface with the bootloader or application
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(via `uart0_txd_o` and `uart0_rxd_i`) via a serial terminal and also the RISC-V-compatible
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on-chip debugger (**OCD**), which is accessible via a standard JTAG interface (`jtag_*`).
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The setup uses the ["indirect boot"](https://stnolting.github.io/neorv32/#_indirect_boot)
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configuration, so software applications can be uploaded and run at any timer via the bootloader
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and a serial terminal and also via the on-chip debugger.
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:books: See User Guide section
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[Debugging using the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger).
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