105 lines
7.1 KiB
C
105 lines
7.1 KiB
C
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// #################################################################################################
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// # << NEORV32: neorv32_xip.h - Execute In Place (XIP) Module HW Driver (Header) >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_xip.h
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* @brief Execute in place module (XIP) HW driver header file.
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*
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* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).
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**************************************************************************/
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#ifndef neorv32_xip_h
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#define neorv32_xip_h
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/**********************************************************************//**
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* @name IO Device: Execute In Place Module (XIP)
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**************************************************************************/
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/**@{*/
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/** XIP module prototype */
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typedef volatile struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_XIP_CTRL_enum) */
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const uint32_t reserved; /**< offset 4: reserved */
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uint32_t DATA_LO; /**< offset 8: SPI data register low */
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uint32_t DATA_HI; /**< offset 12: SPI data register high */
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} neorv32_xip_t;
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/** XIP module hardware access (#neorv32_xip_t) */
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#define NEORV32_XIP ((neorv32_xip_t*) (NEORV32_XIP_BASE))
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/** XIP control/data register bits */
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enum NEORV32_XIP_CTRL_enum {
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XIP_CTRL_EN = 0, /**< XIP control register( 0) (r/w): XIP module enable */
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XIP_CTRL_PRSC0 = 1, /**< XIP control register( 1) (r/w): Clock prescaler select bit 0 */
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XIP_CTRL_PRSC1 = 2, /**< XIP control register( 2) (r/w): Clock prescaler select bit 1 */
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XIP_CTRL_PRSC2 = 3, /**< XIP control register( 3) (r/w): Clock prescaler select bit 2 */
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XIP_CTRL_CPOL = 4, /**< XIP control register( 4) (r/w): SPI (idle) clock polarity */
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XIP_CTRL_CPHA = 5, /**< XIP control register( 5) (r/w): SPI clock phase */
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XIP_CTRL_SPI_NBYTES_LSB = 6, /**< XIP control register( 6) (r/w): Number of bytes in SPI transmission, LSB */
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XIP_CTRL_SPI_NBYTES_MSB = 9, /**< XIP control register( 9) (r/w): Number of bytes in SPI transmission, MSB */
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XIP_CTRL_XIP_EN = 10, /**< XIP control register(10) (r/w): XIP access enable */
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XIP_CTRL_XIP_ABYTES_LSB = 11, /**< XIP control register(11) (r/w): Number XIP address bytes (minus 1), LSB */
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XIP_CTRL_XIP_ABYTES_MSB = 12, /**< XIP control register(12) (r/w): Number XIP address bytes (minus 1), MSB */
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XIP_CTRL_RD_CMD_LSB = 13, /**< XIP control register(13) (r/w): SPI flash read command, LSB */
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XIP_CTRL_RD_CMD_MSB = 20, /**< XIP control register(20) (r/w): SPI flash read command, MSB */
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XIP_CTRL_SPI_CSEN = 21, /**< XIP control register(21) (r/w): SPI chip-select enable */
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XIP_CTRL_HIGHSPEED = 22, /**< XIP control register(22) (r/w): SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) */
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XIP_CTRL_CDIV0 = 23, /**< XIP control register(23) (r/w): Clock divider bit 0 */
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XIP_CTRL_CDIV1 = 24, /**< XIP control register(24) (r/w): Clock divider bit 1 */
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XIP_CTRL_CDIV2 = 25, /**< XIP control register(25) (r/w): Clock divider bit 2 */
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XIP_CTRL_CDIV3 = 26, /**< XIP control register(26) (r/w): Clock divider bit 3 */
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XIP_CTRL_BURST_EN = 29, /**< XIP control register(29) (r/-): Burst mode enabled (set if XIP cache is implemented) */
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XIP_CTRL_PHY_BUSY = 30, /**< XIP control register(30) (r/-): SPI PHY is busy */
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XIP_CTRL_XIP_BUSY = 31 /**< XIP control register(31) (r/-): XIP access in progress */
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};
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/**@}*/
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/**********************************************************************//**
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* @name Prototypes
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**************************************************************************/
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/**@{*/
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int neorv32_xip_available(void);
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void neorv32_xip_setup(int prsc, int cdiv, int cpol, int cpha, uint8_t rd_cmd);
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int neorv32_xip_start(int abytes);
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void neorv32_xip_highspeed_enable(void);
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void neorv32_xip_highspeed_disable(void);
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uint32_t neorv32_xip_get_clock_speed(void);
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void neorv32_xip_spi_trans(int nbytes, uint64_t *rtx_data);
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/**@}*/
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#endif // neorv32_xip_h
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