diff --git a/rtl/processor_templates/neorv32_ProcessorTop_Minimal.v b/rtl/processor_templates/neorv32_ProcessorTop_Minimal.v
index 016fc87..ace1200 100644
--- a/rtl/processor_templates/neorv32_ProcessorTop_Minimal.v
+++ b/rtl/processor_templates/neorv32_ProcessorTop_Minimal.v
@@ -1,24 +1,3 @@
-// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
-// vhd2vl settings:
-//  * Verilog Module Declaration Style: 2001
-
-// vhd2vl is Free (libre) Software:
-//   Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
-//     http://www.ocean-logic.com
-//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
-//   Modifications (C) 2010 Shankar Giri
-//   Modifications Copyright (C) 2002-2023 Larry Doolittle
-//     http://doolittle.icarus.com/~larry/vhd2vl/
-//   Modifications (C) 2017 Rodrigo A. Melo
-//
-//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
-//   Verilog for correctness, ideally with a formal verification tool.
-//
-//   You are welcome to redistribute vhd2vl under certain conditions.
-//   See the license (GPLv2) file included with the source for details.
-
-// The result of translation follows.  Its copyright status should be
-// considered unchanged from the original VHDL.
 
 // #################################################################################################
 // # << NEORV32 - Minimal setup without a bootloader >>                                            #