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Update rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v

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FPGALover 2024-02-28 23:31:44 +00:00
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commit 9cf19a00ce
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rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v
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// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 2001
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002-2023 Larry Doolittle
// http://doolittle.icarus.com/~larry/vhd2vl/
// Modifications (C) 2017 Rodrigo A. Melo
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// #################################################################################################
// # << NEORV32 - Example setup for boards with UP5K devices >> #