From 9cf19a00ce9303bb60266068ea80302f1f345c1f Mon Sep 17 00:00:00 2001 From: FPGALover Date: Wed, 28 Feb 2024 23:31:44 +0000 Subject: [PATCH] Update rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v --- .../neorv32_ProcessorTop_UP5KDemo.v | 20 ------------------- 1 file changed, 20 deletions(-) diff --git a/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v b/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v index 7e698c6..58d27be 100644 --- a/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v +++ b/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v @@ -1,24 +1,4 @@ -// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator -// vhd2vl settings: -// * Verilog Module Declaration Style: 2001 -// vhd2vl is Free (libre) Software: -// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd -// http://www.ocean-logic.com -// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc -// Modifications (C) 2010 Shankar Giri -// Modifications Copyright (C) 2002-2023 Larry Doolittle -// http://doolittle.icarus.com/~larry/vhd2vl/ -// Modifications (C) 2017 Rodrigo A. Melo -// -// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting -// Verilog for correctness, ideally with a formal verification tool. -// -// You are welcome to redistribute vhd2vl under certain conditions. -// See the license (GPLv2) file included with the source for details. - -// The result of translation follows. Its copyright status should be -// considered unchanged from the original VHDL. // ################################################################################################# // # << NEORV32 - Example setup for boards with UP5K devices >> #