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FPGALover 2024-02-28 15:30:16 -08:00
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114
rtl/processor_templates/neorv32_ProcessorTop_Minimal.v 100644
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// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 2001
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002-2023 Larry Doolittle
// http://doolittle.icarus.com/~larry/vhd2vl/
// Modifications (C) 2017 Rodrigo A. Melo
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// #################################################################################################
// # << NEORV32 - Minimal setup without a bootloader >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
// no timescale needed
module neorv32_ProcessorTop_Minimal(
input wire clk_i,
input wire rstn_i,
output wire [IO_PWM_NUM_CH - 1:0] pwm_o
);
// General --
parameter [31:0] CLOCK_FREQUENCY=0;
parameter MEM_INT_IMEM_EN=true;
parameter [31:0] MEM_INT_IMEM_SIZE=8 * 1024;
parameter MEM_INT_DMEM_EN=true;
parameter [31:0] MEM_INT_DMEM_SIZE=64 * 1024;
parameter [31:0] IO_PWM_NUM_CH=3;
// number of PWM channels to implement (0..12); 0 = disabled
// Global control --
// PWM (available if IO_PWM_NUM_CH > 0) --
// internal IO connection --
wire [11:0] con_pwm_o;
// The core of the problem ----------------------------------------------------------------
// -------------------------------------------------------------------------------------------
neorv32_top #(
// General --
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
// clock frequency of clk_i in Hz
.INT_BOOTLOADER_EN(false),
// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
// Internal Instruction memory --
.MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
// implement processor-internal instruction memory
.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
// size of processor-internal instruction memory in bytes
// Internal Data memory --
.MEM_INT_DMEM_EN(MEM_INT_DMEM_EN),
// implement processor-internal data memory
.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
// size of processor-internal data memory in bytes
// Processor peripherals --
.IO_MTIME_EN(true),
// implement machine system timer (MTIME)?
.IO_PWM_NUM_CH(IO_PWM_NUM_CH))
neorv32_inst(
// Global control --
.clk_i(clk_i),
// global clock, rising edge
.rstn_i(rstn_i),
// global reset, low-active, async
// PWM (available if IO_PWM_NUM_CH > 0) --
.pwm_o(con_pwm_o));
// PWM --
assign pwm_o = con_pwm_o[IO_PWM_NUM_CH - 1:0];
endmodule

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rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.v 100644
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// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 2001
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002-2023 Larry Doolittle
// http://doolittle.icarus.com/~larry/vhd2vl/
// Modifications (C) 2017 Rodrigo A. Melo
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// #################################################################################################
// # << NEORV32 - Minimal setup with the bootloader enabled >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
// no timescale needed
module neorv32_ProcessorTop_MinimalBoot(
input wire clk_i,
input wire rstn_i,
output wire [3:0] gpio_o,
output wire uart_txd_o,
input wire uart_rxd_i,
output wire [IO_PWM_NUM_CH - 1:0] pwm_o
);
// General --
parameter [31:0] CLOCK_FREQUENCY=0;
parameter MEM_INT_IMEM_EN=true;
parameter [31:0] MEM_INT_IMEM_SIZE=64 * 1024;
parameter MEM_INT_DMEM_EN=true;
parameter [31:0] MEM_INT_DMEM_SIZE=64 * 1024;
parameter [31:0] IO_GPIO_NUM=0;
parameter [31:0] IO_PWM_NUM_CH=3;
// number of PWM channels to implement (0..12); 0 = disabled
// Global control --
// GPIO (available if IO_GPIO_EN = true) --
// primary UART0 (available if IO_UART0_EN = true) --
// UART0 send data
// UART0 receive data
// PWM (available if IO_PWM_NUM_CH > 0) --
// internal IO connection --
wire [63:0] con_gpio_o;
wire [11:0] con_pwm_o;
// The core of the problem ----------------------------------------------------------------
// -------------------------------------------------------------------------------------------
neorv32_top #(
// General --
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
// clock frequency of clk_i in Hz
.INT_BOOTLOADER_EN(true),
// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
// Internal Instruction memory --
.MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
// implement processor-internal instruction memory
.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
// size of processor-internal instruction memory in bytes
// Internal Data memory --
.MEM_INT_DMEM_EN(MEM_INT_DMEM_EN),
// implement processor-internal data memory
.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
// size of processor-internal data memory in bytes
// Processor peripherals --
.IO_GPIO_NUM(IO_GPIO_NUM),
// number of GPIO input/output pairs (0..64)
.IO_MTIME_EN(true),
// implement machine system timer (MTIME)?
.IO_UART0_EN(true),
// implement primary universal asynchronous receiver/transmitter (UART0)?
.IO_PWM_NUM_CH(IO_PWM_NUM_CH))
neorv32_inst(
// Global control --
.clk_i(clk_i),
// global clock, rising edge
.rstn_i(rstn_i),
// global reset, low-active, async
// GPIO (available if IO_GPIO_NUM > 0) --
.gpio_o(con_gpio_o),
// parallel output
.gpio_i({broken{0}}),
// parallel input
// primary UART0 (available if IO_UART0_EN = true) --
.uart0_txd_o(uart_txd_o),
// UART0 send data
.uart0_rxd_i(uart_rxd_i),
// UART0 receive data
// PWM (available if IO_PWM_NUM_CH > 0) --
.pwm_o(con_pwm_o));
// GPIO --
assign gpio_o = con_gpio_o[3:0];
// PWM --
assign pwm_o = con_pwm_o[IO_PWM_NUM_CH - 1:0];
endmodule

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rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v 100644
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// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 2001
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002-2023 Larry Doolittle
// http://doolittle.icarus.com/~larry/vhd2vl/
// Modifications (C) 2017 Rodrigo A. Melo
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// #################################################################################################
// # << NEORV32 - Example setup for boards with UP5K devices >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
// no timescale needed
module neorv32_ProcessorTop_UP5KDemo(
input wire clk_i,
input wire rstn_i,
input wire [3:0] gpio_i,
output wire [3:0] gpio_o,
output wire uart_txd_o,
input wire uart_rxd_i,
output wire flash_sck_o,
output wire flash_sdo_o,
input wire flash_sdi_i,
output wire flash_csn_o,
output wire spi_sck_o,
output wire spi_sdo_o,
input wire spi_sdi_i,
output wire spi_csn_o,
inout wire twi_sda_io,
inout wire twi_scl_io,
output wire [IO_PWM_NUM_CH - 1:0] pwm_o
);
// General --
parameter [31:0] CLOCK_FREQUENCY=0;
parameter MEM_INT_IMEM_EN=true;
parameter [31:0] MEM_INT_IMEM_SIZE=64 * 1024;
parameter MEM_INT_DMEM_EN=true;
parameter [31:0] MEM_INT_DMEM_SIZE=64 * 1024;
parameter [31:0] IO_GPIO_NUM=64;
parameter [31:0] IO_PWM_NUM_CH=3;
// number of PWM channels to implement (0..12); 0 = disabled
// Global control --
// GPIO (available if IO_GPIO_NUM > 0) --
// primary UART0 (available if IO_UART0_EN = true) --
// UART0 send data
// UART0 receive data
// SPI to on-board flash --
// NEORV32.SPI_CS(0)
// SPI (available if IO_SPI_EN = true) --
// NEORV32.SPI_CS(1)
// TWI (available if IO_TWI_EN = true) --
// PWM (available if IO_PWM_NUM_CH > 0) --
// internal IO connection --
wire [63:0] con_gpio_o;
wire [63:0] con_gpio_i;
wire [11:0] con_pwm_o;
wire con_spi_sck;
wire con_spi_sdi;
wire con_spi_sdo;
wire [7:0] con_spi_csn;
wire con_twi_sda_i;
wire con_twi_sda_o;
wire con_twi_scl_i;
wire con_twi_scl_o;
// The core of the problem ----------------------------------------------------------------
// -------------------------------------------------------------------------------------------
neorv32_top #(
// General --
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
// clock frequency of clk_i in Hz
.INT_BOOTLOADER_EN(true),
// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
// RISC-V CPU Extensions --
.CPU_EXTENSION_RISCV_M(true),
// implement mul/div extension?
.CPU_EXTENSION_RISCV_U(true),
// implement user mode extension?
.CPU_EXTENSION_RISCV_Zicntr(true),
// implement base counters?
// Internal Instruction memory --
.MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
// implement processor-internal instruction memory
.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
// size of processor-internal instruction memory in bytes
// Internal Data memory --
.MEM_INT_DMEM_EN(MEM_INT_DMEM_EN),
// implement processor-internal data memory
.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
// size of processor-internal data memory in bytes
// Processor peripherals --
.IO_GPIO_NUM(IO_GPIO_NUM),
// number of GPIO input/output pairs (0..64)
.IO_MTIME_EN(true),
// implement machine system timer (MTIME)?
.IO_UART0_EN(true),
// implement primary universal asynchronous receiver/transmitter (UART0)?
.IO_SPI_EN(true),
// implement serial peripheral interface (SPI)?
.IO_TWI_EN(true),
// implement two-wire interface (TWI)?
.IO_PWM_NUM_CH(IO_PWM_NUM_CH))
neorv32_inst(
// Global control --
.clk_i(clk_i),
// global clock, rising edge
.rstn_i(rstn_i),
// global reset, low-active, async
// GPIO (available if IO_GPIO_NUM > 0) --
.gpio_o(con_gpio_o),
// parallel output
.gpio_i(con_gpio_i),
// parallel input
// primary UART0 (available if IO_UART0_EN = true) --
.uart0_txd_o(uart_txd_o),
// UART0 send data
.uart0_rxd_i(uart_rxd_i),
// UART0 receive data
// TWI (available if IO_TWI_EN = true) --
.twi_sda_i(con_twi_sda_i),
// serial data line sense input
.twi_sda_o(con_twi_sda_o),
// serial data line output (pull low only)
.twi_scl_i(con_twi_scl_i),
// serial clock line sense input
.twi_scl_o(con_twi_scl_o),
// serial clock line output (pull low only)
// PWM (available if IO_PWM_NUM_CH > 0) --
.pwm_o(con_pwm_o));
// SPI: on-board flash --
assign flash_sck_o = con_spi_sck;
assign flash_sdo_o = con_spi_sdo;
assign flash_csn_o = con_spi_csn[0];
// SPI: user port --
assign spi_sck_o = con_spi_sck;
assign spi_sdo_o = con_spi_sdo;
assign spi_csn_o = con_spi_csn[1];
assign con_spi_sdi = (con_spi_csn[0] == 1'b0) ? flash_sdi_i : spi_sdi_i;
// GPIO --
assign gpio_o = con_gpio_o[3:0];
assign con_gpio_i[3:0] = gpio_i;
assign con_gpio_i[63:4] = {60{1'b0}};
// PWM --
assign pwm_o = con_pwm_o[IO_PWM_NUM_CH - 1:0];
// TWI tri-state driver --
assign twi_sda_io = (con_twi_sda_o == 1'b0) ? 1'b0 : 1'bZ;
// module can only pull the line low actively
assign twi_scl_io = (con_twi_scl_o == 1'b0) ? 1'b0 : 1'bZ;
assign con_twi_sda_i = twi_sda_io;
assign con_twi_scl_i = twi_scl_io;
endmodule