top templates on Verilog HDL
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// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
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// vhd2vl settings:
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// * Verilog Module Declaration Style: 2001
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// vhd2vl is Free (libre) Software:
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// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
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// http://www.ocean-logic.com
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// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
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// Modifications (C) 2010 Shankar Giri
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// Modifications Copyright (C) 2002-2023 Larry Doolittle
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// http://doolittle.icarus.com/~larry/vhd2vl/
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// Modifications (C) 2017 Rodrigo A. Melo
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//
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// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
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// Verilog for correctness, ideally with a formal verification tool.
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//
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// You are welcome to redistribute vhd2vl under certain conditions.
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// See the license (GPLv2) file included with the source for details.
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// The result of translation follows. Its copyright status should be
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// considered unchanged from the original VHDL.
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// #################################################################################################
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// # << NEORV32 - Minimal setup without a bootloader >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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||||||
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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||||||
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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||||||
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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||||||
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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||||||
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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// no timescale needed
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module neorv32_ProcessorTop_Minimal(
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input wire clk_i,
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input wire rstn_i,
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output wire [IO_PWM_NUM_CH - 1:0] pwm_o
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);
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// General --
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parameter [31:0] CLOCK_FREQUENCY=0;
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parameter MEM_INT_IMEM_EN=true;
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parameter [31:0] MEM_INT_IMEM_SIZE=8 * 1024;
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parameter MEM_INT_DMEM_EN=true;
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parameter [31:0] MEM_INT_DMEM_SIZE=64 * 1024;
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parameter [31:0] IO_PWM_NUM_CH=3;
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// number of PWM channels to implement (0..12); 0 = disabled
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// Global control --
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// PWM (available if IO_PWM_NUM_CH > 0) --
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// internal IO connection --
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wire [11:0] con_pwm_o;
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// The core of the problem ----------------------------------------------------------------
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// -------------------------------------------------------------------------------------------
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neorv32_top #(
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// General --
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.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
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// clock frequency of clk_i in Hz
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.INT_BOOTLOADER_EN(false),
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// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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// Internal Instruction memory --
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.MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
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// implement processor-internal instruction memory
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.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
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// size of processor-internal instruction memory in bytes
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// Internal Data memory --
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.MEM_INT_DMEM_EN(MEM_INT_DMEM_EN),
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// implement processor-internal data memory
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.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
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// size of processor-internal data memory in bytes
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// Processor peripherals --
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.IO_MTIME_EN(true),
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// implement machine system timer (MTIME)?
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.IO_PWM_NUM_CH(IO_PWM_NUM_CH))
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neorv32_inst(
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// Global control --
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.clk_i(clk_i),
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// global clock, rising edge
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.rstn_i(rstn_i),
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// global reset, low-active, async
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// PWM (available if IO_PWM_NUM_CH > 0) --
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.pwm_o(con_pwm_o));
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// PWM --
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assign pwm_o = con_pwm_o[IO_PWM_NUM_CH - 1:0];
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endmodule
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@ -0,0 +1,139 @@
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// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
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// vhd2vl settings:
|
||||||
|
// * Verilog Module Declaration Style: 2001
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||||||
|
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// vhd2vl is Free (libre) Software:
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// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
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// http://www.ocean-logic.com
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// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
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// Modifications (C) 2010 Shankar Giri
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// Modifications Copyright (C) 2002-2023 Larry Doolittle
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// http://doolittle.icarus.com/~larry/vhd2vl/
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// Modifications (C) 2017 Rodrigo A. Melo
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//
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// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
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|
// Verilog for correctness, ideally with a formal verification tool.
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||||||
|
//
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||||||
|
// You are welcome to redistribute vhd2vl under certain conditions.
|
||||||
|
// See the license (GPLv2) file included with the source for details.
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||||||
|
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// The result of translation follows. Its copyright status should be
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// considered unchanged from the original VHDL.
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// #################################################################################################
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// # << NEORV32 - Minimal setup with the bootloader enabled >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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||||||
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// # permitted provided that the following conditions are met: #
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||||||
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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||||||
|
// # conditions and the following disclaimer. #
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||||||
|
// # #
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||||||
|
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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||||||
|
// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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||||||
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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||||||
|
// # endorse or promote products derived from this software without specific prior written #
|
||||||
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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||||||
|
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||||
|
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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||||||
|
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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||||||
|
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||||
|
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||||
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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||||||
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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// no timescale needed
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module neorv32_ProcessorTop_MinimalBoot(
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input wire clk_i,
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input wire rstn_i,
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output wire [3:0] gpio_o,
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output wire uart_txd_o,
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input wire uart_rxd_i,
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output wire [IO_PWM_NUM_CH - 1:0] pwm_o
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);
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// General --
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parameter [31:0] CLOCK_FREQUENCY=0;
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parameter MEM_INT_IMEM_EN=true;
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parameter [31:0] MEM_INT_IMEM_SIZE=64 * 1024;
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parameter MEM_INT_DMEM_EN=true;
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parameter [31:0] MEM_INT_DMEM_SIZE=64 * 1024;
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parameter [31:0] IO_GPIO_NUM=0;
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parameter [31:0] IO_PWM_NUM_CH=3;
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// number of PWM channels to implement (0..12); 0 = disabled
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// Global control --
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// GPIO (available if IO_GPIO_EN = true) --
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// primary UART0 (available if IO_UART0_EN = true) --
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// UART0 send data
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// UART0 receive data
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// PWM (available if IO_PWM_NUM_CH > 0) --
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// internal IO connection --
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wire [63:0] con_gpio_o;
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wire [11:0] con_pwm_o;
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// The core of the problem ----------------------------------------------------------------
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// -------------------------------------------------------------------------------------------
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neorv32_top #(
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// General --
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.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
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// clock frequency of clk_i in Hz
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.INT_BOOTLOADER_EN(true),
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// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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// Internal Instruction memory --
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.MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
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// implement processor-internal instruction memory
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.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
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// size of processor-internal instruction memory in bytes
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// Internal Data memory --
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.MEM_INT_DMEM_EN(MEM_INT_DMEM_EN),
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// implement processor-internal data memory
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.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
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// size of processor-internal data memory in bytes
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// Processor peripherals --
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.IO_GPIO_NUM(IO_GPIO_NUM),
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// number of GPIO input/output pairs (0..64)
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.IO_MTIME_EN(true),
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// implement machine system timer (MTIME)?
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.IO_UART0_EN(true),
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// implement primary universal asynchronous receiver/transmitter (UART0)?
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.IO_PWM_NUM_CH(IO_PWM_NUM_CH))
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neorv32_inst(
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// Global control --
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.clk_i(clk_i),
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// global clock, rising edge
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.rstn_i(rstn_i),
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// global reset, low-active, async
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// GPIO (available if IO_GPIO_NUM > 0) --
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.gpio_o(con_gpio_o),
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// parallel output
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.gpio_i({broken{0}}),
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// parallel input
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// primary UART0 (available if IO_UART0_EN = true) --
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.uart0_txd_o(uart_txd_o),
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// UART0 send data
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.uart0_rxd_i(uart_rxd_i),
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// UART0 receive data
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// PWM (available if IO_PWM_NUM_CH > 0) --
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.pwm_o(con_pwm_o));
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// GPIO --
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assign gpio_o = con_gpio_o[3:0];
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// PWM --
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assign pwm_o = con_pwm_o[IO_PWM_NUM_CH - 1:0];
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endmodule
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@ -0,0 +1,201 @@
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// File ../../neorv32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd translated with vhd2vl 3.0 VHDL to Verilog RTL translator
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// vhd2vl settings:
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// * Verilog Module Declaration Style: 2001
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||||||
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// vhd2vl is Free (libre) Software:
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// Copyright (C) 2001-2023 Vincenzo Liguori - Ocean Logic Pty Ltd
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// http://www.ocean-logic.com
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// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
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// Modifications (C) 2010 Shankar Giri
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// Modifications Copyright (C) 2002-2023 Larry Doolittle
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||||||
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// http://doolittle.icarus.com/~larry/vhd2vl/
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||||||
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// Modifications (C) 2017 Rodrigo A. Melo
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||||||
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//
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||||||
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// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
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||||||
|
// Verilog for correctness, ideally with a formal verification tool.
|
||||||
|
//
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||||||
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// You are welcome to redistribute vhd2vl under certain conditions.
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||||||
|
// See the license (GPLv2) file included with the source for details.
|
||||||
|
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||||||
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// The result of translation follows. Its copyright status should be
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||||||
|
// considered unchanged from the original VHDL.
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// #################################################################################################
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// # << NEORV32 - Example setup for boards with UP5K devices >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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||||||
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// # permitted provided that the following conditions are met: #
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||||||
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// # #
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||||||
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||||
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// # conditions and the following disclaimer. #
|
||||||
|
// # #
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||||||
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||||
|
// # conditions and the following disclaimer in the documentation and/or other materials #
|
||||||
|
// # provided with the distribution. #
|
||||||
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// # #
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||||||
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||||
|
// # endorse or promote products derived from this software without specific prior written #
|
||||||
|
// # permission. #
|
||||||
|
// # #
|
||||||
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||||
|
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||||
|
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||||
|
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||||
|
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||||
|
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||||
|
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||||
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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// no timescale needed
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module neorv32_ProcessorTop_UP5KDemo(
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input wire clk_i,
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input wire rstn_i,
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input wire [3:0] gpio_i,
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output wire [3:0] gpio_o,
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output wire uart_txd_o,
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input wire uart_rxd_i,
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output wire flash_sck_o,
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output wire flash_sdo_o,
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input wire flash_sdi_i,
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output wire flash_csn_o,
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output wire spi_sck_o,
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output wire spi_sdo_o,
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input wire spi_sdi_i,
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output wire spi_csn_o,
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inout wire twi_sda_io,
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inout wire twi_scl_io,
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output wire [IO_PWM_NUM_CH - 1:0] pwm_o
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);
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// General --
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parameter [31:0] CLOCK_FREQUENCY=0;
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parameter MEM_INT_IMEM_EN=true;
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parameter [31:0] MEM_INT_IMEM_SIZE=64 * 1024;
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||||||
|
parameter MEM_INT_DMEM_EN=true;
|
||||||
|
parameter [31:0] MEM_INT_DMEM_SIZE=64 * 1024;
|
||||||
|
parameter [31:0] IO_GPIO_NUM=64;
|
||||||
|
parameter [31:0] IO_PWM_NUM_CH=3;
|
||||||
|
// number of PWM channels to implement (0..12); 0 = disabled
|
||||||
|
// Global control --
|
||||||
|
// GPIO (available if IO_GPIO_NUM > 0) --
|
||||||
|
// primary UART0 (available if IO_UART0_EN = true) --
|
||||||
|
// UART0 send data
|
||||||
|
// UART0 receive data
|
||||||
|
// SPI to on-board flash --
|
||||||
|
// NEORV32.SPI_CS(0)
|
||||||
|
// SPI (available if IO_SPI_EN = true) --
|
||||||
|
// NEORV32.SPI_CS(1)
|
||||||
|
// TWI (available if IO_TWI_EN = true) --
|
||||||
|
// PWM (available if IO_PWM_NUM_CH > 0) --
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// internal IO connection --
|
||||||
|
wire [63:0] con_gpio_o;
|
||||||
|
wire [63:0] con_gpio_i;
|
||||||
|
wire [11:0] con_pwm_o;
|
||||||
|
wire con_spi_sck;
|
||||||
|
wire con_spi_sdi;
|
||||||
|
wire con_spi_sdo;
|
||||||
|
wire [7:0] con_spi_csn;
|
||||||
|
wire con_twi_sda_i;
|
||||||
|
wire con_twi_sda_o;
|
||||||
|
wire con_twi_scl_i;
|
||||||
|
wire con_twi_scl_o;
|
||||||
|
|
||||||
|
// The core of the problem ----------------------------------------------------------------
|
||||||
|
// -------------------------------------------------------------------------------------------
|
||||||
|
neorv32_top #(
|
||||||
|
// General --
|
||||||
|
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
|
||||||
|
// clock frequency of clk_i in Hz
|
||||||
|
.INT_BOOTLOADER_EN(true),
|
||||||
|
// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
||||||
|
// RISC-V CPU Extensions --
|
||||||
|
.CPU_EXTENSION_RISCV_M(true),
|
||||||
|
// implement mul/div extension?
|
||||||
|
.CPU_EXTENSION_RISCV_U(true),
|
||||||
|
// implement user mode extension?
|
||||||
|
.CPU_EXTENSION_RISCV_Zicntr(true),
|
||||||
|
// implement base counters?
|
||||||
|
// Internal Instruction memory --
|
||||||
|
.MEM_INT_IMEM_EN(MEM_INT_IMEM_EN),
|
||||||
|
// implement processor-internal instruction memory
|
||||||
|
.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
|
||||||
|
// size of processor-internal instruction memory in bytes
|
||||||
|
// Internal Data memory --
|
||||||
|
.MEM_INT_DMEM_EN(MEM_INT_DMEM_EN),
|
||||||
|
// implement processor-internal data memory
|
||||||
|
.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
|
||||||
|
// size of processor-internal data memory in bytes
|
||||||
|
// Processor peripherals --
|
||||||
|
.IO_GPIO_NUM(IO_GPIO_NUM),
|
||||||
|
// number of GPIO input/output pairs (0..64)
|
||||||
|
.IO_MTIME_EN(true),
|
||||||
|
// implement machine system timer (MTIME)?
|
||||||
|
.IO_UART0_EN(true),
|
||||||
|
// implement primary universal asynchronous receiver/transmitter (UART0)?
|
||||||
|
.IO_SPI_EN(true),
|
||||||
|
// implement serial peripheral interface (SPI)?
|
||||||
|
.IO_TWI_EN(true),
|
||||||
|
// implement two-wire interface (TWI)?
|
||||||
|
.IO_PWM_NUM_CH(IO_PWM_NUM_CH))
|
||||||
|
neorv32_inst(
|
||||||
|
// Global control --
|
||||||
|
.clk_i(clk_i),
|
||||||
|
// global clock, rising edge
|
||||||
|
.rstn_i(rstn_i),
|
||||||
|
// global reset, low-active, async
|
||||||
|
// GPIO (available if IO_GPIO_NUM > 0) --
|
||||||
|
.gpio_o(con_gpio_o),
|
||||||
|
// parallel output
|
||||||
|
.gpio_i(con_gpio_i),
|
||||||
|
// parallel input
|
||||||
|
// primary UART0 (available if IO_UART0_EN = true) --
|
||||||
|
.uart0_txd_o(uart_txd_o),
|
||||||
|
// UART0 send data
|
||||||
|
.uart0_rxd_i(uart_rxd_i),
|
||||||
|
// UART0 receive data
|
||||||
|
// TWI (available if IO_TWI_EN = true) --
|
||||||
|
.twi_sda_i(con_twi_sda_i),
|
||||||
|
// serial data line sense input
|
||||||
|
.twi_sda_o(con_twi_sda_o),
|
||||||
|
// serial data line output (pull low only)
|
||||||
|
.twi_scl_i(con_twi_scl_i),
|
||||||
|
// serial clock line sense input
|
||||||
|
.twi_scl_o(con_twi_scl_o),
|
||||||
|
// serial clock line output (pull low only)
|
||||||
|
// PWM (available if IO_PWM_NUM_CH > 0) --
|
||||||
|
.pwm_o(con_pwm_o));
|
||||||
|
|
||||||
|
// SPI: on-board flash --
|
||||||
|
assign flash_sck_o = con_spi_sck;
|
||||||
|
assign flash_sdo_o = con_spi_sdo;
|
||||||
|
assign flash_csn_o = con_spi_csn[0];
|
||||||
|
// SPI: user port --
|
||||||
|
assign spi_sck_o = con_spi_sck;
|
||||||
|
assign spi_sdo_o = con_spi_sdo;
|
||||||
|
assign spi_csn_o = con_spi_csn[1];
|
||||||
|
assign con_spi_sdi = (con_spi_csn[0] == 1'b0) ? flash_sdi_i : spi_sdi_i;
|
||||||
|
// GPIO --
|
||||||
|
assign gpio_o = con_gpio_o[3:0];
|
||||||
|
assign con_gpio_i[3:0] = gpio_i;
|
||||||
|
assign con_gpio_i[63:4] = {60{1'b0}};
|
||||||
|
// PWM --
|
||||||
|
assign pwm_o = con_pwm_o[IO_PWM_NUM_CH - 1:0];
|
||||||
|
// TWI tri-state driver --
|
||||||
|
assign twi_sda_io = (con_twi_sda_o == 1'b0) ? 1'b0 : 1'bZ;
|
||||||
|
// module can only pull the line low actively
|
||||||
|
assign twi_scl_io = (con_twi_scl_o == 1'b0) ? 1'b0 : 1'bZ;
|
||||||
|
assign con_twi_sda_i = twi_sda_io;
|
||||||
|
assign con_twi_scl_i = twi_scl_io;
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
Reference in New Issue