5 Commits (e12e594b5145a044e2087665e01c1e0edd516883)

Author	SHA1	Message	Date
FPGALover	9cf19a00ce	Update rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.v	2024-02-28 23:31:44 +00:00
FPGALover	93d7845bd1	Update rtl/processor_templates/neorv32_ProcessorTop_Minimal.v	2024-02-28 23:31:33 +00:00
FPGALover	bcfa595309	Update rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.v	2024-02-28 23:31:15 +00:00
FPGALover	f4b7b79e07	top templates on Verilog HDL	2024-02-28 15:30:16 -08:00
FPGALover	63dd9360f3	Adding Files	2024-02-24 00:25:27 -08:00