<<< :sectnums: == Packaging the Processor as IP block for Xilinx Vivado Block Designer [start=1] . Import all the core files from `rtl/core` (including default internal memory architectures from `rtl/core/mem`) and assign them to a _new_ design library `neorv32`. . Instantiate the `rtl/system_integration/neorv32_top_axi4lite.vhd` module. . Then either directly use that module in a new block-design ("Create Block Design", right-click -> "Add Module", thats easier for a first try) or package it ("Tools", "Create and Package new IP") for the use in other projects. . Connect your AXI-peripheral directly to the core's AXI4-Interface if you only have one, or to an AXI-Interconnect (from the IP-catalog) if you have multiple peripherals. . Connect ALL the `ACLK` and `ARESETN` pins of all peripherals and interconnects to the processor's clock and reset signals to have a _unified_ clock and reset domain (easier for a first setup). . Open the "Address Editor" tab and let Vivado assign the base-addresses for the AXI-peripherals (you can modify them according to your needs). . For all FPGA-external signals (like UART signals) make all the connections you need "external" (right-click on the signal/pin -> "Make External"). . Save everything, let VIVADO create a HDL-Wrapper for the block-design and choose this as your _Top Level Design_. . Define your constraints and generate your bitstream. .Example AXI SoC using Xilinx Vivado image::neorv32_axi_soc.png[] .True Random Number Generator [IMPORTANT] The NEORV32 TRNG peripheral is enabled by default in the `neorv32_top_axi4lite` AXI wrapper. Otherwise, Vivado cannot insert the wrapper into a block design (see https://github.com/stnolting/neorv32/issues/227.). footnote:[Seems like Vivado has problem evaluating design source files that have more than two in-file sub-entities.] If the TRNG is not needed, you can disable it by double-clicking on the module's block and de-selecting "IO_TRNG_EN" after inserting the module. **Combinatorial Loops DRC error** If the TRNG is enabled it is recommended to add the following commands to the project's constraints file in order to prevent DRC errors during bitstream generation: [source,xdc] ---- set_property SEVERITY {warning} [get_drc_checks LUTLP-1] set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1] set_property ALLOW_COMBINATORIAL_LOOPS TRUE ---- [NOTE] Guide provided by GitHub user https://github.com/AWenzel83[`AWenzel83`] (see https://github.com/stnolting/neorv32/discussions/52#discussioncomment-819013). ❤️