// ################################################################################################# // # << NEORV32 - Processor Top Entity with AvalonMM Compatible Host Interface >> # // # ********************************************************************************************* # // # (c) "AvalonMM", "Qsys", "MegaWizard" and "Platform Designer" are trademarks of Intel corp. # // # ********************************************************************************************* # // # BSD 3-Clause License # // # # // # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 # // # Copyright (c) 2024, Stephan Nolting. All rights reserved. # // # # // # Redistribution and use in source and binary forms, with or without modification, are # // # permitted provided that the following conditions are met: # // # # // # 1. Redistributions of source code must retain the above copyright notice, this list of # // # conditions and the following disclaimer. # // # # // # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # // # conditions and the following disclaimer in the documentation and/or other materials # // # provided with the distribution. # // # # // # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # // # endorse or promote products derived from this software without specific prior written # // # permission. # // # # // # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # // # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # // # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # // # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # // # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # // # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # // # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # // # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # // # OF THE POSSIBILITY OF SUCH DAMAGE. # // ################################################################################################# // no timescale needed module neorv32_top_avalonmm( input wire clk_i, input wire rstn_i, input wire jtag_trst_i, input wire jtag_tck_i, input wire jtag_tdi_i, output wire jtag_tdo_o, input wire jtag_tms_i, output wire read_o, output wire write_o, input wire waitrequest_i, output wire [3:0] byteenable_o, output wire [31:0] address_o, output wire [31:0] writedata_o, input wire [31:0] readdata_i, output wire xip_csn_o, output wire xip_clk_o, input wire xip_dat_i, output wire xip_dat_o, output wire [63:0] gpio_o, input wire [63:0] gpio_i, output wire uart0_txd_o, input wire uart0_rxd_i, output wire uart0_rts_o, input wire uart0_cts_i, output wire uart1_txd_o, input wire uart1_rxd_i, output wire uart1_rts_o, input wire uart1_cts_i, output wire spi_clk_o, output wire spi_dat_o, input wire spi_dat_i, output wire [7:0] spi_csn_o, input wire twi_sda_i, output wire twi_sda_o, input wire twi_scl_i, output wire twi_scl_o, input wire onewire_i, output wire onewire_o, output wire [11:0] pwm_o, input wire [IO_CFS_IN_SIZE - 1:0] cfs_in_i, output wire [IO_CFS_OUT_SIZE - 1:0] cfs_out_o, output wire neoled_o, input wire [31:0] xirq_i, input wire mtime_irq_i, input wire msw_irq_i, input wire mext_irq_i ); // General -- parameter [31:0] CLOCK_FREQUENCY; parameter [31:0] HART_ID=32'h00000000; parameter [31:0] VENDOR_ID=32'h00000000; parameter INT_BOOTLOADER_EN=false; parameter ON_CHIP_DEBUGGER_EN=false; parameter CPU_EXTENSION_RISCV_B=false; parameter CPU_EXTENSION_RISCV_C=false; parameter CPU_EXTENSION_RISCV_E=false; parameter CPU_EXTENSION_RISCV_M=false; parameter CPU_EXTENSION_RISCV_U=false; parameter CPU_EXTENSION_RISCV_Zfinx=false; parameter CPU_EXTENSION_RISCV_Zicntr=true; parameter CPU_EXTENSION_RISCV_Zihpm=false; parameter CPU_EXTENSION_RISCV_Zmmul=false; parameter CPU_EXTENSION_RISCV_Zxcfu=false; parameter FAST_MUL_EN=false; parameter FAST_SHIFT_EN=false; parameter [31:0] PMP_NUM_REGIONS=0; parameter [31:0] PMP_MIN_GRANULARITY=4; parameter [31:0] HPM_NUM_CNTS=0; parameter [31:0] HPM_CNT_WIDTH=40; parameter MEM_INT_IMEM_EN=false; parameter [31:0] MEM_INT_IMEM_SIZE=16 * 1024; parameter MEM_INT_DMEM_EN=false; parameter [31:0] MEM_INT_DMEM_SIZE=8 * 1024; parameter ICACHE_EN=false; parameter [31:0] ICACHE_NUM_BLOCKS=4; parameter [31:0] ICACHE_BLOCK_SIZE=64; parameter [31:0] ICACHE_ASSOCIATIVITY=1; parameter DCACHE_EN=false; parameter [31:0] DCACHE_NUM_BLOCKS=4; parameter [31:0] DCACHE_BLOCK_SIZE=64; parameter XIP_EN=false; parameter XIP_CACHE_EN=false; parameter [31:0] XIP_CACHE_NUM_BLOCKS=8; parameter [31:0] XIP_CACHE_BLOCK_SIZE=256; parameter [31:0] XIRQ_NUM_CH=0; parameter [31:0] XIRQ_TRIGGER_TYPE=32'hffffffff; parameter [31:0] XIRQ_TRIGGER_POLARITY=32'hffffffff; parameter [31:0] IO_GPIO_NUM=0; parameter IO_MTIME_EN=false; parameter IO_UART0_EN=false; parameter [31:0] IO_UART0_RX_FIFO=1; parameter [31:0] IO_UART0_TX_FIFO=1; parameter IO_UART1_EN=false; parameter [31:0] IO_UART1_RX_FIFO=1; parameter [31:0] IO_UART1_TX_FIFO=1; parameter IO_SPI_EN=false; parameter [31:0] IO_SPI_FIFO=1; parameter IO_TWI_EN=false; parameter [31:0] IO_PWM_NUM_CH=0; parameter IO_WDT_EN=false; parameter IO_TRNG_EN=false; parameter [31:0] IO_TRNG_FIFO=1; parameter IO_CFS_EN=false; parameter [31:0] IO_CFS_CONFIG=32'h00000000; parameter [31:0] IO_CFS_IN_SIZE=32; parameter [31:0] IO_CFS_OUT_SIZE=32; parameter IO_NEOLED_EN=false; parameter [31:0] IO_NEOLED_TX_FIFO=1; parameter IO_GPTMR_EN=false; parameter IO_ONEWIRE_EN=false; // implement 1-wire interface (ONEWIRE)? // Global control -- // global clock, rising edge // global reset, low-active, async // JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- // low-active TAP reset (optional) // serial clock // serial data input // serial data output // mode select // AvalonMM interface // XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- // chip-select, low-active // serial clock // device data input // controller data output // GPIO (available if IO_GPIO_EN = true) -- // parallel output // parallel input // primary UART0 (available if IO_UART0_EN = true) -- // UART0 send data // UART0 receive data // HW flow control: UART0.RX ready to receive ("RTR"), low-active, optional // HW flow control: UART0.TX allowed to transmit, low-active, optional // secondary UART1 (available if IO_UART1_EN = true) -- // UART1 send data // UART1 receive data // HW flow control: UART1.RX ready to receive ("RTR"), low-active, optional // HW flow control: UART1.TX allowed to transmit, low-active, optional // SPI (available if IO_SPI_EN = true) -- // SPI serial clock // controller data out, peripheral data in // controller data in, peripheral data out // chip-select // TWI (available if IO_TWI_EN = true) -- // serial data line sense input // serial data line output (pull low only) // serial clock line sense input // serial clock line output (pull low only) // 1-Wire Interface (available if IO_ONEWIRE_EN = true) -- // 1-wire bus sense input // 1-wire bus output (pull low only) // PWM (available if IO_PWM_NUM_CH > 0) -- // pwm channels // Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- // custom CFS inputs conduit // custom CFS outputs conduit // NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- // async serial data line // External platform interrupts (available if XIRQ_NUM_CH > 0) -- // IRQ channels // CPU interrupts -- // machine timer interrupt, available if IO_MTIME_EN = false // machine software interrupt // machine external interrupt // Wishbone bus interface (available if MEM_EXT_EN = true) -- wire [2:0] wb_tag_o; // request tag wire [31:0] wb_adr_o; // address wire [31:0] wb_dat_i = 1'bU; // read data wire [31:0] wb_dat_o; // write data wire wb_we_o; // read/write wire [3:0] wb_sel_o; // byte enable wire wb_stb_o; // strobe wire wb_cyc_o; // valid cycle wire wb_ack_i = 1'bL; // transfer acknowledge wire wb_err_i = 1'bL; // transfer error neorv32_top #( // General -- .CLOCK_FREQUENCY(CLOCK_FREQUENCY), .HART_ID(HART_ID), .VENDOR_ID(VENDOR_ID), // On-Chip Debugger (OCD) -- .ON_CHIP_DEBUGGER_EN(ON_CHIP_DEBUGGER_EN), // RISC-V CPU Extensions -- .CPU_EXTENSION_RISCV_B(CPU_EXTENSION_RISCV_B), .CPU_EXTENSION_RISCV_C(CPU_EXTENSION_RISCV_C), .CPU_EXTENSION_RISCV_E(CPU_EXTENSION_RISCV_E), .CPU_EXTENSION_RISCV_M(CPU_EXTENSION_RISCV_M), .CPU_EXTENSION_RISCV_U(CPU_EXTENSION_RISCV_U), .CPU_EXTENSION_RISCV_Zfinx(CPU_EXTENSION_RISCV_Zfinx), .CPU_EXTENSION_RISCV_Zicntr(CPU_EXTENSION_RISCV_Zicntr), .CPU_EXTENSION_RISCV_Zihpm(CPU_EXTENSION_RISCV_Zihpm), .CPU_EXTENSION_RISCV_Zmmul(CPU_EXTENSION_RISCV_Zmmul), .CPU_EXTENSION_RISCV_Zxcfu(CPU_EXTENSION_RISCV_Zxcfu), // Extension Options -- .FAST_MUL_EN(FAST_MUL_EN), .FAST_SHIFT_EN(FAST_SHIFT_EN), // Physical Memory Protection (PMP) -- .PMP_NUM_REGIONS(PMP_NUM_REGIONS), .PMP_MIN_GRANULARITY(PMP_MIN_GRANULARITY), // Hardware Performance Monitors (HPM) -- .HPM_NUM_CNTS(HPM_NUM_CNTS), .HPM_CNT_WIDTH(HPM_CNT_WIDTH), // Internal Instruction memory (IMEM) -- .MEM_INT_IMEM_EN(MEM_INT_IMEM_EN), .MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE), // Internal Data memory (DMEM) -- .MEM_INT_DMEM_EN(MEM_INT_IMEM_EN), .MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE), // Internal Cache memory (iCACHE) -- .ICACHE_EN(ICACHE_EN), .ICACHE_NUM_BLOCKS(ICACHE_NUM_BLOCKS), .ICACHE_BLOCK_SIZE(ICACHE_BLOCK_SIZE), .ICACHE_ASSOCIATIVITY(ICACHE_ASSOCIATIVITY), // Internal Data Cache (dCACHE) -- .DCACHE_EN(DCACHE_EN), .DCACHE_NUM_BLOCKS(DCACHE_NUM_BLOCKS), .DCACHE_BLOCK_SIZE(DCACHE_BLOCK_SIZE), // External memory interface (WISHBONE) -- .MEM_EXT_EN(true), .MEM_EXT_TIMEOUT(0), .MEM_EXT_PIPE_MODE(false), .MEM_EXT_BIG_ENDIAN(false), .MEM_EXT_ASYNC_RX(false), .MEM_EXT_ASYNC_TX(false), // Execute in-place module (XIP) -- .XIP_EN(XIP_EN), .XIP_CACHE_EN(XIP_CACHE_EN), .XIP_CACHE_NUM_BLOCKS(XIP_CACHE_NUM_BLOCKS), .XIP_CACHE_BLOCK_SIZE(XIP_CACHE_BLOCK_SIZE), // External Interrupts Controller (XIRQ) -- .XIRQ_NUM_CH(XIRQ_NUM_CH), .XIRQ_TRIGGER_TYPE(XIRQ_TRIGGER_TYPE), .XIRQ_TRIGGER_POLARITY(XIRQ_TRIGGER_POLARITY), // Processor peripherals -- .IO_GPIO_NUM(IO_GPIO_NUM), .IO_MTIME_EN(IO_MTIME_EN), .IO_UART0_EN(IO_UART0_EN), .IO_UART0_RX_FIFO(IO_UART0_RX_FIFO), .IO_UART0_TX_FIFO(IO_UART0_TX_FIFO), .IO_UART1_EN(IO_UART1_EN), .IO_UART1_RX_FIFO(IO_UART1_RX_FIFO), .IO_UART1_TX_FIFO(IO_UART1_TX_FIFO), .IO_SPI_EN(IO_SPI_EN), .IO_SPI_FIFO(IO_SPI_FIFO), .IO_TWI_EN(IO_TWI_EN), .IO_PWM_NUM_CH(IO_PWM_NUM_CH), .IO_WDT_EN(IO_WDT_EN), .IO_TRNG_EN(IO_TRNG_EN), .IO_TRNG_FIFO(IO_TRNG_FIFO), .IO_CFS_EN(IO_CFS_EN), .IO_CFS_CONFIG(IO_CFS_CONFIG), .IO_CFS_IN_SIZE(IO_CFS_IN_SIZE), .IO_CFS_OUT_SIZE(IO_CFS_OUT_SIZE), .IO_NEOLED_EN(IO_NEOLED_EN), .IO_NEOLED_TX_FIFO(IO_NEOLED_TX_FIFO), .IO_GPTMR_EN(IO_GPTMR_EN), .IO_ONEWIRE_EN(IO_ONEWIRE_EN)) neorv32_top_map( // Global control -- .clk_i(clk_i), .rstn_i(rstn_i), // JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- .jtag_trst_i(jtag_trst_i), .jtag_tck_i(jtag_tck_i), .jtag_tdi_i(jtag_tdi_i), .jtag_tdo_o(jtag_tdo_o), .jtag_tms_i(jtag_tms_i), // Wishbone bus interface (available if MEM_EXT_EN = true) -- .wb_tag_o(wb_tag_o), .wb_adr_o(wb_adr_o), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), .wb_we_o(wb_we_o), .wb_sel_o(wb_sel_o), .wb_stb_o(wb_stb_o), .wb_cyc_o(wb_cyc_o), .wb_ack_i(wb_ack_i), .wb_err_i(wb_err_i), // XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- .xip_csn_o(xip_csn_o), .xip_clk_o(xip_clk_o), .xip_dat_i(xip_dat_i), .xip_dat_o(xip_dat_o), // GPIO (available if IO_GPIO_EN = true) -- .gpio_o(gpio_o), .gpio_i(gpio_i), // primary UART0 (available if IO_UART0_EN = true) -- .uart0_txd_o(uart0_txd_o), .uart0_rxd_i(uart0_rxd_i), .uart0_rts_o(uart0_rts_o), .uart0_cts_i(uart0_cts_i), // secondary UART1 (available if IO_UART1_EN = true) -- .uart1_txd_o(uart1_txd_o), .uart1_rxd_i(uart1_rxd_i), .uart1_rts_o(uart1_rts_o), .uart1_cts_i(uart1_cts_i), // SPI (available if IO_SPI_EN = true) -- .spi_clk_o(spi_clk_o), .spi_dat_o(spi_dat_o), .spi_dat_i(spi_dat_i), .spi_csn_o(spi_csn_o), // TWI (available if IO_TWI_EN = true) -- .twi_sda_i(twi_sda_i), .twi_sda_o(twi_sda_o), .twi_scl_i(twi_scl_i), .twi_scl_o(twi_scl_o), // 1-Wire Interface (available if IO_ONEWIRE_EN = true) -- .onewire_i(onewire_i), .onewire_o(onewire_o), // PWM (available if IO_PWM_NUM_CH > 0) -- .pwm_o(pwm_o), // Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- .cfs_in_i(cfs_in_i), .cfs_out_o(cfs_out_o), // NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- .neoled_o(neoled_o), // External platform interrupts (available if XIRQ_NUM_CH > 0) -- .xirq_i(xirq_i), // CPU interrupts -- .mtime_irq_i(mtime_irq_i), .msw_irq_i(msw_irq_i), .mext_irq_i(mext_irq_i)); // Wishbone to AvalonMM bridge assign read_o = (wb_stb_o == 1'b1 && wb_we_o == 1'b0) ? 1'b1 : 1'b0; assign write_o = (wb_stb_o == 1'b1 && wb_we_o == 1'b1) ? 1'b1 : 1'b0; assign address_o = wb_adr_o; assign writedata_o = wb_dat_o; assign byteenable_o = wb_sel_o; assign wb_dat_i = readdata_i; assign wb_ack_i = ~(waitrequest_i); assign wb_err_i = 1'b0; endmodule