// #################################################################################################
// # << NEORV32 - Test Setup using the RISC-V-compatible On-Chip Debugger >>                       #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved.                                     #
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// # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32                           #
// #################################################################################################
// no timescale needed

module neorv32_test_on_chip_debugger(
input wire clk_i,
input wire rstn_i,
input wire jtag_trst_i,
input wire jtag_tck_i,
input wire jtag_tdi_i,
output wire jtag_tdo_o,
input wire jtag_tms_i,
output wire [7:0] gpio_o,
output wire uart0_txd_o,
input wire uart0_rxd_i
);

// adapt these for your setup --
parameter [31:0] CLOCK_FREQUENCY=100000000;
parameter [31:0] MEM_INT_IMEM_SIZE=16 * 1024;
parameter [31:0] MEM_INT_DMEM_SIZE=8 * 1024;
// size of processor-internal data memory in bytes
// Global control --
// global clock, rising edge
// global reset, low-active, async
// JTAG on-chip debugger interface --
// low-active TAP reset (optional)
// serial clock
// serial data input
// serial data output
// mode select
// GPIO --
// parallel output
// UART0 --
// UART0 send data
// UART0 receive data



wire [63:0] con_gpio_o;

  // The Core Of The Problem ----------------------------------------------------------------
  // -------------------------------------------------------------------------------------------
  neorv32_top #(
      // General --
    .CLOCK_FREQUENCY(CLOCK_FREQUENCY),
    // clock frequency of clk_i in Hz
    .INT_BOOTLOADER_EN(true),
    // boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
    // On-Chip Debugger (OCD) --
    .ON_CHIP_DEBUGGER_EN(true),
    // implement on-chip debugger
    // RISC-V CPU Extensions --
    .CPU_EXTENSION_RISCV_C(true),
    // implement compressed extension?
    .CPU_EXTENSION_RISCV_M(true),
    // implement mul/div extension?
    .CPU_EXTENSION_RISCV_U(true),
    // implement user mode extension?
    .CPU_EXTENSION_RISCV_Zicntr(true),
    // implement base counters?
    // Internal Instruction memory --
    .MEM_INT_IMEM_EN(true),
    // implement processor-internal instruction memory
    .MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
    // size of processor-internal instruction memory in bytes
    // Internal Data memory --
    .MEM_INT_DMEM_EN(true),
    // implement processor-internal data memory
    .MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
    // size of processor-internal data memory in bytes
    // Processor peripherals --
    .IO_GPIO_NUM(8),
    // number of GPIO input/output pairs (0..64)
    .IO_MTIME_EN(true),
    // implement machine system timer (MTIME)?
    .IO_UART0_EN(true))
  neorv32_top_inst(
      // Global control --
    .clk_i(clk_i),
    // global clock, rising edge
    .rstn_i(rstn_i),
    // global reset, low-active, async
    // JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
    .jtag_trst_i(jtag_trst_i),
    // low-active TAP reset (optional)
    .jtag_tck_i(jtag_tck_i),
    // serial clock
    .jtag_tdi_i(jtag_tdi_i),
    // serial data input
    .jtag_tdo_o(jtag_tdo_o),
    // serial data output
    .jtag_tms_i(jtag_tms_i),
    // mode select
    // GPIO (available if IO_GPIO_NUM > 0) --
    .gpio_o(con_gpio_o),
    // parallel output
    // primary UART0 (available if IO_UART0_EN = true) --
    .uart0_txd_o(uart0_txd_o),
    // UART0 send data
    .uart0_rxd_i(uart0_rxd_i));

  // GPIO output --
  assign gpio_o = con_gpio_o[7:0];

endmodule