stnolting neorv32 RISC-V 1.9.5 The NEORV32 RISC-V Processor NEORV32 r2p0 little true true false false true true 4 false 8 32 32 read-write 0x00000000 0x00000000 CFS Custom functions subsystem CFS 0xFFFFEB00 CFS_FIRQ1 0 0x100 registers REG0User-defined0x00 REG1User-defined0x04 REG2User-defined0x08 REG3User-defined0x0C REG4User-defined0x10 REG5User-defined0x14 REG6User-defined0x18 REG7User-defined0x1C REG8User-defined0x20 REG9User-defined0x24 REG10User-defined0x28 REG11User-defined0x2C REG12User-defined0x30 REG13User-defined0x34 REG14User-defined0x38 REG15User-defined0x3C REG16User-defined0x40 REG17User-defined0x44 REG18User-defined0x48 REG19User-defined0x4C REG20User-defined0x50 REG21User-defined0x54 REG22User-defined0x58 REG23User-defined0x5C REG24User-defined0x60 REG25User-defined0x64 REG26User-defined0x68 REG27User-defined0x6C REG28User-defined0x70 REG29User-defined0x74 REG30User-defined0x78 REG31User-defined0x7C REG32User-defined0x80 REG33User-defined0x84 REG34User-defined0x88 REG35User-defined0x8C REG36User-defined0x90 REG37User-defined0x94 REG38User-defined0x98 REG39User-defined0x9C REG40User-defined0xA0 REG41User-defined0xA4 REG42User-defined0xA8 REG43User-defined0xAC REG44User-defined0xB0 REG45User-defined0xB4 REG46User-defined0xB8 REG47User-defined0xBC REG48User-defined0xC0 REG49User-defined0xC4 REG50User-defined0xC8 REG51User-defined0xCC REG52User-defined0xD0 REG53User-defined0xD4 REG54User-defined0xD8 REG55User-defined0xDC REG56User-defined0xE0 REG57User-defined0xE4 REG58User-defined0xE8 REG59User-defined0xEC REG60User-defined0xF0 REG61User-defined0xF4 REG62User-defined0xF8 REG63User-defined0xFC SDI Serial data interface controller SDI 0xFFFFF700 SDI_FIRQ11 0 0x08 registers CTRL Control register 0x00 SDI_CTRL_EN [0:0] SDI enable flag SDI_CTRL_CLR_RX [1:1] Clear RX FIFO, bit auto-clears SDI_CTRL_FIFO [7:4] Log2 of SDI FIFO size SDI_CTRL_IRQ_RX_AVAIL [15:15] Fire interrupt if RX FIFO is not empty SDI_CTRL_IRQ_RX_HALF [16:16] Fire interrupt if RX FIFO is at least half full SDI_CTRL_IRQ_RX_FULL [17:17] Fire interrupt if RX FIFO is full SDI_CTRL_IRQ_TX_EMPTY [18:18] Fire interrupt if TX FIFO is empty SDI_CTRL_RX_AVAIL [23:23] read-only RX FIFO not empty (data available) SDI_CTRL_RX_HALF [24:24] read-only RX FIFO at least half full SDI_CTRL_RX_FULL [25:25] read-only RX FIFO full SDI_CTRL_TX_EMPTY [26:26] read-only TX FIFO empty SDI_CTRL_TX_FULL [27:27] read-only TX FIFO full DATA RX/TX data register (lowest 8 bit) 0x04 SLINK Stream Link Interface SLINK 0xFFFFEC00 SLINK_FIRQ14 0 0x10 registers CTRL Control register 0x00 SLINK_CTRL_EN [0:0] SLINK enable flag SLINK_CTRL_RX_CLR [1:1] Clear RX FIFO (auto-clears) SLINK_CTRL_TX_CLR [2:2] Clear TX FIFO (auto-clears) SLINK_CTRL_RX_LAST [4:4] RX link end-of-stream delimiter SLINK_CTRL_RX_EMPTY [8:8] read-only RX FIFO empty SLINK_CTRL_RX_HALF [9:9] read-only RX FIFO at least half full SLINK_CTRL_RX_FULL [10:10] read-only RX FIFO full SLINK_CTRL_TX_EMPTY [11:11] read-only TX FIFO empty SLINK_CTRL_TX_HALF [12:12] read-only TX FIFO at least half full SLINK_CTRL_TX_FULL [13:13] read-only TX FIFO full SLINK_CTRL_IRQ_RX_NEMPTY [16:16] IRQ if RX FIFO not empty SLINK_CTRL_IRQ_RX_HALF [17:17] IRQ if RX FIFO at least half full SLINK_CTRL_IRQ_RX_FULL [18:18] IRQ if RX FIFO full SLINK_CTRL_IRQ_TX_EMPTY [19:19] IRQ if TX FIFO empty SLINK_CTRL_IRQ_TX_NHALF [20:20] IRQ if TX FIFO not at least half full SLINK_CTRL_IRQ_TX_NFULL [21:21] IRQ if TX FIFO not full SLINK_CTRL_RX_FIFO [27:24] read-only log2(RX FIFO size) SLINK_CTRL_TX_FIFO [31:28] read-only log2(TX FIFO size) RX_DATA RX link receive data read-only 0x04 TX_DATA TX link transmit data 0x08 TX_DATA_LAST TX link transmit data (plus end-of-stream delimiter) 0x0c DMA Direct memory access controller DMA 0xFFFFED00 DMA_FIRQ10 0 0x10 registers CTRL Control register 0x00 DMA_CTRL_EN [0:0] DMA enable flag DMA_CTRL_AUTO [1:1] Enable automatic transfer trigger (FIRQ-triggered) DMA_CTRL_FENCE [2:2] Issue a downstream FENCE operation when DMA transfer completes (without errors) DMA_CTRL_ERROR_RD [8:8] read-only Error during last read access DMA_CTRL_ERROR_WR [9:9] read-only Error during last write access DMA_CTRL_BUSY [10:10] read-only DMA transfer in progress DMA_CTRL_DONE [11:11] DMA transfer done; auto-clears on write access DMA_CTRL_FIRQ_MASK [31:16] FIRQ trigger mask SRC_BASE Source base address; shows the last accessed read address on read access 0x04 DST_BASE Destination base address; shows the last accessed write address on read access 0x08 TTYPE Destination base address; shows the last accessed write address on read access 0x0c DMA_TTYPE_NUM [23:0] Number of elements to transfer DMA_TTYPE_QSEL [28:27] Data quantity select DMA_TTYPE_SRC_INC [29:29] Source constant (0) or incrementing (1) address DMA_TTYPE_DST_INC [30:30] Destination constant (0) or incrementing (1) address DMA_TTYPE_ENDIAN [31:31] Convert Endianness when set CRC Cyclic redundancy check unit CRC 0xFFFFEE00 0 0x10 registers MODE CRC mode control (CRC8, CRC16, CRC32) 0x00 POLY CRC polynomial 0x04 DATA LSB-aligned data input (bytes) 0x08 SREG CRC shift register 0x0c PWM Pulse-width modulation controller PWM 0xFFFFF000 0 0x10 registers CTRL Control register 0x00 PWM_CTRL_EN [0:0] PWM controller enable flag PWM_CTRL_PRSCx [3:1] Clock prescaler select DC[0] Duty cycle register 0 0x04 DC[1] Duty cycle register 1 0x08 DC[2] Duty cycle register 2 0x0C XIP Execute In Place Module CIP 0xFFFFEF00 0 0x10 registers CTRL Control register 0x00 XIP_CTRL_EN [0:0] XIP module enable flag XIP_CTRL_PRSC [3:1] SPI clock prescaler select XIP_CTRL_CPOL [4:4] SPI clock (idle) polarity XIP_CTRL_CPHA [5:5] SPI clock phase XIP_CTRL_SPI_NBYTES [9:6] Number of bytes in SPI transmission XIP_CTRL_XIP_EN [10:10] XIP mode enable XIP_CTRL_XIP_ABYTES [12:11] Number of XIP address bytes (minus 1) XIP_CTRL_RD_CMD [20:13] SPI flash read command XIP_CTRL_SPI_CSEN [21:21] SPI chip-select enable XIP_CTRL_HIGHSPEED [22:22] SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) XIP_CTRL_CDIV [23:26] SPI clock divider XIP_CTRL_BURST_EN [29:29] read-only Busr mode enabled (when cache is implemented) XIP_CTRL_PHY_BUSY [30:30] read-only SPI PHY busy XIP_CTRL_XIP_BUSY [31:31] read-only XIP access in progress DATA_LO Direct SPI access - data register low 0x08 DATA_HI Direct SPI access - data register high 0x0C GPTMR General purpose timer GPTMR 0xFFFFF100 GPTMR_FIRQ12 0 0x10 registers CTRL Control register 0x00 GPTMR_CTRL_EN [0:0] Timer enable flag GPTMR_CTRL_PRSC [3:1] Clock prescaler select GPTMR_CTRL_IRQM [4:4] Enable interrupt on timer match GPTMR_CTRL_IRQC [5:5] Enable interrupt on capture trigger GPTMR_CTRL_RISE [6:6] Capture on rising edge; capture-mode only GPTMR_CTRL_FALL [7:7] Capture on falling edge; capture-mode only GPTMR_CTRL_FILTER [8:8] Filter capture input; capture-mode only GPTMR_CTRL_TRIGM [30:30] Timer-match has fired, cleared by writing 0 GPTMR_CTRL_TRIGC [31:31] Capture-trigger has fired, cleared by writing THRES Threshold register 0x04 COUNT Counter register 0x08 CAPTURE Capture register 0x0C read-only ONEWIRE 1-Wire Interface Controller ONEWIRE 0xFFFFF200 ONEWIRE_FIRQ13 0 0x08 registers CTRL Control register 0x00 ONEWIRE_CTRL_EN [0:0] ONEWIRE controller enable ONEWIRE_CTRL_PRSC [2:1] Clock prescaler select ONEWIRE_CTRL_CLKDIV [10:3] Clock divider ONEWIRE_CTRL_TRIG_RST [11:11] Trigger reset pulse and presence detect operation, auto-clears ONEWIRE_CTRL_TRIG_BIT [12:12] Trigger single-bit transmission operation, auto-clears ONEWIRE_CTRL_TRIG_BYTE [13:13] Trigger full-byte transmission operation, auto-clears ONEWIRE_CTRL_SENSE [29:29] read-only Current state of the 1-wire bus line ONEWIRE_CTRL_PRESENCE [30:30] read-only Set if device(s) found during presence detect phase ONEWIRE_CTRL_BUSY [31:31] read-only Operation in progress when set DATA Read/write transmission data register 0x04 ONEWIRE_DATA [7:0] RTX data, transmitted LSB-first XIRQ External interrupts controller XIRQ 0xFFFFF300 XIRQ_FIRQ8 0 0x10 registers IER IRQ input enable register 0x00 IPR IRQ pending/ack/clear register 0x04 SCR IRQ source register 0x08 MTIME Machine timer MTIME 0xFFFFF400 0 0x10 registers TIME_LO System time register - low 0x00 TIME_HI System time register - high 0x04 TIMECMP_LO Time compare register - low 0x08 TIMECMP_HI Time compare register - high 0x0C UART0 Primary universal asynchronous receiver and transmitter UART0 0xFFFFF500 UART0_RX_FIRQ2 UART0_TX_FIRQ3 0 0x08 registers CTRL Control register 0x00 UART_CTRL_EN [0:0] UART enable flag UART_CTRL_SIM_MODE [1:1] Simulation output override enable, for use in simulation only UART_CTRL_HWFC_EN [2:2] Enable RTS/CTS hardware flow-control UART_CTRL_PRSC [5:3] CLock prescaler select UART_CTRL_BAUD [15:6] BAUD rate divisor UART_CTRL_RX_NEMPTY [16:16] read-only RX FIFO not empty UART_CTRL_RX_HALF [17:17] read-only RX FIFO at least half full UART_CTRL_RX_FULL [18:18] read-only RX FIFO full UART_CTRL_TX_EMPTY [19:19] read-only TX FIFO empty UART_CTRL_TX_NHALF [20:20] read-only TX FIFO not at least half full UART_CTRL_TX_FULL [21:21] read-only TX FIFO full UART_CTRL_IRQ_RX_NEMPTY [22:22] Fire IRQ if RX FIFO not empty UART_CTRL_IRQ_RX_HALF [23:23] Fire IRQ if RX FIFO at least half-full UART_CTRL_IRQ_RX_FULL [24:24] Fire IRQ if RX FIFO full UART_CTRL_IRQ_TX_EMPTY [25:25] Fire IRQ if TX FIFO empty UART_CTRL_IRQ_TX_NHALF [26:26] Fire IRQ if TX FIFO not at least half-full UART_CTRL_RX_OVER [30:30] read-only RX FIFO overflow UART_CTRL_TX_BUSY [31:31] read-only Transmitter busy or TX FIFO not empty DATA RTX data register 0x04 UART1 Secondary universal asynchronous receiver and transmitter UART1 0xFFFFF600 UART1_RX_FIRQ4 UART1_TX_FIRQ5 0 0x08 registers SPI Serial peripheral interface controller SPI 0xFFFFF800 SPI_FIRQ6 0 0x08 registers CTRL Control register 0x00 SPI_CTRL_EN [0:0] SPI enable flag SPI_CTRL_CPHA [1:1] Clock phase SPI_CTRL_CPOL [2:2] Clock polarity SPI_CTRL_CS_SEL [5:3] CS select SPI_CTRL_CS_EN [6:6] Enable selected CS line SPI_CTRL_PRSC [9:7] Clock prescaler select SPI_CTRL_CDIV [13:10] SPI clock divider SPI_CTRL_HIGHSPEED [14:14] SPI high-speed mode SPI_CTRL_RX_AVAIL [16:16] read-only RX FIFO data available (RX FIFO not empty) SPI_CTRL_TX_EMPTY [17:17] read-only TX FIFO is empty SPI_CTRL_TX_NHALF [18:18] read-only TX FIFO not at least half full SPI_CTRL_TX_FULL [19:19] read-only TX FIFO is full SPI_CTRL_IRQ_RX_AVAIL [20:20] Fire interrupt if RX FIFO is not empty SPI_CTRL_IRQ_TX_EMPTY [21:21] Fire interrupt if TX FIFO is empty SPI_CTRL_IRQ_TX_NHALF [22:22] Fire interrupt if TX FIFO is not at least half full SPI_CTRL_FIFO [26:23] read-only log2(FIFO size) SPI_CTRL_BUSY [31:31] read-only SPI busy flag DATA Data register 0x04 TWI Two-wire interface controller SPI 0xFFFFF900 TWI_FIRQ7 0 0x08 registers CTRL Control register 0x00 TWI_CTRL_EN [0:0] TWI enable flag TWI_CTRL_START [1:1] Generate START condition, auto-clears TWI_CTRL_STOP [2:2] Generate STOP condition, auto-clears TWI_CTRL_MACK [3:3] Generate ACK by controller for each transmission TWI_CTRL_CSEN [4:4] Allow clock stretching when set TWI_CTRL_PRSC [7:5] Clock prescaler select TWI_CTRL_CDIV [11:8] TWI clock divider TWI_CTRL_CLAIMED [29:29] read-only Set if the TWI bus is currently claimed by any controller TWI_CTRL_ACK [30:30] read-only ACK received when set TWI_CTRL_BUSY [31:31] read-only Transfer in progress, busy flag DATA RX/TX data register 0x04 TWI_DATA [7:0] RX/TX data TRNG True random number generator TRNG 0xFFFFFA00 0 0x04 registers CTRL Control and data register 0x00 TRNG_CTRL_DATA [7:0] read-only Random data TRNG_CTRL_FIFO [19:16] read-only Log2(FIFO size) TRNG_CTRL_IRQ_FIFO_NEMPTY [25:25] IRQ if FIFO is not empty TRNG_CTRL_IRQ_FIFO_HALF [26:26] IRQ if FIFO is at least half full TRNG_CTRL_IRQ_FIFO_FULL [27:27] IRQ if FIFO is full TRNG_CTRL_FIFO_CLR [28:28] Clear data FIFO when set (auto clears) TRNG_CTRL_SIM_MODE [29:29] read-only TRNG simulation mode (PRNG!) active TRNG_CTRL_EN [30:30] TRNG enable flag TRNG_CTRL_VALID [31:31] read-only Random data output valid WDT Watchdog timer WDT 0xFFFFFB00 WDT_FIRQ0 0 0x08 registers CTRL Control register 0x00 WDT_CTRL_EN [0:0] WDT enable flag WDT_CTRL_LOCK [1:1] Lock write access to control register, clears on reset (HW or WDT) only WDT_CTRL_DBEN [2:2] Allow WDT to continue operation even when in debug mode WDT_CTRL_SEN [3:3] Allow WDT to continue operation even when in sleep mode WDT_CTRL_STRICT [4:4] Force hardware reset if reset password is incorrect or if write attempt to locked CTRL register WDT_CTRL_RCAUSE [6:5] read-only Cause of last system reset: 0=external reset, 1=OCD reset, 2=WDT reset WDT_CTRL_TIMEOUT [31:8] Timeout value RESET Watchdog reset register 0x04 WDT_RESET [31:0] Write password to reset/feed the watchdog (0x709D1AB3) GPIO General purpose input/output port GPIO 0xFFFFFC00 0 0x10 registers INPUT_LO Parallel input register - low 0x00 read-only INPUT_HI Parallel input register - high 0x04 read-only OUTPUT_LO Parallel output register - low 0x08 OUTPUT_HI Parallel output register - high 0x0C NEOLED Smart LED hardware interface NEOLED 0xFFFFFD00 NEOLED_FIRQ9 0 0x08 registers CTRL Control register 0x00 NEOLED_CTRL_EN [0:0] NEOLED enable flag NEOLED_CTRL_MODE [1:1] TX mode (0=24-bit, 1=32-bit) NEOLED_CTRL_STROBE [2:2] Strobe (0=send normal data, 1=send RESET command on data write) NEOLED_CTRL_PRSC [5:3] Clock prescaler select NEOLED_CTRL_BUFS [9:6] read-only log2(tx buffer size) NEOLED_CTRL_T_TOT [14:10] pulse-clock ticks per total period bit NEOLED_CTRL_T_ZERO_H [19:15] pulse-clock ticks per ZERO high-time NEOLED_CTRL_T_ONE_H [24:20] pulse-clock ticks per ONE high-time NEOLED_CTRL_IRQ_CONF [27:27] TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty NEOLED_CTRL_TX_EMPTY [28:28] read-only TX FIFO is empty NEOLED_CTRL_TX_HALF [29:29] read-only TX FIFO is at least half-full NEOLED_CTRL_TX_FULL [30:30] read-only TX FIFO is full NEOLED_CTRL_TX_BUSY [31:31] read-only busy flag DATA Data register 0x04 SYSINFO System configuration information memory SYSINFO 0xFFFFFE00 0 0x20 registers CLK Clock speed in Hz 0x00 read-only MEM Memory configuration (sizes) 0x04 read-only SYSINFO_MEM_0[7:0]log2(IMEM size in bytes) SYSINFO_MEM_1[15:8]log2(DMEM size in bytes) SYSINFO_MEM_2[23:16]reserved SYSINFO_MEM_3[31:24]log2(reservation set granulartiy in bytes) SOC SoC configuration 0x08 read-only SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented SYSINFO_SOC_DCACHE[6:6]Processor-internal data cache implemented SYSINFO_SOC_CLOCK_GATING[7:7]Clock gating implemented SYSINFO_SOC_IO_CRC[12:12]Cyclic redundancy check unit implemented SYSINFO_SOC_IO_SLINK[13:13]Stream link interface implemented SYSINFO_SOC_IO_DMA[14:14]Direct memory access controller implemented SYSINFO_SOC_IO_GPIO[15:15]General purpose input/output port unit implemented SYSINFO_SOC_IO_MTIME[16:16]Machine system timer implemented SYSINFO_SOC_IO_UART0[17:17]Primary universal asynchronous receiver/transmitter 0 implemented SYSINFO_SOC_IO_SPI[18:18]Serial peripheral interface implemented SYSINFO_SOC_IO_TWI[19:19]Two-wire interface implemented SYSINFO_SOC_IO_PWM[20:20]Pulse-width modulation unit implemented SYSINFO_SOC_IO_WDT[21:21]Watchdog timer implemented SYSINFO_SOC_IO_CFS[22:22]Custom functions subsystem implemented SYSINFO_SOC_IO_TRNG[23:23]True random number generator implemented SYSINFO_SOC_IO_SDI[24:24]Serial data interface implemented SYSINFO_SOC_IO_UART1[25:25]Secondary universal asynchronous receiver/transmitter 1 implemented SYSINFO_SOC_IO_NEOLED[26:26]NeoPixel-compatible smart LED interface implemented SYSINFO_SOC_IO_XIRQ[27:27]External interrupt controller implemented SYSINFO_SOC_IO_GPTMR[28:28]General purpose timer implemented SYSINFO_SOC_XIP[29:29]Execute in place module implemented SYSINFO_SOC_IO_ONEWIRE[30:30]1-wire interface controller implemented SYSINFO_SOC_OCD[31:31]On-chip debugger implemented CACHE Cache configuration 0x0C read-only SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes) SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines) SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity) SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0)