168 lines
6.8 KiB
Plaintext
168 lines
6.8 KiB
Plaintext
<<<
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:sectnums:
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== LiteX SoC Builder Support
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https://github.com/enjoy-digital/litex[LiteX] is a SoC builder framework by https://github.com/enjoy-digital[Enjoy-Digital]
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that allows easy creation of complete system-on-chip designs - including sophisticated interfaces like Ethernet, serial ATA
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and DDR memory controller. The NEORV32 has been ported to the LiteX framework to be used as central processing unit.
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The default microcontroller-like NEORV32 processor is not directly supported as all the peripherals would provide some _redundancy_.
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Instead, the LiteX port uses a _core complex wrapper_ that only includes the actual NEORV32 CPU, the instruction cache (optional),
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the RISC-V machine system timer (optional), the on-chip debugger (optional) and the internal bus infrastructure.
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The specific implementation of optional modules as well as RISC-V ISA configuration and performance optimization options are
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controlled by a single _CONFIGURATION_ option wrapped in the LiteX build flow. The Wishbone interface is used to with the
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other LiteX SoC parts.
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.Core Complex Wrapper
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[TIP]
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The NEORV32 core complex wrapper used by LiteX for integration can be found in
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`rtl/system_integration/neorv32_litex_core_complex.vhd`.
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.LiteX NEORV32 Documentation
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[TIP]
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More information can be found in the "NEORV32" section of the LiteX project wiki: https://github.com/enjoy-digital/litex/wiki/CPUs
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.Work-In-Progress 🚧
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[NOTE]
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UG: synthesis - how to create a whole NEORV32 + LiteX SoC for a FPGA +
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LiteX: debugger - the NEORV32 on-chip-debugger is not supported by the LiteX port yet +
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LiteX: external interrupt - the "RISC-V machine external interrupt" is not supported by the LiteX port yet
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=== LiteX Setup
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[start=1]
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. Install LiteX and the RISC-V compiler following the excellent quick start guide: https://github.com/enjoy-digital/litex/wiki#quick-start-guide
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. The NEORV32 port for LiteX uses GHDL and yosys for converting the VHDL files via the https://github.com/ghdl/ghdl-yosys-plugin[GHDL-yosys-plugin].
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You can download prebuilt packages for example from https://github.com/YosysHQ/fpga-toolchain, which is _no longer maintained. It is superdesed
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by https://github.com/YosysHQ/fpga-toolchain.
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. _EXPERIMENTAL:_ GHDL provides a https://ghdl.github.io/ghdl/using/Synthesis.html[synthesis options], which converts a VHDL setup into a plain-Verilog
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netlist module (not tested on LiteX yet). Check out https://github.com/stnolting/neorv32-verilog[neorv32-verilog] for more information.
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.GHDL-yosys Plugin
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[WARNING]
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If you would like to use the experimental GHDL Yosys plugin for VHDL on Linux or MacOS, you will need to set
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the `GHDL_PREFIX` environment variable. e.g. `export GHDL_PREFIX=<install_dir>/fpga-toolchain/lib/ghdl`.
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On Windows this is not necessary. +
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+
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If you are using an existing Makefile set up for ghdl-yosys-plugin and see ERROR: This version of yosys
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is built without plugin support you probably need to remove `-m ghdl` from your yosys parameters. This is
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because the plugin is typically loaded from a separate file but it is provided built into yosys in this
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package. +
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- from https://github.com/YosysHQ/fpga-toolchain +
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+
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**This means you might have to edit the call to yosys in `litex/soc/cores/cpu/neorv32/core.py`.**
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[start=3]
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. Add the `bin` folder of the ghdl-yosys-plugin to your `PATH` environment variable. You can test your yosys installation
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and check for the GHDL plugin:
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[source, bash]
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----
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$ yosys -H
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.10+12 (open-tool-forge build) (git sha1 356ec7bb, gcc 9.3.0-17ubuntu1~20.04 -Os)
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-- Running command `help' --
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... <1>
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ghdl load VHDL designs using GHDL <2>
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...
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----
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<1> A long list of plugins...
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<2> This is the plugin we need.
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=== LiteX Simulation
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Start a simulation right in your console using the NEORV32 as target CPU:
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[source, bash]
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----
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$ litex_sim --cpu-type=neorv32
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----
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LiteX will start running its BIOS:
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[source]
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----
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__ _ __ _ __
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/ / (_) /____ | |/_/
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/ /__/ / __/ -_)> <
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/____/_/\__/\__/_/|_|
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Build your hardware, easily!
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(c) Copyright 2012-2022 Enjoy-Digital
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(c) Copyright 2007-2015 M-Labs
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BIOS built on Jul 19 2022 12:21:36
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BIOS CRC passed (6f76f1e8)
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LiteX git sha1: 0654279a
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--=============== SoC ==================--
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CPU: NEORV32-standard @ 1MHz
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BUS: WISHBONE 32-bit @ 4GiB
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CSR: 32-bit data
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ROM: 128KiB
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SRAM: 8KiB
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--============== Boot ==================--
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Booting from serial...
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Press Q or ESC to abort boot completely.
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sL5DdSMmkekro
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Timeout
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No boot medium found
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--============= Console ================--
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litex> help
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LiteX BIOS, available commands:
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flush_cpu_dcache - Flush CPU data cache
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crc - Compute CRC32 of a part of the address space
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ident - Identifier of the system
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help - Print this help
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serialboot - Boot from Serial (SFL)
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reboot - Reboot
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boot - Boot from Memory
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mem_cmp - Compare memory content
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mem_speed - Test memory speed
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mem_test - Test memory access
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mem_copy - Copy address space
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mem_write - Write address space
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mem_read - Read address space
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mem_list - List available memory regions
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litex>
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----
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You can use the provided console to execute LiteX commands.
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