149 lines
8.0 KiB
VHDL
149 lines
8.0 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> #
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-- # ********************************************************************************************* #
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-- # This memory optionally includes the in-place executable image of the application. See the #
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-- # processor's documentary to get more information. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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architecture neorv32_imem_rtl of neorv32_imem is
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-- local signals --
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signal rdata : std_ulogic_vector(31 downto 0);
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signal rden : std_ulogic;
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signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
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-- --------------------------- --
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-- IMEM as pre-initialized ROM --
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-- --------------------------- --
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-- application (image) size in bytes --
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constant imem_app_size_c : natural := (application_init_image'length)*4;
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-- ROM - initialized with executable code --
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constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);
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-- The memory (RAM) is built from 4 individual byte-wide memories because some synthesis
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-- tools have issues inferring 32-bit memories that provide dedicated byte-enable signals
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-- and/or with multi-dimensional arrays. [NOTE] Read-during-write behavior is irrelevant
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-- as read and write accesses are mutually exclusive.
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signal mem_ram_b0, mem_ram_b1, mem_ram_b2, mem_ram_b3 : mem8_t(0 to IMEM_SIZE/4-1);
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert false report
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"[NEORV32] Implementing DEFAULT processor-internal IMEM as " &
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cond_sel_string_f(IMEM_AS_IROM, "pre-initialized ROM.", "blank RAM.") severity note;
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assert not ((IMEM_AS_IROM = true) and (imem_app_size_c > IMEM_SIZE)) report
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"[NEORV32] Application (image = " & natural'image(imem_app_size_c) &
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" bytes) does not fit into processor-internal IMEM (ROM = " & natural'image(IMEM_SIZE) & " bytes)!" severity error;
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-- Implement IMEM as pre-initialized ROM --------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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imem_rom:
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if (IMEM_AS_IROM = true) generate
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mem_access: process(clk_i)
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begin
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if rising_edge(clk_i) then -- no reset to infer block RAM
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rdata <= mem_rom_c(to_integer(unsigned(addr)));
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end if;
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end process mem_access;
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end generate;
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-- word aligned access --
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addr <= bus_req_i.addr(index_size_f(IMEM_SIZE/4)+1 downto 2);
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-- Implement IMEM as non-initialized RAM --------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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imem_ram:
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if (IMEM_AS_IROM = false) generate
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mem_access: process(clk_i)
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begin
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if rising_edge(clk_i) then -- no reset to infer block RAM
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if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
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if (bus_req_i.ben(0) = '1') then -- byte 0
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mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(07 downto 00);
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end if;
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if (bus_req_i.ben(1) = '1') then -- byte 1
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mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 08);
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end if;
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if (bus_req_i.ben(2) = '1') then -- byte 2
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mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
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end if;
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if (bus_req_i.ben(3) = '1') then -- byte 3
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mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
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end if;
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end if;
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rdata(07 downto 00) <= mem_ram_b0(to_integer(unsigned(addr)));
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rdata(15 downto 08) <= mem_ram_b1(to_integer(unsigned(addr)));
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rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr)));
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rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr)));
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end if;
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end process mem_access;
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end generate;
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-- Bus Feedback ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_feedback: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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rden <= '0';
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bus_rsp_o.ack <= '0';
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elsif rising_edge(clk_i) then
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rden <= bus_req_i.stb and (not bus_req_i.rw);
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if (IMEM_AS_IROM = true) then
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bus_rsp_o.ack <= bus_req_i.stb and (not bus_req_i.rw); -- read-only!
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else
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bus_rsp_o.ack <= bus_req_i.stb;
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end if;
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end if;
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end process bus_feedback;
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bus_rsp_o.data <= rdata when (rden = '1') else (others => '0'); -- output gate
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bus_rsp_o.err <= '0'; -- no access error possible
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end neorv32_imem_rtl;
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