129 lines
6.0 KiB
VHDL
129 lines
6.0 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 #
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-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_gpio is
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generic (
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GPIO_NUM : natural range 0 to 64 -- number of GPIO input/output pairs (0..64)
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);
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port (
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active, async
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bus_req_i : in bus_req_t; -- bus request
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bus_rsp_o : out bus_rsp_t; -- bus response
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gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
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gpio_i : in std_ulogic_vector(63 downto 0) -- parallel input
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);
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end neorv32_gpio;
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architecture neorv32_gpio_rtl of neorv32_gpio is
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signal din, din_rd, dout, dout_rd : std_ulogic_vector(63 downto 0);
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begin
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-- Bus Access -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_access: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_rsp_o.ack <= '0';
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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dout <= (others => '0');
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elsif rising_edge(clk_i) then
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-- bus handshake --
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bus_rsp_o.ack <= bus_req_i.stb;
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bus_rsp_o.err <= '0';
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bus_rsp_o.data <= (others => '0');
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if (bus_req_i.stb = '1') then
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-- write access --
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if (bus_req_i.rw = '1') then
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if (bus_req_i.addr(3 downto 2) = "10") then
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dout(31 downto 00) <= bus_req_i.data;
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end if;
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if (bus_req_i.addr(3 downto 2) = "11") then
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dout(63 downto 32) <= bus_req_i.data;
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end if;
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-- read access --
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else
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case bus_req_i.addr(3 downto 2) is
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when "00" => bus_rsp_o.data <= din_rd(31 downto 00);
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when "01" => bus_rsp_o.data <= din_rd(63 downto 32);
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when "10" => bus_rsp_o.data <= dout_rd(31 downto 00);
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when others => bus_rsp_o.data <= dout_rd(63 downto 32);
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end case;
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end if;
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end if;
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end if;
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end process bus_access;
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-- Physical Pin Mapping -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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pin_mapping: process(din, dout)
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begin
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-- defaults --
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din_rd <= (others => '0');
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dout_rd <= (others => '0');
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for i in 0 to GPIO_NUM-1 loop
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din_rd(i) <= din(i);
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dout_rd(i) <= dout(i);
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end loop;
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end process pin_mapping;
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-- output --
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gpio_o <= dout_rd;
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-- synchronize input --
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input_sync: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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din <= (others => '0');
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elsif rising_edge(clk_i) then
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din <= gpio_i; -- to prevent metastability
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end if;
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end process input_sync;
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end neorv32_gpio_rtl;
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