139 lines
6.3 KiB
Verilog
139 lines
6.3 KiB
Verilog
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// #################################################################################################
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// # << NEORV32 - Test Setup using the RISC-V-compatible On-Chip Debugger >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 #
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// #################################################################################################
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// no timescale needed
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module neorv32_test_on_chip_debugger(
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input wire clk_i,
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input wire rstn_i,
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input wire jtag_trst_i,
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input wire jtag_tck_i,
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input wire jtag_tdi_i,
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output wire jtag_tdo_o,
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input wire jtag_tms_i,
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output wire [7:0] gpio_o,
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output wire uart0_txd_o,
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input wire uart0_rxd_i
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);
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// adapt these for your setup --
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parameter [31:0] CLOCK_FREQUENCY=100000000;
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parameter [31:0] MEM_INT_IMEM_SIZE=16 * 1024;
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parameter [31:0] MEM_INT_DMEM_SIZE=8 * 1024;
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// size of processor-internal data memory in bytes
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// Global control --
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// global clock, rising edge
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// global reset, low-active, async
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// JTAG on-chip debugger interface --
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// low-active TAP reset (optional)
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// serial clock
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// serial data input
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// serial data output
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// mode select
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// GPIO --
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// parallel output
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// UART0 --
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// UART0 send data
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// UART0 receive data
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wire [63:0] con_gpio_o;
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// The Core Of The Problem ----------------------------------------------------------------
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// -------------------------------------------------------------------------------------------
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neorv32_top #(
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// General --
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.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
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// clock frequency of clk_i in Hz
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.INT_BOOTLOADER_EN(true),
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// boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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// On-Chip Debugger (OCD) --
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.ON_CHIP_DEBUGGER_EN(true),
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// implement on-chip debugger
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// RISC-V CPU Extensions --
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.CPU_EXTENSION_RISCV_C(true),
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// implement compressed extension?
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.CPU_EXTENSION_RISCV_M(true),
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// implement mul/div extension?
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.CPU_EXTENSION_RISCV_U(true),
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// implement user mode extension?
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.CPU_EXTENSION_RISCV_Zicntr(true),
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// implement base counters?
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// Internal Instruction memory --
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.MEM_INT_IMEM_EN(true),
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// implement processor-internal instruction memory
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.MEM_INT_IMEM_SIZE(MEM_INT_IMEM_SIZE),
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// size of processor-internal instruction memory in bytes
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// Internal Data memory --
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.MEM_INT_DMEM_EN(true),
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// implement processor-internal data memory
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.MEM_INT_DMEM_SIZE(MEM_INT_DMEM_SIZE),
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// size of processor-internal data memory in bytes
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// Processor peripherals --
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.IO_GPIO_NUM(8),
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// number of GPIO input/output pairs (0..64)
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.IO_MTIME_EN(true),
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// implement machine system timer (MTIME)?
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.IO_UART0_EN(true))
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neorv32_top_inst(
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// Global control --
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.clk_i(clk_i),
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// global clock, rising edge
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.rstn_i(rstn_i),
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// global reset, low-active, async
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// JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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.jtag_trst_i(jtag_trst_i),
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// low-active TAP reset (optional)
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.jtag_tck_i(jtag_tck_i),
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// serial clock
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.jtag_tdi_i(jtag_tdi_i),
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// serial data input
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.jtag_tdo_o(jtag_tdo_o),
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// serial data output
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.jtag_tms_i(jtag_tms_i),
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// mode select
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// GPIO (available if IO_GPIO_NUM > 0) --
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.gpio_o(con_gpio_o),
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// parallel output
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// primary UART0 (available if IO_UART0_EN = true) --
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.uart0_txd_o(uart0_txd_o),
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// UART0 send data
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.uart0_rxd_i(uart0_rxd_i));
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// GPIO output --
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assign gpio_o = con_gpio_o[7:0];
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endmodule
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