272 lines
15 KiB
C
272 lines
15 KiB
C
// #################################################################################################
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// # << NEORV32: neorv32.h - Main Core Library File >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32.h
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* @author Stephan Nolting
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*
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* @brief Main NEORV32 core library include file.
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**************************************************************************/
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#ifndef neorv32_h
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#define neorv32_h
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Standard libraries
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#include <stdint.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <unistd.h>
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#include <stdlib.h>
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/**********************************************************************//**
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* Processor clock prescaler select
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**************************************************************************/
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enum NEORV32_CLOCK_PRSC_enum {
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CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */
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CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */
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CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */
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CLK_PRSC_64 = 3, /**< CPU_CLK (from clk_i top signal) / 64 */
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CLK_PRSC_128 = 4, /**< CPU_CLK (from clk_i top signal) / 128 */
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CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */
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CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */
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CLK_PRSC_4096 = 7 /**< CPU_CLK (from clk_i top signal) / 4096 */
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};
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/**********************************************************************//**
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* @name Fast Interrupt Requests (FIRQ) device aliases
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**************************************************************************/
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/**@{*/
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/** @name Watchdog Timer (WDT) */
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/**@{*/
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#define WDT_FIRQ_ENABLE CSR_MIE_FIRQ0E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define WDT_FIRQ_PENDING CSR_MIP_FIRQ0P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define WDT_RTE_ID RTE_TRAP_FIRQ_0 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define WDT_TRAP_CODE TRAP_CODE_FIRQ_0 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Custom Functions Subsystem (CFS) */
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/**@{*/
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#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define CFS_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Primary Universal Asynchronous Receiver/Transmitter (UART0) */
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/**@{*/
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#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_3 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Secondary Universal Asynchronous Receiver/Transmitter (UART1) */
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/**@{*/
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#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Serial Peripheral Interface (SPI) */
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/**@{*/
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#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define SPI_RTE_ID RTE_TRAP_FIRQ_6 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Two-Wire Interface (TWI) */
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/**@{*/
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#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define TWI_RTE_ID RTE_TRAP_FIRQ_7 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name External Interrupt Controller (XIRQ) */
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/**@{*/
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#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Smart LED Controller (NEOLED) */
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/**@{*/
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#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Direct Memory Access Controller (DMA) */
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/**@{*/
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#define DMA_FIRQ_ENABLE CSR_MIE_FIRQ10E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define DMA_FIRQ_PENDING CSR_MIP_FIRQ10P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define DMA_RTE_ID RTE_TRAP_FIRQ_10 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define DMA_TRAP_CODE TRAP_CODE_FIRQ_10 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Serial Data Interface (SDI) */
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/**@{*/
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#define SDI_FIRQ_ENABLE CSR_MIE_FIRQ11E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define SDI_FIRQ_PENDING CSR_MIP_FIRQ11P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define SDI_RTE_ID RTE_TRAP_FIRQ_11 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define SDI_TRAP_CODE TRAP_CODE_FIRQ_11 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name General Purpose Timer (GPTMR) */
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/**@{*/
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#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name 1-Wire Interface Controller (ONEWIRE) */
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/**@{*/
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#define ONEWIRE_FIRQ_ENABLE CSR_MIE_FIRQ13E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define ONEWIRE_FIRQ_PENDING CSR_MIP_FIRQ13P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define ONEWIRE_RTE_ID RTE_TRAP_FIRQ_13 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define ONEWIRE_TRAP_CODE TRAP_CODE_FIRQ_13 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Stream Link Interface (SLINK) */
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/**@{*/
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#define SLINK_FIRQ_ENABLE CSR_MIE_FIRQ14E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define SLINK_FIRQ_PENDING CSR_MIP_FIRQ14P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define SLINK_RTE_ID RTE_TRAP_FIRQ_14 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define SLINK_TRAP_CODE TRAP_CODE_FIRQ_14 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name True-Random Number Generator (TRNG) */
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/**@{*/
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#define TRNG_FIRQ_ENABLE CSR_MIE_FIRQ15E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define TRNG_FIRQ_PENDING CSR_MIP_FIRQ15P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define TRNG_RTE_ID RTE_TRAP_FIRQ_15 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define TRNG_TRAP_CODE TRAP_CODE_FIRQ_15 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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* @name Main Address Space Sections
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**************************************************************************/
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/**@{*/
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/** XIP-mapped memory base address */
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#define XIP_MEM_BASE_ADDRESS (0xE0000000U)
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/** bootloader memory base address */
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#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U)
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/** peripheral/IO devices memory base address */
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#define IO_BASE_ADDRESS (0xFFFFE000U)
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/**@}*/
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/**********************************************************************//**
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* @name IO Address Space - Peripheral/IO Devices
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**************************************************************************/
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/**@{*/
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#define NEORV32_CFS_BASE (0xFFFFEB00U) /**< Custom Functions Subsystem (CFS) */
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#define NEORV32_SLINK_BASE (0xFFFFEC00U) /**< Stream Link Interface (SLINK) */
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#define NEORV32_DMA_BASE (0xFFFFED00U) /**< Direct Memory Access Controller (DMA) */
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#define NEORV32_CRC_BASE (0xFFFFEE00U) /**< Cyclic Redundancy Check Unit (DMA) */
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#define NEORV32_XIP_BASE (0xFFFFEF00U) /**< Execute In Place Module (XIP) */
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#define NEORV32_PWM_BASE (0xFFFFF000U) /**< Pulse Width Modulation Controller (PWM) */
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#define NEORV32_GPTMR_BASE (0xFFFFF100U) /**< General Purpose Timer (GPTMR) */
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#define NEORV32_ONEWIRE_BASE (0xFFFFF200U) /**< 1-Wire Interface Controller (ONEWIRE) */
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#define NEORV32_XIRQ_BASE (0xFFFFF300U) /**< External Interrupt Controller (XIRQ) */
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#define NEORV32_MTIME_BASE (0xFFFFF400U) /**< Machine System Timer (MTIME) */
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#define NEORV32_UART0_BASE (0xFFFFF500U) /**< Primary Universal Asynchronous Receiver and Transmitter (UART0) */
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#define NEORV32_UART1_BASE (0xFFFFF600U) /**< Secondary Universal Asynchronous Receiver and Transmitter (UART1) */
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#define NEORV32_SDI_BASE (0xFFFFF700U) /**< Serial Data Interface (SDI) */
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#define NEORV32_SPI_BASE (0xFFFFF800U) /**< Serial Peripheral Interface Controller (SPI) */
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#define NEORV32_TWI_BASE (0xFFFFF900U) /**< Two-Wire Interface Controller (TWI) */
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#define NEORV32_TRNG_BASE (0xFFFFFA00U) /**< True Random Number Generator (TRNG) */
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#define NEORV32_WDT_BASE (0xFFFFFB00U) /**< Watchdog Timer (WDT) */
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#define NEORV32_GPIO_BASE (0xFFFFFC00U) /**< General Purpose Input/Output Port Controller (GPIO) */
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#define NEORV32_NEOLED_BASE (0xFFFFFD00U) /**< Smart LED Hardware Interface (NEOLED) */
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#define NEORV32_SYSINFO_BASE (0xFFFFFE00U) /**< System Information Memory (SYSINFO) */
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#define NEORV32_DM_BASE (0xFFFFFF00U) /**< On-Chip Debugger - Debug Module (OCD) */
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/**@}*/
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// ----------------------------------------------------------------------------
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// Include all system header files
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// ----------------------------------------------------------------------------
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// intrinsics
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#include "neorv32_intrinsics.h"
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// cpu core
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#include "neorv32_cpu.h"
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#include "neorv32_cpu_amo.h"
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#include "neorv32_cpu_csr.h"
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#include "neorv32_cpu_cfu.h"
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// NEORV32 runtime environment
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#include "neorv32_rte.h"
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// IO/peripheral devices
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#include "neorv32_cfs.h"
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#include "neorv32_crc.h"
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#include "neorv32_dm.h"
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#include "neorv32_dma.h"
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#include "neorv32_gpio.h"
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#include "neorv32_gptmr.h"
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#include "neorv32_mtime.h"
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#include "neorv32_neoled.h"
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#include "neorv32_onewire.h"
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#include "neorv32_pwm.h"
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#include "neorv32_sdi.h"
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#include "neorv32_slink.h"
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#include "neorv32_spi.h"
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#include "neorv32_sysinfo.h"
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#include "neorv32_trng.h"
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#include "neorv32_twi.h"
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#include "neorv32_uart.h"
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#include "neorv32_wdt.h"
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#include "neorv32_xip.h"
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#include "neorv32_xirq.h"
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// backwards compatibility layer
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#include "legacy.h"
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#ifdef __cplusplus
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}
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#endif
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#endif // neorv32_h
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